Efficient Methods for FFT calculations Using Memory Reduction Techniques.

Transcription

1 Efficient Methods for FFT calculations Using Memory Reduction Techniques. N. Kalaiarasi Assistant professor SRM University Kattankulathur, chennai A.Rathinam Assistant professor SRM University Kattankulathur,chennai ABSTRACT FFT algorithms is one of the many methods used for the calculation of DFT, but they are preferred due to their increased speed and higher efficiency, which arises due to the fact that for the calculation of a N-point DFT, the sequence is broken into several segments and the DFT for each segment is calculated. However, for this many redundant memory spaces are required. The Butterfly structure for the calculation of DFT by FFT algorithms is preferred due to its symmetry which makes it suitable for hardware implementations, but this requires the loading of the twiddle factors for each stage repeatedly, which leads to inefficient use of memory space. To overcome this, grouping the identical twiddle factors of different stages together reduces the number of memory references and the storage space due to twiddle factors, therein reducing the number of clock cycles needed for the complete implementation of the algorithm. Thus this can be an efficient method for the calculation of FFT algorithms. The Decimation In Time (DIT) and Decimation In Frequency (DIF) algorithms can be implemented in MATLAB- Simulink blocks to verify their accuracy and coded in C language to verify their reduction in computation time. The same can also be verified using Code composer studio (CCS) and implemented in DSP Processors for the verification of reduced clock cycles. The reduction in memory spaces and memory references of the twiddle factors is evident implicitly when compared with conventional methods. In Keywords DIT, DIF, FFT, Memory Reference, Twiddle factors. 1.INTRODUCTION Fourier transform of a signal can be found out if that function is periodic in nature, but for signals that do not fall under this category are computed by means of Discrete Fourier Transforms (DFT) method. The DFT is used to convert a finite discrete time sequence x(n) to an N point frequency domain sequence denoted by X(k). The N point DFT of a finite duration sequence x(n) of length L,where L < = N is defined as:.(1) To calculate DFT we have several algorithms available like FFT algorithms, split radix, Cooley-Turkey algorithm, combination of Decimation-in-Time (DIT) and Decimation- in-frequency (DIF) FFT algorithms, WFTA algorithms are to name a few. Out of these, FFT is widely used. Higher accuracy and reduced computational time and it can be implemented on multiple platforms are some of the advantages of FFT. The Fast Fourier Transform (FFT) is a method or algorithm for computing the DFT with reduced number of calculations. The computational efficiency is achieved if we adopt a divide and conquer approach. 2.FFT ALGORITHMS These algorithms are based on decomposition of an N point DFT into successively smaller DFTs. This basic approach leads to a family of efficient computational algorithms known collectively as FFT algorithms. The FFT algorithm works on the butterfly structure which is very much suited for hardware implementation. The FFT can be calculated in two ways. One is Decimation-in-Time domain. (DIT).and the other algorithm is Decimation-in-Frequency domain. (DIF). 2.1Decimation in Time Algorithm In Decimation in Time algorithm, the time domain sequence x(n) is decimated. The N- point DFT can be realized from 2 numbers of N/2 - point DFTs, the N/2 - point can be realized from two numbers of N/4 points DFTs, and so on. 2.2Decimation in Frequency Algorithm In Decimation in Frequency algorithm, the frequency domain sequence X(K) is decimated. The N- point time domain sequence is converted to two numbers of N/2 points sequences. Then each N/2 point sequence is converted to two numbers of N/4 point sequences. Thus, we get 4 numbers of N/4 point sequences and so on. For the calculation of both DIT and DIF a complex number is used known as twiddle factor. The complex number W n is called phase factor or twiddle factor. The W n represent a complex number 1<-2π/N or e -j2πnk/n. Hence W n has phase alone. It also represents an N th root of unity. Though the FFT s are preferred over other algorithms, yet they use up a lot of memory references due to long latencies and high power consumption. Lot of memory references are used up for loading the identical twiddle factors over and over again for different stages. Hence an efficient method is needed to minimize the memory references due to twiddle factors for implementing various different FFT Algorithms on DSP. The proposed methods first group the butterflies with identical twiddle factors from different stages in the FFT 134

2 diagrams and compute them before computing other butterflies with different twiddle factors, and it then reduces the number of look-ups required by using the symmetrical property of Twiddle Factors. As a result of which each Twiddle Factor is loaded only once and the memory references due to twiddle factors can be easily minimized, which therein reduces the computational time, storage space used up by twiddle factors, memory references of twiddle factors and the number of clock cycles 3.MEMORY REFERENCE REDUCTION METHODS The N point DFT of x(n) is given by, wherek=0,1,.,n-1..(2) This algorithm is also known as Radix-2 DIT- FFT algorithm which means the number of output points can be expressed as a power of 2,that is N=2 M, where M is an integer. In this, for a N point sequence x(n),where N is assumed to be a power of 2,the sequence is decimated into two sequences of length N/2,where one sequence consists of even - indexed values of x(n) and other of odd-indexed values of x(n). In Radix-2-DIT-FFT algorithm, the time domain N-point sequences is decimated into 2-point sequences. The result of 2-point DFTs is used to compute 4- points DFTs. Two numbers of 2-point DFT are combined to get a 4-point DFT. The results of 4-point DFTs are used to compute 8- point DFTs. Two numbers of 4-point DFTs are combined to get an 8-poin DFT. This process is continued until we get a N point DFT. In Radix-2-DIF-FFT algorithm the N-point time domain sequence is converted to two numbers of N/2 point sequences. Then each N/2 point sequences is converted to two numbers of N/4 point sequences. This process is continued until we get N/2 numbers of 2-point sequences. Now the 2-point DFTs of N/2 numbers of 2- point sequences will give N samples, which is the N-point DFT of the time domain sequence. Here the equations for forming N/2 point sequences, N/4 point sequences are obtained by decimation of frequency domain sequences. Hence this method is called DIF 3.1Summary of Steps of Radix-2 DIT-FFT Algorithm 3. The number of stages in the flow graph is given by M=log 2 N. 4. Each stage consists of N/2 butterflies. 5. Inputs/outputs for each butterfly are separated by 2 m-1 sample, where m represents the stage index, i.e., for first stage m-1 and for second stage m+2 and so on. 6. The number of complex multiplications is given by N/2 log 2 N. 7. The number of complex additions is given by N log 2 N. 8. The twiddle factor exponents are a function of the stage index m and is given by k=n t /2 m where t=0, 1, 2..2 m The number of sets or sections of butterflies in each stage is given by the formula 2 M-m. 10. The exponent repeat factor (ERF) which is the number of times the exponent sequence associated with m is repeated is given by 2 M-m. Figure 1. Butterfly structure for conventional 16-point DIT 1. The number of input samples N=2 M, where, M is an integer. 2. The input sequence is shuffled through bit-reversal.. 135

3 Figure 2. Butterfly structure for conventional 16-point DIT 3.2Summary of Steps of Radix-2 DIF-FFT Algorithm 1. The number of input samples N=2 M, where, M is an integer. 2. The input sequence is in natural order. 3. The number of stages in the flow graph is given by M=log 2 N. 4. Each stage consists of N/2 butterflies. 5. Inputs/outputs for each butterfly are separated by 2 M-m samples, where m represents the stage index, i.e., for first stage m-1 and for second stage m+2 and so on. 6. The number of complex multiplications is given by N/2 log 2 N. 7. The number of complex additions is given by N log 2 N. 8. The twiddle factor exponents are a function of the stage index m and is given by k=n t /2 M-m+1 where t=0, 1, 2..2 m MEMORY REDUCTION METHODS Memory references in digital signal processors (DSP) are expensive due to their long latencies and high power consumption. Implementing fast Fourier transform (FFT) algorithms on DSP involves many memory references to access butterfly inputs and twiddle factors. In general, a N-point radix-2 FFT diagram can be divided into log 2N stages, each of which contains a column of N/2 butterflies. Conventional FFT implementations require redundant memory references to load identical twiddle factors for butterflies from different stages in the FFT diagrams. Here we use Novel Memory Reference Reduction methods to minimize memory references due to twiddle factors for implementing various different FFT Algorithms on DSP. Figure 3. Butterfly structure for conventional 16-point DIF The proposed methods first group the butterflies with identical twiddle factors from different stages in the FFT diagrams and compute them before computing other butterflies with different twiddle factors, and it then reduces the number of look-ups required by using the symmetrical property of Twiddle Factors. As a result of which each Twiddle Factor is loaded only once and the memory references due to twiddle factors can be easily minimized, which therein reduces the computational time, storage space used up by twiddle factors, Memory references of twiddle factors and the number of clock cycles.fig.1shows the general or the conventional method for the calculation of DFT using DIT. Here the number of memory references and the computational time required is more as the identical twiddle factors are not clubbed together, neither is their symmetrical property used. For example W 0 16 occurs in stage one and also in stage four but it has not been clubbed together. But in the algorithm described seven butterflies with the twiddle factor W 4 16 can be found in Stage 2 to Stage 4 of the 16-point radix-2 DIT FFT diagram can be calculated in stage two only and they can be grouped for future stages and by using the symmetrical property the computational time can be further reduced.[1] 4.1Algorithm for Grouping Butterflies with Identical Twiddle Factors In general, an N-point radix-2 FFT diagram can be broken up into log 2N stages each of which contains a column of N/2 butterflies. The butterflies within a stage have no data dependencies with each other but have data dependencies with butterflies in other stages. For example, the butterflies in Stage 2 of the FFT diagram in Fig.7, have no data dependencies with each other but have data dependencies with butterflies in both Stage 1 and Stage

4 The butterflies in the same stage of the FFT diagram can be further partitioned into groups. Each group contains all butterflies sharing identical twiddle factors within the same stage. Particularly, the butterflies in the Stage s of the pt radix- 2 DIT FFT diagram are divided into 2 s-1 groups, while the Stage s of 16-point radix-2 DIF FFT diagram contains N/2 s groups.[3] 1. Compute the butterflies with Twiddle factors that will not occur after the stage 1 of the FFT diagram. Compute the N/2 butterflies with the twiddle factor where m=1,3,5,..({n/2} -1). 2. Compute the butterflies with Twiddle factors that will not occur after the stage 2 of the FFT diagram. This includes, N/4 butterflies in the second stage in the DIF FFT diagram and N/8 butterflies in the first stage. The twiddle factors for this are where m=2,6,10..(n/4-1)*2. 3. The butterflies with twiddle factors that will not occur after the stage s of N pt radix-2 include N/4 butterflies in the stage s, N/8 butterflies in stage s-1. and N/2 s+1. Figure 5. Dividing 16-point radix 2 DIF- FFT butterfly diagram into groups. 4. Butterflies in first stage. The twiddle factors are where m=2 s-1,3*2 s-1,5*2 s-1..,(n/2 s -1)*2 s Compute the butterflies with twiddle factors. 6. Totally N-1 butterflies with twiddle factors in an N-pt radix-2 DIF FFT diagram are computed. 7. Thus each twiddle factor is loaded only once during the computation of the N-point radix-2 DIF- FFT diagram. Figure 6. Grouping of butterflies according to identical twiddle factors in DIT- FFT diagram. Figure 4. Dividing 16-point radix 2 diagram into groups. DIT- FFT butterfly 137

5 and the number of memory references due to twiddle factors can be minimized.[4] 1. The memory references for twiddle factors are reduced by 76.4% by grouping the butterflies with identical twiddle factors, as it is evident from the grouped butterfly structure. 2. The storage space of the twiddle factors is also reduced by 53.5% using the symmetrical property of twiddle factors. 3. The C-code for the 16 point DIF-FFT gives us the reduced number of Clock Cycles. Using the above two points, it can be inferred that the computational time is reduced. The average computational time for the conventional 16 point DIF is ms, while that for the reduced 16point DIF is ms, hence the computational time is reduced by %.. Figure7. Grouping of butterflies according to identical twiddle factors in DIF- FFT diagram. 6.CONCLUSIONS Thus, by using the Novel Memory Reference Reduction Methods, the number of memory references, the storage space of twiddle factors, the computational time and the number of clock cycles are reduced, by grouping the butterflies with the identical twiddle factor, and also by using their symmetrical properties. 7.REFERENCES [1] Yuke Wang, Yiyan (Felix) Tang, Yingtao Jiang, Member, IEEE, Jin-Gyun Chung,Member, IEEE, Sang-Seob Song, Member, IEEE, and Myoung-Seob Lim, Member, IEEE Novel Memory Reference Reduction Methods for FFT Implementations on DSP Processors [2] Yi-Pin Hsu and Shin-Yu Lin Parallel-computing approach for FFT implementation on digital signal processor (DSP) [3] Mokhtar A. Aboleaze Dept. of Computer Science and Engineering York Toronto, ON. Canada Ayman I. Elnaggar Dept. of Electrical and Computer Engineering Sultan Qaboos University Muscat, Oman Reducing Memory References for FFT Calculation. [4] National Chiao Tung University, Yi-Pin Hsu and Shin-Yu Lin, Implementation of Low-Memory Reference FFT on Digital Signal Processor. Figure 8. Simulink Model of reduced 16 Point DIF-FFT 5.PERFORMANCE EVALUATION These methods propose a novel memory reference reduction technique to minimize the number of memory references due to twiddle factors in FFT implementations on DSP. The proposed methods first group the butterflies with identical twiddle factors from different stages in the FFT diagram and compute them together, and then reduce the total number of necessary twiddle factors by taking advantage from the properties of twiddle factors. Consequently, each twiddle factor is loaded only once [5] R.C.Agarwal, F.G.Gustavson, M.Zubair,IBM T.J Watson Research Centre,Yorktown Hts,NY,proceedings of the 1994 conference on super computing, A high performance algorithm for 1-D FFT. [6] D. Takahashi, IEEE Signal Process. Lett., vol. 8, no. 5, pp , May 2001 An extended split-radix FFT algorithm. [7] M. T. Heideman, H. W. Johnson, and C. S. Burrus. Prime factor algorithms for Real 8211;valued series. In Proceedings of the IEEE International Conference on 138

6 Acoustics, speech, and Signal Processing, page 28A ;4, San Diego, CA, March [10] TMS320C64x DSP Library Programmer s Reference (Rev. B), Texas Instrument, Oct. 23, 2003, SPRU565A [8] Editor: C. Sidney Burrus, Fast Fourier Transforms Collection. [9] TMS320C6000 Programmer s Guide, Texas Instruments. 139