CS 6353 Compiler Construction, Homework #3

Transcription

1 CS 6353 Compiler Construction, Homework #3 1. Consider the following attribute grammar for code generation regarding array references. (Note that the attribute grammar is the same as the one in the notes. The newtemp function returns a new temporary variable name. The name consists of a leading character t and a number. For the i-th call, the number is i. In other words, the temporary variables generated by a sequence of call to newtemp function are: t1, t2, t3,. You can start from t1. The lookup function searches the symbol table to find the corresponding id entry. The input to the function is the name of the identifier. The field arraysize is an array storing the maximum sizes of all the dimensions of the array. The field elementwidth is the size of each element in the array. The field arraydim is the number of dimensions of the array. S := E { if (.array = true and E.array = false) then emit (.place [.tn ] := E.place); } A {.array := true;.tn := A.tn;.place := A.place; } A Elist] { A.place := arrayplace; A.tn := tempn; emit (tempn := tempn elementwidth; } Elist Elist1, E { Elist.dim := Elist1.dim 1; emit (tempn := tempn arraysize[elist.dim]); emit (tempn := tempn E.place; } Elist id[e { Elist.dim := 0; arrayplace := id.name; tempn := newtemp(); addentry (tempn, ); p := lookup (id.name); arraysize := p.arrarysize; elementwidth := p.elementwidth; emit (tempn := E.place); } E id { E.place := id.name; } E num { E.place := num; } Test offset = 128 arraydim = 4 arraysize = [9, 8, 7, 6] elementwidth = 8 Consider a given input statement: Test[5, x, y, 3] := z. The entry of Test in symbol table is given in the diagram on above right. The fields for Test are given in the table. Follow the attribute grammar above and generate the three address code. t1 := 5 t1 := t1 8 t1 := t1 x t1 := t1 7 t1 := t1 y t1 := t1 6 t1 := t1 3 t1 := t1 8 Test[t1] := z

2 2. Consider the following program. for (i=2; i<=n; i) a[i] = TRUE; count = 0; s = sqrt (n); for (i=2; i<=s; i) if (a[i]) { count; for (j=2i; j<=n; j = j1) a[j] = FASE; } (a) Translate the program into three address code as defined in Section 6.2, dragon book. (1) i := 2 (2) if i > n goto (7) (3) a[i] := TRUE (4) t2 := i1 (5) i := t2 (6) goto (2) (7) count := 0 (8) s := sqrt(n) (9) i := 2 (10) if i > s goto (23) (11) if a[i]!= TRUE goto (20) (12) t4 := count 1 (13) count := t4 (14) j := 2i (15) if j > n goto (20) (16) a[j] := FASE (17) t6 := j1 (18) j := t6 (19) goto (15) (20) t7 := i1 (21) i := t7 (22) goto (10) (23)exit (b) Identify all basic blocks in your three address code. B1: 1 B2: 2 B3: 3-6 B4: 7-9 B5: 10 B6: 11 B7: B8: 15 B9: B10: B11: 23

3 (c) Build the flow graph for the three address code.

4 (d) Build the dominator tree and identify the back edges in your flow graph in (c) Flow graph Dominator tree Back edges are (10,5), (9,8), (3,2) (shown as the red edge of the flow graph). (e) Find the entry node and the set of nodes in the natural loop associated with each back edge identified in (d). back edge (10,5): entry node: 5 loop nodes: {5,6,7,8,9,10} back edge (9,8): entry node: 8 loop nodes: {8,9} back edge (3,2): entry node: 2 loop nodes: {2,3}

5 3. Consider the flow graph in Dragon book, Figure 9.10 (also given as follows). (a) Compute Gen and Kill sets for each block in the flow graph. Gen[B1] = {(1),(2)} Kill[B1] = {(8),(10),(11)} Gen[B2] = {(3),(4)} Kill[B2] = {(5),(6)} Gen[B3] = {(5)} Kill[B3] = {(4),(6)} Gen[B4] = {(6),(7)} Kill[B4] = {(4),(5),(9)} Gen[B5] = {(8),(9)} Kill[B5] = {(2),(7),(11)} Gen[B6] = {(10),(11)} Kill[B6] = {(1),(2),(8)} (b) Compute the In and Out sets for each block in the flow graph. Round 0. Initialization: In[B1] = Out[B1] = Gen[B1] = {(1),(2)} In[B2] = Out[B2] = Gen[B2] = {(3),(4)} In[B3] = Out[B3] = Gen[B3] = {(5)} In[B4] = Out[B4] = Gen[B4] = {(6),(7)} In[B5] =

6 Out[B5] = Gen[B5] = {(8),(9)} In[B6] = Out[B6] = Gen[B6] = {(10),(11)} Update: Round 1. In[B1] = Out[B1] = Gen[B1] (In[B1]-Kill[B1]) = {(1),(2)} In[B2] = Out[B1] Out[B5] ={(1),(2), (8),(9)} Out[B2] = Gen[B2] (In[B2]-Kill[B2]) = {(1),(2), (3),(4), (8),(9)} In[B3] = Out[B2] Out[B4] ={(1),(2),(3),(4),(6),(7),(8),(9)} Out[B3] = Gen[B3] (In[B3]-Kill[B3]) = {(1),(2),(3),(5),(7),(8),(9)} In[B4] = Out[B3] ={(1),(2),(3),(5),(7),(8),(9)} Out[B4] = Gen[B4] (In[B4]-Kill[B4]) = {(1),(2),(3),(6),(7),(8)} In[B5] = Out[B3] = {(1),(2),(3),(5),(7),(8),(9)} Out[B5] = Gen[B5] (In[B5]-Kill[B5]) = {(1),(3),(5),(8),(9)} In[B6] = Out[B5] ={(1),(3),(5),(8),(9)} Out[B6] = Gen[B6] (In[B6]-Kill[B6]) = {(3),(5),(9),(10),(11)} Round 2. In[B1] = Out[B1] = Gen[B1] (In[B1]-Kill[B1]) = {(1),(2)} In[B2] = Out[B1] Out[B5] ={(1),(2), (5),(6),(8),(9)} Out[B2] = Gen[B2] (In[B2]-Kill[B2]) = {(1),(2), (3),(4), (8),(9)} In[B3] = Out[B2] Out[B4] ={(1),(2), (3),(4), (6),(7),(8),(9)} Out[B3] = Gen[B3] (In[B3]-Kill[B3]) = {(1),(2), (3),(5),(7),(8),(9)} In[B4] = Out[B3] ={(1),(2), (3),(5),(7),(8),(9)} Out[B4] = Gen[B4] (In[B4]-Kill[B4]) = {(1),(2),(3),(6),(7),(8)} In[B5] = Out[B3] = {(1),(2),(3),(5),(7),(8),(9)} Out[B5] = Gen[B5] (In[B5]-Kill[B5]) = {(1),(3),(5),(8),(9)} In[B6] = Out[B5] ={(1),(3),(5),(8),(9)} Out[B6] = Gen[B6] (In[B6]-Kill[B6]) = {(3),(5),(9),(10),(11)} Reached fixed point (c) Perform constant propagation and constant folding. In[B1]: Out[B1]: a = 1; b =2 In[B2]: a = 1; b = ; c = ; d = ; e = ; Out[B2]: a = 1; b = ; c = ; d = ; e = ; In[B3]: a = 1; b = ; c = ; d = ; e = ; Out[B3]: a = 1; b = ; c = ; d = ; e = ; In[B4]: a = 1; b = ; c = ; d = ; e = ; Out[B4]: a = 1; b = ; c = ; d = ; e = ; In[B5]: a = 1; b = ; c = ; d = ; e = ; Out[B5]: a = 1; b = ; c = ; d = ; e = ; In[B6]: a = 1; b = ; c = ; d = ; e = ; Out[B6]: a = ; b = ; c = ; d = ; e = ; Constant folding B1

7 B2 B3 B4 B5 B6 (1) a = 1 (2) b = 1 (3) c = a b c = 1 b (4) d = c a d = c 1 (5) d = b d (6) d = a b d = 1 b (7) e = e 1 (8) b = a b b = 1 b (9) e = c a e = c 1 (10) a = b d (11) b = a d (d) Perform common subexpression elimination. Round 1. In[B1] = Out[B1] = In[B2] = Out[B2] = {c = ab, d = c-a} In[B3] = Out[B3] = -- note: d = bd kills bd In[B4] = Out[B4] = {d = ab, e = e1} In[B5] = Out[B5] = {b = ab, e = c-a} In[B6] = {b = ab, e = c-a} Out[B6] = Round 2. In[B1] = Out[B1] = In[B2] = Out[B2] = {c = ab, d = c-a} In[B3] = = {c,d = ab} Out[B3] = {c,d = ab} In[B4] = {c,d = ab} Out[B4] = {c,d = ab, e = e1} In[B5] = {c,d = ab} Out[B5] = {b,c,d = ab, e = c-a} In[B6] = {b,c,d = ab, e = c-a} Out[B6] = Common sub expression elimination: B1 (1) a = 1 (2) b = 1 B2

8 B3 B4 B5 B6 (3) c = a b t1 = a b; c = t1 (4) d = c a (5) d = b d (6) d = a b d = t1 (7) e = e 1 (8) b = a b b = t1 (9) e = c a (10) a = b d (11) b = a d (e) There is one common subexpression defined in (4) that can actually be reused in (9) but got eliminated unnecessarily. Explain what the problem is. The In set of a block is the intersection of the Out sets of all prior blocks is not suitable for loops. (4) actually can reach the loop body, but got eliminated due to the intersection performed at the entry point of the loop. (f) Can you come up with a revised algorithm to give a greater power in finding common subexpressions so that the unnecessarily eliminated subexpression as shown in (e) can get reused? (You can assume that the three address code being processed always follows the structured programming practice.) A loop should be viewed as multiple branches, executing the loop body 0, 1, 2, 3, times. For each loop, we can convert the CFG and let it be represented by an infinite number of branches. Then we can perform the analysis on the converted CFG. For the specific case of finding common subexpressions, we actually only need to consider two branches: the loop body being executed 0 and 1 times. So we can convert the CFG accordingly to perform the analysis.

9 4. Consider the following flow graph. B1 t1 = 1 B3 s1 = 1 t2 = t2 N B5 t3 = N N = 100 M = 1000 s1 = 2 t2 = t1 s1 if (t2 < N) go to B4 s2 = N 2 t3 = t2 s2 if (t3 < N) go to B6 B6 d = A[t1] A[t2] if d < M go to B8 B8 A[t3] = d t1 = t1 1 if (t1 < N) go to B2 B2 B4 B7 d = d M M = M 1 B9 print A[0] to A[N 1]

10 (a) Identify and mark define-use links within the loop based on data flow analysis results. You need to consider the block level define-use relations as well as define-use relations within the block. (b) Identify all the loop invariants based on the define-use links computed in (b). Assume that all the loop invariants can be moved out of the loop. So you need to find loop invariants repetitively till a fixed point is reached. In each round, you need to pretend to move out those loop invariants you found in the previous rounds. Round 1: B2: Statement N = 100 is a loop invariant, move it out of the loop Statement M = 1000 is a loop invariant, move it out of the loop Statement s1 = 2 is a loop invariant, move it out of the loop B3: Statement s1 = 1 is a loop invariant, move it out of the loop Round2: B4: Statement s2 = N 2 now is a loop invariant, move it out of the loop

11 B5: Statement t3 = N now is a loop invariant, move it out of the loop (c) For each loop invariant, determine whether it can actually be moved out of the loop. If so, move it out of the loop. If not, state the reason why it cannot be moved out. Generate the new code after code motion. Round 1: B2: Statement N = 100 is a loop invariant, and it satisfies all 3 criteria, move it out of the loop Statement M = 1000 is a loop invariant, but there are multiple definitions of M in the loop, cannot be moved out Statement s1 = 2 is a loop invariant, but there are multiple definitions of s1 in the loop, cannot be moved out B3: B3 does not dominate the exit, no point to consider any statement in it Round2: B4: Statement s2 = N 2 now is a loop invariant, and it satisfies all 3 criteria, move it out of the loop B5: B5 does not dominate the exit, no point to consider any statement in it B1 t1 = 1 B3 s1 = 1 t2 = t2 N B5 t3 = N N = 100 s2 = N 2 N = 100 M = 1000 s1 = 2 t2 = t1 s1 if (t2 < N) go to B4 s2 = N 2 t3 = t2 s2 if (t3 < N) go to B6 B6 d = A[t1] A[t2] if d < M go to B8 B8 A[t3] = d t1 = t1 1 if (t1 < N) go to B2 B2 B4 B7 d = d M M = M 1 B9 print A[0] to A[N 1]

12 5. Consider the following three address code in a basic block. (1) t1 = j 1 (2) t2 = 4 t1 (3) temp = A[t2] (4) t3 = j (5) t4 = j 1 (6) t5 = 4 t3 (7) t6 = A[t5] (8) t7 = j 1 (9) t8 = 4 t7 (10) A[t8] = t6 (11) t9 = j (12) t10 = j 1 (13) t11 = 4 t9 (14) A[t11] = temp (b) Perform copy propagation. You need to do necessary data flow analysis to make sure that the propagation can be done correctly. In[1]=Out[1]= In[2]=Out[2]= In[3] =, Out[3] = {3}; In[4] = {3}, Out[4] = {3,4} In[5] = {3,4}, Out[5] = {3,4} In[6] = {3,4}, Out[6] = {3,4} replace (6) by (6) t5 = 4 j In[7] = {3,4}, Out[7] = {3,4,7} In[8] = {3,4,7}, Out[8] = {3,4,7} In[9] = {3,4,7}, Out[9] = {3,4,7} In[10] = {3,4,7}, Out[10] = {4,10} replace (10) by (10) A[t8] = A[t5] In[11] = {4,10}, Out[11] = {4,10,11} In[12] = {4,10,11}, Out[12] = {4,10,11} In[13] = {4,10,11}, Out[13] = {4,10,11} replace (13) by (13) t11 = 4 j In[14] = {4,10,11}, Out[14] = {4,11,14} (1) t1 = j 1 (2) t2 = 4 t1 (3) temp = A[t2] (4) t3 = j (5) t4 = j 1 (6) t5 = 4 j (7) t6 = A[t5] (8) t7 = j 1 (9) t8 = 4 t7 (10) A[t8] = A[t5] (11) t9 = j (12) t10 = j 1 (13) t11 = 4 j (14) A[t11] = temp

13 (c) Perform dead code elimination. You need to do necessary analysis to make sure that the elimination can be done correctly. Also, assume that after the basic block, array A[i], for all i, is alive and no other variables are alive. t1 = j 1 [13] = {A, j, t1} t2 = 4 t1 [13] = {A, j, t2} temp = A[t2] [13] = {A, temp, j} t3 = j dead code [13] = {A, temp, j} t4 = j dead code [13] = {A, temp, j} t5 = 4 j [13] = {A, temp, j, t5} t6 = A[t5] dead code [13] = {A, temp, j, t5} t7 = j 1 [13] = {A, temp, j, t5, t7} t8 = 4 t7 [13] = {A, temp, j, t5, t8} A[t8] = A[t5] [13] = {A, temp, j} t9 = j dead code [13] = {A, temp, j} t10 = j dead code [13] = {A, temp, j} t11 = 4 j [13] = {A, temp, t11} A[t11] = temp [14] = {A} Note: A is a special case, since it is an array, we do not know the exact address being defined or used, so A definition does not kill A. On the other hand, A[5] definition can kill A[5] 6. Consider the following flow graph. Perform strength reduction for the statements in the loop. t1 = 0 read (x, y) B1 a := x t1 t2 := t1 3 5 b := y t2 c := t2 5 d := c b t1 := t1 2 B2

14 t1 = t1 2 in loop B2 is a basic IV t2 := t135 is only defined once in loop B2 and satisfies the IV format, so it is an IV defined on the basic IV t1 = t1 2. We can perform strength reduction for t2 and the revised code is as follows: t1 = 0 read (x, y) B1 st2 = t135 a := x t1 t2 := st2 b := y t2 c := t2 5 d := c b t1 := t1 2 st2 := st2 6 B2 7. Consider the following CFG. (a) Perform liveliness analysis. Show the ive sets at each point of the CFG.

15 (b) Construct the interference graph. (c) Assume that the system has five registers. Perform color assignment. Determine the register for each variable. 5-color: Remove a first Then all nodes have < 5 edges. It is 5-colorable. Remove the remainder nodes in arbitrary order. The registers for each variable are listed as follows, a: R4 b: R4 c: R3 d: R2 f: R1 v: R0 (d) Assume that the system has only three registers. Perform color assignment and determine the register for each variable. In case it is necessary to spill, spill and revise the code and then do color assignment. 3-color: Remove a first

16 Since the node with 2 edges can t be found need to spill, choose to spill v Since the node with 2 edges still can t be found need to spill. Choose to spill c. Now it is 3-colorable Next we check whether the spilled nodes can have their registers when loaded back

17 The above interference graph is colorable by 3 colors. So, spilling c and v will work. So the registers for each variable are listed as follows a: R2 b: R0 c: spill d: R2 f: R1 v: spill t1: R0: is used for temporary loading and using v t2: R1: is used for temporary loading and using v t3: R2: are used for temporary loading and using c t4: R1: are used for temporary loading and using c 8. Consider the following three address code. t1 := j t1 := t1 dim2 t1 := t1 k t1 := t1 w t2 := j k t3 := j t3 := t3 dim2 t3 := t3 k t3 := t3 w t4 : = B [ t3 ] t5: = t2 t4 A [ t1 ] := t5 (a) Construct a dag from the three address code such that subexpressions and redundant variables are eliminated.

18 A[]= t5 t4 =B[] t1 3, t3 3 t2 t1 2, t3 2 w t1 1, t3 1 k t1 0, t3 0 j dim2 (b) Schedule the dag based on the numbering scheme. Run a global register allocation algorithm. Generate code based on the register allocation and instruction schedule you derived. Your code should make sure that the content of arrays A and B are permanently modified. 1 A[]= 2 t5 4 t4 =B[] 3 t1 2, t3 2 t1 3, t3 3 5 w 8 t t1 0, t3 0 t1 1, t3 1 j 6 dim2 7 k 11

19 t1 := j t1 := t1 dim2 t1 := t1 k t1 := t1 w t2 := j k t3 := j t3 := t3 dim2 t3 := t3 k t3 := t3 w t4 : = B [ t3 ] t5: = t2 t4 A [ t1 ] := t5 {j, k} {t1, j, k} {t1, j, k } {t1, j, k} {t1, j, k} {t1, t2, j, k} {t1, t2, t3, k} {t1, t2, t3, k} {t1, t2, t3} {t1, t2, t3} {t1, t2, t4} {t1, t5} {} r3 j r1 t1 t5 r2 t4 r3 k t2 r4 r2 t3 r3 Need 4 registers r4 := load k r3 := load j r1 := r3 r2 := r3 r4 r1 := r1 dim2 r1 := r4 r1 r1 := r1 w r3 := B[r1] r2 := r3 r2 A[r1] := r2

20 9. Consider the following instruction set (only those for basic blocks). Some costs for the instructions is unreasonable, just for the purpose of practicing the instruction selection algorithms. Instruction Description Cost load <reg> <id> load identifier <id> from memory into register <reg> 10 store <reg> <id> store <reg> value into <id> s memory location 10 aload <reg1> <reg2> <reg3> load the content of array A[reg3] into register <reg1>, 11 where reg2 = &A (A s base address) astore <reg1> <reg2> <reg3> store the content of register <reg1> into array A[reg3] 15 into, where reg2 = &A add <reg1> <reg2> <reg3> reg1 := reg2 reg3 2 mul <reg1> <reg2> <reg3> reg1 := reg2 reg3 5 addc <reg1> <reg2> <const> reg1 := reg2 constant 2 mulc <reg1> <reg2> <const> reg1 := reg2 constant 5 addx <reg1> <reg2> <id> reg1 := reg2 id 11 mulx <reg1> <reg2> <id> reg1 := reg2 id 16 Consider the following three address code in a basic block. t1 := j 1 t1 := t1 d2 t1 := t1 k t1 := t1 w t7 : = B[t1] t2 := j k t2 := t2 w t8: = A[t2] t9 := t7 t8 A[t1] := t9 (a) Draw the tiles for operators aload, astore, addx, mulx. (The tiles for the remaining operators can be found in the notes and in the book.) load reg id reg store S id aload reg1 astore S reg1 &array-id reg2 reg3 &array-id reg2 reg3 add addc addx reg1 reg1 reg1 reg2 reg3 reg2 const reg2 id

21 (b) Draw the instruction tree for the basic block given above. (c) Tile the tree using the maximal munching algorithm. Assign registers to the selected instructions and generate the machine code. S R3 R1 R2 R1 R3 &A R2 R2 w R1 R2 R2 R3 R2 R2 1 d2 k &B R2 R2 w &A R3 R3 w j R2 k j k R2 1 d2 j load R2 j addc R2 R2 1 mulx R2 R2 d2 addx R2 R2 k mulx R2 R2 w load R1 &B aload R1 R1 R2 load R2 &A load R3 j mulx R3 k mulx R3 w aload R3 R2 R3 add R2 R1 R3 load R2 j addc R2 R2 1 mulx R2 R2 d2 addx R2 R2 k mulx R2 R2 w load R1 &A astore R3 R1 R2

22 (d) Tile the tree using the dynamic programming algorithm. 1 S 1 d2 w k j k w d2 w k &A &B &A j j