# NH 67, Karur Trichy Highways, Puliyur C.F, Karur District DEPARTMENT OF INFORMATION TECHNOLOGY CS 2202 DIGITAL PRINCIPLES AND SYSTEM DESIGN

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1 NH 67, Karur Trichy Highways, Puliyur C.F, Karur District DEPARTMENT OF INFORMATION TECHNOLOGY CS 2202 DIGITAL PRINCIPLES AND SYSTEM DESIGN UNIT 1 BOOLEAN ALGEBRA AND LOGIC GATES Review of binary number systems - Binary arithmetic Binary codes Boolean algebra and theorems - Boolean functions Simplifications of Boolean functions using K arnaugh map and tabulation methods Implementation of Boolean functions using logic gates. OBJECTIVES Difference between analog & digital system Understand the basic operation & laws of Boolean algebra Relate these operations & laws to circuit composed of gates & switches To understand different methods used for simplification of Boolean functions Understand the relation between operations performed using the map and the corresponding algebric operations INTRODUCTION The world of electronics is divided into two areas: analog and digital. Analog circuits consist mainly of amplifiers for voltage or current variations that are smooth and continuous. Digital circuits provide electronic switching of voltage pulses. A pulse has abrupt changes between two extreme amplitude levels (i.e.: 5 volt = high level and 0 volt = low level).

3 Decimal Hexadecimal A B C D E F Table below shows an example of counting from 0 to 18 in each of the four number systems. Number Base Conversion: Decimal Binary Octal Hexadecimal A B C D E F The conversion of a number in base r to decimal is done by expanding the number in a power series and adding all the terms For Example, 1)BINARY-DECIMAL a.(110101) 2 =1x2 5 +1x2 4 +0x2 3 +1x2 2 +0x2 1 +1x2 0 = (110101) 2 =(53) 10

4 b.( )= 1x2-1 +2x2-2 +0x2-3 +1x2-4 +0x2-5 +0x2-6 +1x2-7 = = )OCTAL-DECIMAL a = 2 x (8 2 ) + 3 x (8 1 ) + 7 x (8 0 ) = b.(123.4) 8 =1x8 2 +2x8 1 +3x8 0 +4x8-1 =1x64+2x8+3x1+4x(1/8) = =(83.5) 10 3)HEXADECIMAL-DECIMAL a.(b44b) 16 =11x x x x16 0 =(46155) 10 b = 2 x (16 1 ) + 4 x (16 0 ) + 6 x (16-1 ) = The conversion of a number in decimal to base r is done by REPEATED DIVISION by base r. For Example, 1)DECIMAL - BINARY a.(41) 10

5 (41) 10 =(101001) 2 b.(0.6875) 10

6 FOR U: Do the following Conversions 1.to decimal a.(4310) 5 b.(123) 8 c.(198) 12 d.( ) 2 e.(baba) 16 f.(16.5) 16 g.( ) 2 h.(246) 8 i.(525) 6 2.Convert the hexadecimal number 68BE to binary,and then convert it from binary to octal. 1.2 Binary number system The native language of digital computers is inherently binary. Thus, numbers are naturally represented as binary integers by the computer. The range of numbers which can be represented is

7 dependent on the number of bits used. A common unit of storage is a byte which is a group of eight bits. Eight bits can represent 2 8 unique states, i.e. 256 possible combinations. This fact can be used to our advantage to represent many different things on the computer. For example, a byte can be used to represent 256 colours, 256 shades of grey, 256 shapes, 256 symbols, 256 names, or even 256 different numbers. More typically, we can use a byte to represent 256 sequential numbers such as the numbers from 1 to 256, or the numbers from 0 to 255. Remember that 0 is not "nothing" and has equal significance as any other number. Signed Integers One of the eight bit is reserved to indicate the sign of the number. Following usual convention, the left-most bit (called the most significant bit or MSB) is dedicated as the sign bit. For the numbers from to 127, there are 256 unique numbers in this range. With this scheme, we can now have 128 positive and 128 negative numbers, typically the numbers from 0 to 127. This scheme has the anomaly that there are two unique representations for positive and negative zero. A more serious problem is that the rules of binary arithmetic breakdown when we decrement by 1 from positive to negative numbers. To overcome the discontinuity at zero, a scheme of complementary binary is used whereby negative numbers are represented by the binary complement of the positive representation. This system is called one's complement binary. This system also has two unique representations for positive and negative zero. The two's complement binary system overcomes both problems mentioned above. In this notation, the negative number is represented by forming the binary complement of the positive number and adding one. To summarize, integers are commonly represented by the unsigned binary and the 2's complement binary representations. The range of integer numbers can be extended by utilizing more bits. For example, 16 bits will allow us to represent 2 16 unique items, i.e possible states. These can be the numbers from 0 to for unsigned integers or to for 2's complement signed integers SIGN- MAGNITUDE form s compliment form s compliment form Binary arithmetic Arithmetic in binary is much like arithmetic in other numeral systems. Addition, subtraction, multiplication, and division can be performed on binary numerals.

8 Addition The simplest arithmetic operation in binary is addition. Adding two single-digit binary numbers is relatively simple, using a form of carrying: , carry 1 (since = in binary) Ex: (carried digits) = Subtraction Subtraction works in much the same way: , borrow = Binary Multiplication Usually, two other logic functions, left shift and right shift, are provided since these are also easy to implement in hardware. When a number is shifted by one digit to the left, for example, 123 left shifted becomes 1230, this is equivalent to multiplying the number by the radix, whatever it may be. Similarly, 123 shifted to the right is 12.3 and this is the same as dividing by the radix. In binary, shifting left by one bit is equivalent to multiplying by 2. Shifting right by one bit is the same as dividing by 2.

9 To find 2941 x 318, the first number is called the multiplicand and the second is the multiplier, there are two ways depending on which end of the multiplier we begin with. The following should look familiar: = = = A less familiar method is the following where we start with the left digit of the multiplier: = = = = = = In both cases, the product can be formally stated as the sum of partial products as follows: = ( ) + ( ) + ( ) Multiplication in binary (or any other radix) can be performed using the same technique as for decimal. Both methods shown are easily implemented in binary on a digital computer. In the examples shown above, the partial products are first formed and the summation is done at the end. In a computer algorithm this is not the usual case since it is more efficient to sum the partial products as they are formed. In special processors optimized for speed, such as digital signal processors (DSP), dedicated hardware to do this is called a multiply and accumulate register (MAC). Multiplying in binary follows the same rules. 111 x 101. This can be formulated as follows: ( ) + ( ) + ( )

10 With binary arithmetic, the task of multiplying by 2 is simply a shift of one bit to the left. Similarly, dividing by 2 is a shift of one bit to the right. Binary Division Division in binary follows the same concept as for long division in decimal (Ex) Binary Codes for Decimal Digits Internally, digital computers operate on binary numbers. When interfacing to humans, digital processors, e.g. pocket calculators, communication is decimal-based. Input is done in decimal then converted to binary for internal processing. For output, the result has to be converted from its internal binary representation to a decimal form. To be handled by digital processors, the decimal input (output) must be coded in binary in a digit by digit manner. For example, to input the decimal number 957, each digit of the number is individually

11 coded and the number is stored as 1001_0101_0111. Thus, we need a specific code for each of the 10 decimal digits. There is a variety of such decimal binary codes. The shown table gives several common such codes. One commonly used code is the Binary Coded Decimal (BCD) code which corresponds to the first 10 binary representations of the decimal digits 0-9. The BCD code requires 4 bits to represent the 10 decimal digits. Since 4 bits may have up to 16 different binary combinations, a total of 6 combinations will be unused. The position weights of the BCD code are 8, 4, 2, 1. Other codes (shown in the table) use position weights of 8, 4, -2, -1 and 2, 4, 2, 1. An example of a non-weighted code is the excess-3 code where digit codes is obtained from their binary equivalent after adding 3. Thus the code of a decimal 0 is 0011, that of 6 is 1001, etc.

12

13 Gray Code The Gray code consist of 16 4-bit code words to represent the decimal Numbers 0 to 15. For Gray code, successive code words differ by only one bit from one to the next as shown in the table and further illustrated in the Figure

14 Character Codes ASCII Character Code ASCII code is a 7-bit code. Thus, it represents a total of 128 characters. Out of the 128 characters, there are 94 printable characters and 34 control (non- printable) characters. The printable characters include the upper and lower case letters (2*26), the 10 numerals (0-9), and 32 special characters, %, \$, etc. For example, A is at (41)16, while a is at (61) )16. To convert upper case letters to lower case letters, add (20)16. Thus a is at (41)16 + (20)16 = (61)16. The code of the character 9 at position (39)16 is different from the binary number 9 ( ). To convert ASCII code of a numeral to its binary number value, subtract (30)16.

15 Boolean Algebra Boolean Algebra George Boole (1854) invented a new kind of algebra that could be used to analyse and design digital and computer circuits Boolean laws and theorems Certain rules and theorems are defined to facilitate the simplification of Boolean expressions inturn making the simpler logic circuits with reduced number of gates. Basic laws Commutative law: A+B =B+A AB = BA Associative law: A + (B+C) = (A+B) + C A(BC) = (AB)C

16 Distributive law: A (B+C) = AB + AC Postulates 1. Identity Identity elements exist for each operation that leaves the result unchanged. A+0 = A A.0 = 0 A+1 = 1 A.1 = A An operation between two identical variables will yield a result that is unchanged A+A = A A.A = A 2. Inverse For every element, there is an inverse or complement with the following properties A.A = 0 A+A = 1 3. The complement of a complement gives back the original quantity (A ) = A Boolean relations about OR operations

17 A+0=A A+A=A A+1=1 Boolean relations about AND operations A ' 1 = A A ' A = A A ' 0 = 0 DE MORGAN S THEOREMS 1. This states that the inverse (i.e.)of a product [and] is equal to the sum [or] of the complements 2. This states that the inverse (complement) of a sum [or] is equal to the product [and] of the complements These theorems can be extended to cover several variables: Logic Gates 1. NOT operation

18 Fig. 2-1: Inverter symbol and Boolean notation Ex: If A is 0 (low) ' X = NOT 0 = 1 In Boolean algebra the overbar stands for NOT operation. 2. OR operation TRUTH TABLE Fig. 2-2: OR symbol and Boolean notation Ex: If A = 0, B = 1 ' X = A or B = 0 or 1 = l In Boolean algebra the + sign stans for the OR A B Z X=A+B Ex: If A = 1, B = 0 ' X = A + B = = 1 3.AND operation

19 Fig. 2-3: AND symbol and Boolean notation In Boolean algebra the multiplication sign stands for the X = AB Ex: If A = 1, B = 0 ' X = A B = 1 ' 0 = 0 TRUTH TABLE A B Z AND operation 4. NOR gate Based on the three fundamental logic operations it is possible to design additionel logic devices. Fig. 2-6: NOR gate, symbol and truth table

20 5. NAND gate Fig. 2-7: NAND grate, symbol and truth table 6. XOR gate Events which are true only if and only if one of the motivating events are true Truth Table A B F Canonical and Standard forms Consider two binary variables x and y combined by an AND operation X. Y 0 0 m 0 X. Y 0 1 m 1

21 X. Y 1 0 m 2 Where X Primed representing binary 0 X. Y 1 1 m 3 And X Unprimed representing binary 1 m x Minterm or standard product For n variables, there are in total 2 n Minterms. For OR operation, X + Y 0 0 M 0 X + Y 0 1 M 1 X + Y 1 0 M 2 X + Y 1 1 M 3 M x Maxterm or standard sum Each Maxterm is the complement of corresponding Minterm. Boolean expression can be expressed in terms of Minterms and Maxterms as follows X Y Z f Sum of minterms: Boolean expression for the function f 1 from the given truth table is,

22 f 1 = X Y Z + XY Z + XYZ = m 1 + m 4 + m 7 ie) OR ing the minterms which gives 1 in the function f 1 2 Product of maxterms: Similarly, f 1 = (X+Y+Z) (X+Y +Z) (X+Y +Z ) (X +Y+Z ) (X +Y +Z) = M 0. M 2.M 3.M 5. M 6 ie) AND ing the maxterms which gives 0 in the function f 1 Karnaugh Map It is a systematic method to simplify Boolean expression using a map. Map is a diagram made up of cells where each cell gives the output value for the corresponding input combination. Totally there are 2 n cells for n input variables. The map presents a visual diagram of all possible ways a function may be expressed in a standard form. 1.Two- and Three- variable maps A Two-variable map is shown below. There are 4 cells for 2 variables. Each cell for a minterm. Figure (a) shows the minterms and (b) the relationship between the cells and variables. Example: F 1 = XY is represented by this mapping method as,

23 Since XY is equal to m 3, a 1 is placed inside the cell that belongs to m 3. Similarly, F 2 = X + Y as, A Three-variable map is shown below. Here 8 cells are not arranged in a binary sequence, but in a sequence similar to Gray code. The characteristic of this sequence is that only 1 bit changes from 0 to 1 or 1 to 0 in the listing sequence. ie) the minterms in the adjacent cells are differing by a single bit. This is the basic principle behind K-Map and can be clarified by taking a function having m 5 and m 7 as, m 5 + m 7 = XY Z + XYZ = XZ(Y +Y) = XZ.

24 Two minterms of 3 literals is solved into a single minterm of 2 literals. The two cells are considered to be adjacent even though they do not touch each other like m 0 and m 2. Example: #1) Simplify the Boolean function F(X, Y, Z) = (2, 3, 4, 5) Mark 1 in each minterm that represents the function. Find the adjacent cells (shown in two rectangles) Upper rectangle area is enclosed by the variables X and Y Similarly lower rectangle by variables X and Y So the resultant function is F(X, Y, Z) = (2, 3, 4, 5) = X Y + XY 2. Four- variable map A Four-variable map is shown below.

25 The minterm corresponding to each cell can be obtained by the concatenation of the respective row and column. For instance, third row (11) and second column (01) gives 1101, the binary equivalent of decimal 13 representing m 13. The map minimization is the similar procedure as that of the three variable type. No other combination of squares can simplify the function. 3.Five- variable map shown below Maps for more than 4 variables are not as simple to use. It needs 32 cells. A Five-variable map is It consists of 2 four-variable maps, where A distinguishes between two maps. Minterms 0 throgh 15 belong with A = 0 and Minterms 16 throgh 31 belong with A = 1. Each map retains adjacency when taken

26 separately. Each cell in the A = 0 map is adjacent to the corresponding cell in the A = 1 map like 4 and 20, 15 and 31. Simply, for 2 k adjacent squares, for k = 0,1,2..n, in an n-variable map will represent an area that gives a term of n-k literals. When n=k, the entire areas of the is combined to give the identity function. 4 Product of Sum simplification With minor modification, POS form is obtained as the result of simplification from the map. Simplified expression for the complement of the function,f, is obtained if the cells with 0 s are combined into valid squares. The complement of F inturn gives us F in POS form.(by Demorgan s Theorem) Ex: #1) Simplify the given Boolean expression in SOP and POS form. F(A,B,C,D) = (0,1,2,5,8,9,10)

27 Combining cells with 1 s gives the SOP form, F = B D + B C + A C D Combining cells with 0 s gives the form, F = AB + CD + BD Applyind Demorgan s theorem, we get the simplified POS form F = (A + B ) (C + D ) (B + D) Gate implementation of the function F = B D + B C + A C D F = (A + B ) (C + D ) (B + D) NAND and NOR Implementation NAND and NOR gates are easier to fabricate and are the basic gates used in all IC digital logic families. So Boolean functions interms of NAND and NOR is necessory. The invert OR symbol is followed from the Demorgan s thoerem. Similarly for NOR gate,

28 A one-input NAND or NOR behaves like an inverter 1. NAND implementation Boolean expression in sum of product form is needed for NAND implementation. Consider for example, F = AB+CD+E is implemented in three ways as shown below. Figure (a) and (c) looks similar but NAND implementation needs one more NAND gate for complementing E. By Demorgan s theorem, F = [ (AB). (CD). E ] = AB + CD + E. Thus the two level implementation is possible with the NAND gates for the given Boolean expression.

29 2. NOR implementation NOR function is the dual of the NAND function. So all the procedures and rules for NOR logic are the dual of the NAND logic. Boolean expression in product of sum form is needed for NOR implementation. For the same example given above, F = (A+B). (C+D). E To obtain product of sum from a map, it is necessary to combine cells with 0 s and then complement the function. 3. Don t-care conditions The logical sun of minterms associated with the Boolean function specifies the condition under which the function is equal to 1. The function is equal to 0 for the rest of the minterms. Ie) all the combinations of variables are valid. In some practical applications the function is not specified for certain combinations of variables. For example four bit codes for BCD greater than 9 has six invalid combinations. These unspecified minterms are known as don t care conditions and used for further simplification. To distinguish don t care condition from 0 and 1, it is marked with X. Don t care cell is assumed to be 1 or 0 when choosing adjacent squares. Ex. #1) Simplify F(w,x,y,z) = (1,3,7,11,15) That has the don t care conditions d(w,x,y,z) = (0,2,5)

30 All the five 1 s should be included to form the sum of products. But X may or may not be included. By including 0 and 2 don t care items, F = yz+w x By including 5 don t care item, F = yz+w z Expression in POS form is by grouping 0 s and include minterms 0 and 2 to get it in the simplified version. F = z + wy Complementing F yields F(w,x,y,z) = z(w +y) = yz+w z For this case minterms 0 and 2 are included with 0 s and minterm 5 with the 1 s. TABULATION METHOD If the number of variables exceeds five or six, excessive number of cells make the grouping difficult whereby the tabulation method is a step-by-step procedure.this method was first tabulated by Quine and later improved by Mccluskey. Hence it is known as Quine- Mccluskey method. It consists of two parts. First is to find the Prime implicants. Second to choose among the prime implicants those that give an expression with least number of literals. Example 1) Find minimal SOP for f = (1,2,3,4,5,7,8,9,10,11,14,15)

31 Solution: i) write the given minterms in binary form minterms A B C D ii) Arrange the numbers in increasing number of 1 s No. Of 1 s minterms A B C D 1 ^ ^ ^ ^ ^ ^ ^ ^ ^ ^

32 4 15 ^ iii) Compare adjacent groups to find numbers which differ by 1 variable. ^denotes the numbers undergone the comparision Combination A B C D (1,3) ^ 0 0 _ 1 (1,9)^ _ (2,3)^ _ (2,10)^ _ (8,9)^ _ (8,10) ^ 1 0 _ 0 (3,7)^ 0 _ 1 1 (3,11)^ _ (9,11)^ 1 0 _ 1 (10,11)^ _ (10,14) ^ 1 _ 1 0 (7,15) ^ _ (11,15)^ 1 _ 1 1 (14,15)^ denotes the differing variable position iv) Form 4 cell combination,by having adjacent group comparison, with 1 bit varying and _ in same position Combination A B C D (1,3,9,11) _ 0 _ 1 (2,3,10,11) _ 0 1 _ (8,9,10,11) 1 0

33 (3,7,11,15) 1 1 (10,11,14,15) 1 _ 1 _ From the above table no more combination is possible. v) Prime Implicants table Prime Implicants (1,3,9,11)* X X X X (2,3,10,11)* X X X X (8,9,10,11)* X X X X (3,7,11,15)* X X X X (10,11,14,15)* X X X X Essential ^ ^ ^ Prime Implicants ^ ^ Essential Prime Implicants is the one which has only one X in the column of minterms * mark is placed on the Prime Implicants which has Essential Prime Implicants inside. The resultant function consisting of Essential Prime Implicants and the Prime Implicants covering the remaining minterms. Here all the Prime Implicants are Essential Prime Implicants. Therefore Y = B D + B C + AB + CD + AC SUMMARY Digital electronics are electronics systems that use digital signals. Arithmetic in binary is much like arithmetic in other numeral systems. Addition, subtraction, multiplication, and division can be performed on binary numerals. One commonly used code is the Binary Coded Decimal (BCD) code non-weighted code is the excess-3 code where digit codes is obtained from their binary equivalent after adding 3.

34 Gray code consist of 16 4-bit code words to represent the decimal Numbers 0 to 15. ASCII code is a 7-bit Alpha-Numeric code Karnaugh Map is a systematic method to simplify Boolean expression using a map. KEY TERM Binary codes De morgan s theorems Product of maxterms Logic Gates ASCII Sum of minterms Karnaugh Map Universal Gates MULTIPLE CHOICE 1)Digital signals: (a) vary smoothly, then change abruptly to new values. (b) consist of codes of high-level and low-level signals. (c) vary smoothly continuously. (d) have periods of high-level and low-level signals, then change to continuous signals. 2)Binary digital systems: (a) have two discrete levels 1 or 0, high level or low level. (b) have three or more discrete levels. (c) have a level that varies continuously with time. (d) have binary digits, or bits for short. (e) none of the above. (f) d and a above. 3)Decimal numbering systems have: (a) weighted digit positions that vary randomly. (b) weighted digit positions varying by powers of 10. (c) weighted digit positions varying by powers of 2. (d) weighted digit positions that remain constant at one value.

35 4)Digital systems represent quantities: (a) using combinations of binary digits in codes. (b) using more bits in its binary codes as the quantity value increases. (c) using more bits in its binary code as more accuracy is required. (d) using binary codes with just two levels 1 or 0, high level or low level. (e) none of the above. (f) all of the above. 5) The standard SOP form of the expression is (a) (b) (c) (d) 6) The standard symbol for EX-OR gate is 7) In the 8421 BCD code the decimal number 125 is written as a) b) c) 7D d) None of the above 8) The expression can be simplified to

36 9) The 2's complement of is 10) Number of nibbles making one byte is 11) Next binary number after 0,1, 10, 11 is - 12)

37 13)The binary division gives 14) The binary equivalent of is 15) The output Y of the circuit in the given figure is

38 PART-A 1. Find the hexadecimal equivalent of the decimal number Find the octal equivalent of the decimal number What is meant by weighted and non-weighted coding? 4. Convert A3BH and 2F3H into binary and octal respectively 5. Find the decimal equivalent of (123)9 6. Find the octal equivalent of the hexadecimal number AB.CD 7. Encode the ten decimal digits in the 2 out of 5 code 8. Show that the Excess 3 code is self complementing 9. Find the hexadecimal equivalent of the octal number Find the decimal equivalent of (346)7 11. A hexadecimal counter capable of counting up to at least (10,000)10 is to be constructed. What is the minimum number of hexadecimal digits that the counter must have? 12. Convert the decimal number 214 to hexadecimal 13. Convert to base Give an example of a switching function that contains only cyclic prime implicant 15. Give an example of a switching function that for which the MSP from is not unique. 16. Express x+yz as the sum of minterms 17. What is prime implicant? 18. Find the value of X = A B C (A+D) if A=0; B=1; C=1 and D=1 19. What are minterms and maxterms? 20. State and prove Demorgan s theorem 21. Find the complement of x+yz 22. Define the following : minterm and term 23. State and prove Consensus theorem 24. What theorem is used when two terms in adjacent squares of K map are combined? 25. How will you use a 4 input NAND gate as a 2 input NAND gate? 26. How will you use a 4 input NOR gate as a 2 input NOR gate? 27. Show that the NAND connection is not associative 28. What happens when all the gates is a two level AND-OR gate network are replaced by NOR gates? 29. What is meant by multilevel gates networks? 30. Show that the NAND gate is a universal building block

39 PART-B 1. (a) Explain how you will construct an (n+1) bit Gray code from an n bit Gray code (b) Show that the Excess 3 code is self -complementing 2. (a) Prove that (x1+x2).(x1. x3 +x3) (x2 + x1.x3) =x1 x2 (b) Simplify using K-map to obtain a minimum POS expression: (A + B +C+D) (A+B +C+D) (A+B+C+D ) (A+B+C +D ) (A +B+C +D ) (A+B+C +D) 3. (a) State and Prove idempotent laws of Boolean algebra. (b) using a K-Map,Find the MSP from of F= _(0,4,8,12,3,7,11,15) +_d(5) 4. Find the Minterm expansion of f(a,b,c,d) = a (b +d) + acd 5. Simplify the following Boolean function by using the Tabulation Method F= _ (0, 1, 2, 8, 10, 11, 14, 15) 6. State and Prove the postulates of Boolean algebra 7. Find a Min SOP and Min POS for f = b c d + bcd + acd + a b c + a bc d 8. State and Prove the theorems of Boolean algebra with illustration 9. Find the MSP representation for F(A,B,C,D,E) = _m(1,4,6,10,20,22,24,26) + _d (0,11,16,27) using K-Map method Draw the circuit of the minimal expression using only NAND gates 10. (a) Show that if all the gates in a two level AND-OR gate networks are replaced by NAND gates the output function does not change (b) Why does a good logic designer minimize the use of NOT gates?

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41 Appendix-I IC s 74LS00 Quad 2 input NAND gate 74LS01 Quad 2 input NAND gate (OC) 74LS02 Quad 2 input NOR gate 74LS03 Quad 2 input NAND gate 74LS04 74LS05 74LS06 74LS08 74LS09 74LS10 74LS11 74LS12 74LS13 74LS14 74LS16 74LS15 74LS20 74LS21 Hex Inverter Hex Inverter (OC) Hex Inverter buffer/driver Quad 2 input AND Quad 2 input AND gate (OC) Triple 3 input NAND gate Triple 3 input AND gate Triple 3 input NAND gate (OC) Dual 4-input NAND gate Schmitt trigger Hex Inverter Schmitt trigger Hex Inverter (OC) Triple 3 input AND gate (OC) Dual 4 input NAND gate Dual 4 input AND gate

42 74LS22 Dual 4 input NAND gate (OC) 7425 Dual 4 input NOR gate with strobe 74LS22 Dual 4 input NAND gate (OC) 7425 Dual 4 input NOR gate with strobe 74LS27 74LS30 74LS32 74LS38 74LS42 Triple 3 input NOR gate 8 input NAND gate Quad 2 input OR gate Quad 2 input NAND gate Buffer BCD to DEC decoder 7445 BCD to DEC decoder 74LS47 74LS48 74LS51 74LS54 74F64 BCD to 7 seg decoder/driver BCD to 7 seg decoder/driver AND/OR/INVERT gate AND/OR/INVERT gate AND/OR/INVERT gate 7470 JK flip flop 7472 JK M/S flip flop 74LS73 74LS74 74LS75 Dual JK flip flop with clear Dual D-Type flip-flops with preset and clear 4 bit bistable latch

43 74LS76 74LS83 74LS85 74LS86 74LS90 74LS91 74LS92 74LS93 74LS95 Dual JK flip-flops with preset and clear 4 bit full adder 4 bit magnitude comparator Quad 2 input XOR gate Decade counter 8-bit shift register Divide by 12 counter Binary counter 4 bit shift register 74LS107 Dual JK flip-flops with clear 74LS109 Dual JK pos edge trig flip flop 74LS112 Dual JK neg edge trig flip flop Monostable multivibrator 74LS122 Monostable multivibrator 74LS123 Monostable multivibrator 74LS125 Monostable multivibrator 74LS132 Quad 2 input NAND gate Schmitt trigger 74S input NAND 74LS136 Quad 2 input XOR (O.C) 74LS138 3-to-8 line decoder/demux

44 74LS139 Dual 1-of-4 decoder/demux 74LS line - 4 line octal priority encoder 74LS148 8 line - 3 line octal priority encoder Data selector/mux 74LS151 8 input MUX 74LS153 Dual 4-to-1 Multiplexer 74LS154 4-to16 decoder/demux 74LS155 Dual 2 line to 4 line decoder / demux 74LS156 Dual 2 line to 4 line decoder / demux (O.C) 74LS157 Quad 2 input MUX 74LS158 Quad 2 input MUX with invereted outputs 74LS160 BCD decade counter 74LS161 Synchronous 4 bit binary counter 74LS162 BCD decade counter counter 74LS163 Asynchronous 4 bit binary counter 74LS164 8 bit SIPO shift register 74LS165 8 bit PISO shift register 74LS166 74LS174 74LS175 8 bit PISO shift register Hex D type flip flop with clear Quad D type flip flop with clear

45 74176 Decade Counter Binary Counter 74LS191 74LS192 74LS193 74LS195 74LS196 74LS197 4 bit binary up / down counter BCD up / down counter 4 bit binary up / down counter 4 bit shift register Presettable decade counter Presettable binary counter bit shift register 74LS221 74S225 74LS240 74LS241 74LS244 74LS245 74LS251 74LS257 74LS259 74LS266 74LS273 Dual monostable multivibrator 16x5 FIFO memory Octal buffer/line driver Octal 3-state buffer Octal buffer/line driver Octal bus transceiver Data selector / MUX Quad 2 input mux 3-state 8 bit addressable latch Quad 2 input XNOR (O.C) Octal D type flip flop with clear

46 74LS280 74LS298 74LS299 74LS323 74LS367 74LS368 74LS373 74LS374 74LS390 74LS393 74LS395 74LS540 74LS541 9 bit odd / even parity generator Quad 2 input MUX with storage 8 bit universal shift register 8-Bit Shift register Hex bus driver Hex bus driver with inverters Octal transparent latch Octal D type flip flop 3-state Dual 4 bit decade counter Dual 4 bit binary counter 4 bit shift register Octal buffer 3-state Octal buffer 3-state outputs

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