Chap 3. Modeling structure & basic concept of Verilog HDL

Size: px
Start display at page:

Download "Chap 3. Modeling structure & basic concept of Verilog HDL"

Transcription

1 Chap 3. Modeling structure & basic concept of Verilog HDL Fall semester, 2016 Prof. Jaeseok Kim School of Electrical & Electronics Eng. Yonsei university Digital System Design 3-1

2 Chapter overview Modeling structure of Verilog language - Module, port, module instance Description of module body : Three styles Simulation with testbench program Basic features of Verilog language - Lexical conventions for identifiers, comments, numbers, strings - Logic values, data types, scalars & vectors, time variables - Arrays, memories, parameters, operators - Hierarchical names Basic system tasks Compiler directives Digital System Design 3-2

3 3.1 Modeling structure of Verilog language Verilog design consists of interconnected modules 1) Module : Basic design building block in Verilog - Can be a design element or a collection of lower-level design block - Provides a module name and its port interface (inputs/outputs) 2) Port : - Interface by which module can communicate with its environment 3) Module instance : - A unique object created from module template when the module is invoked - The objects are called instances - Each object has its own name, variables, parameters and I/O interface - The process of creating objects from a module template is called instantiation Digital System Design 3-3

4 Modules - Begins with keyword module & ends with endmodule - Module name, port list, port declaration and optional parameter must come first in a module definition - Four components within a module to describe functional specifications: Variable declarations (wires, regs, ) Behavioral statements (always & initial blocks) and/or Data flow statements (assign) Instantiation of lower-level modules Tasks or functions * Can be in any order Digital System Design 3-4

5 Module components module <modul_name> (<port_list>); Port declarations Parameters (optional) Declarations of wires, regs, and other variables; Behavioral and data flow statements; Instantiation of lower-level modules; Tasks and functions; endmodule Digital System Design 3-5

6 Example : Full Adder Module * Full adder schematic * Verilog module description A B Cin A B Cin A B xor1 or1 w1 w2 xor2 and1 and2 w3 w4 sum or2 c_out module full_addr(a, Module b, c_in, full_adder(a, sum, c_out); b, c_in, sum, c_out); Module name input a, b, c_in; output port listsum, c_out; wire w1, w2, w3, w4; port declaration wire declaration xor xor or and and or endmodule xor1(w1, a, b); xor2(sum, w1, c_in); or1(w2, a, b); and1(w3, w2, c_in); and2(w4, a, b); or2(c_out, w3, w4); Module instantiation input a, b, c_in; output sum, c_out; wire w1, w2, w3, w4; xor xor or and and or xor1(w1,a,b); xor2(sum, w1, c_in); or1(w2,a,b); and1(w3, w2, c_in); and2(w4, a, b); or2(c_out, w3, w4); endmodule //Basic gate instantiation and a1(out, IN1, IN2); or or1(out, IN1, IN2); xor x1(out, IN1, IN2); Digital System Design 3-6

7 Port Declaration Provide the interface by which a module can communicate with its environment Type of Port : input, output, inout (Bi-directional) All port declarations are implicitly declared as wire If output ports hold their value, they must be declared as reg (Ex. D F/F output q) Digital System Design 3-7

8 Port Declaration example * Port Declaration of full adder Block diagram Port Declaration of full adder module full_adder(a, b, c_in, sum, c_out); input a, b, c_in; output sum, c_out; wire w1, w2, w3, w4; endmodule a b c_in Full Adder sum c_out ANSI C style Port Declaration module full_adder( input a, b, input c_in output sum, output c_out); endmodule Digital System Design 3-8

9 Connecting Ports(1) * Connecting Ports to external signals 1) Connecting by ordered list - The signal to be connected must appear in module instantiation in same order as the ports in port list in module definition module Top; //Declare connection variables reg A, B; reg C_in; wire SUM; wire C_OUT; //Instantiate module full_adder, named FA1 //Signals are connected to ports in order (by position) full_adder FA1(A, B, C_in, SUM, C_OUT); <stimulus> endmodule module full_adder(a, b, c_in, sum, c_out); input a, b, c_in; output sum, c_out; wire w1, w2, w3, w4; <module internal> endmodule Digital System Design 3-9

10 Connecting Ports (2) 2) Connecting ports by name - Connect external signals to ports by the port names full_adder FA1(.sum(SUM),.c_out(C_OUT),.a(A),.b(B),.c_in(C_in)); Digital System Design 3-10

11 3.2 Description of module body Module body: Specifies module s functionality 1) Behavioral style - describe the module s function by behavioral operation using behavioral statements inside always block 2) Dataflow style - describe the function by specifying data flow between HW registers using assign statement including Boolean expressions * RTL level design : combination of behavioral and dataflow style 3) Primitive gate style -Describe the function by primitive logic gates 4) Instantiation of lower-level modules - describe sub-components and connect lower-level components to form the upper-level design Digital System Design 3-11

12 Behavioral-level modeling example Full adder (Behavioral-level) Truth table Verilog code A B Cin SUM Co module Full_adder(A, B, Cin, SUM, Co); input A, B, Cin; output SUM, Co; reg SUM, Co; (A,B,Cin) begin case({a, B, Cin}) 3'b000 : begin SUM = 0; Co = 0; end 3'b001 : begin SUM = 1; Co = 0; end 3'b010 : begin SUM = 1; Co = 0; end 3'b011 : begin SUM = 0; Co = 1; end 3'b100 : begin SUM = 1; Co = 0; end 3'b101 : begin SUM = 0; Co = 1; end 3'b110 : begin SUM = 0; Co = 1; end 3'b111 : begin SUM = 1; Co = 1; end endcase end endmodule Digital System Design 3-12

13 Behavioral-level modeling example 4bit-binary counter (Behavioral-level) //4-bit Binary counter module counter(q, clock, clear); //I/O ports output [3:0] Q; input clock, clear; //output defined as register reg [3:0] Q; clear or negedge clock) begin if(clear) Q <= 4'd0; //Nonblocking assignments are recommended //for creating sequential logic such as flipflops else Q <= Q + 1; //Modulo 16 is not necessary because Q is a //4-bit value and wraps around end endmodule Digital System Design 3-13

14 Data-flow modeling example Full adder (Data-flow) Boolean Equation using K-map Cin SUM AB SUM = ABCin+ABCin+ABCin+ABCin Verilog code module Full_adder(A, B, Cin, SUM, Co); input A, B, Cin; output SUM, Co; assign S = (~A & ~B & Cin) (~A & B & ~Cin) (A & B & Cin) (A & ~B & ~Cin); assign Co = (A&B) (B&Cin) (A&Cin); Cin 0 1 Co AB endmodule Co = AB+BCin+ACin Digital System Design 3-14

15 Data-flow modeling example 4bit-ripple counter (Dataflow-level/gate-level) * The counter is built with four T_FFs // Ripple counter module counter(clk, clear, Q, rst_n); // I/O ports input clk, clear, rst_n; output [3:0] Q; // Instantiate the T flipflops t_ff tff0(q[0], ~clk, rst_n); t_ff tff1(q[1], ~Q[0], rst_n); t_ff tff2(q[2], ~Q[1], rst_n); t_ff tff3(q[3], ~Q[2], rst_n); endmodule * Compare with the behavioral modeling Digital System Design 3-15

16 s Data-flow modeling example T_FFs * Built-in T_FF models //T_FF module module t_ff(q,clk,reset); output q; input clk,reset; wire d; d_ff dff0(q, d, clk, reset); //initiate d_ff not n1(d,q); endmodule // D_FF module module d_ff(q,d,clk,reset); output q; input d, clk, reset; reg q; always@(posedge reset or negedge clk) If(reset) q <= 1 b0; else q<=d; endmodule Digital System Design 3-16

17 Gate-level modeling example Full adder (Gate-level) Verilog code Schematic // Define the module full adder. // It instantiates And and OR gates module full_adder(a, b, c_in, sum, c_out); a b xor1 w1 input a, b, c_in; output sum, c_out; wire w1, w2, w3, w4; c_in xor2 sum xor xor1(w1, a, b ); xor xor2(sum, w1, c_in); or or1(w2, a, b); and and1(w3, w2, c_in); and and2(w4, a, b); or or2(c_out, w3, w4); a b c_in a b or1 w2 and1 and2 w3 w4 or2 c_out endmodule Digital System Design 3-17

18 Pre-defined gate primitives AND/OR/NAND/NOR/XOR/XNOR gates Have one scalar output & multiple scalar inputs The 1st port in I/O list is output and the other ports are inputs buf/not gates : one output & one input i1 i2 out i1 i2 out and nand i1 i2 out i1 i2 out or nor i1 i2 out i1 i2 out xor xnor Digital System Design 3-18

19 Instantiation of basic gate types wire OUT, IN1, IN2; //basic gate instantiations. and a1(out, IN1, IN2); nand na1(out, IN1, IN2); or or1(out, IN1, IN2); nor nor1(out, IN1, IN2); xor x1(out, IN1, IN2); xnor nx1(out, IN1, IN2); Digital System Design 3-19

20 Example of module instantiation * 4-bit Ripple Carry Adder(RCA) // Top-level module called ripple carry adder. // It instantiates 4 full adders. module ripple_carry_adder(a, b, sum, c_out); input [3:0] a; input [3:0] b; output [3:0] sum; output c_out; wire c_out1, c_out2, c_out3; a[3] b[3] c_out3 a[2] b[2] c_out2 a[1] b[1] c_out1 a[0] b[0] 1'b0 //Four instances of the module full_adder are created. full_adder FA0(a[0], b[0], 1'b0, sum[0], c_out1); full_adder FA1(a[1], b[1], c_out1, sum[1], c_out2); full_adder FA2(a[2], b[2], c_out2, sum[2], c_out3); full_adder FA3(a[3], b[3], c_out3, sum[3], c_out); endmodule c_out Full Adder (FA3) sum[3] Full Adder (FA2) sum[2] Full Adder (FA1) sum[1] Full Adder (FA0) sum[0] Digital System Design 3-20

21 3.3 Verilog Simulation A system designed in Verilog must be simulated & tested for functionality before implementation Simulating a design requires design description & test data (testbench), and you will get observation of simulation results Verilog Design Description Test bench Verilog Simulator Simulation Results (waveform, text, ) Digital System Design 3-21

22 Concurrency of Verilog simulation All the components in an electronic circuit are to be operated concurrently Verilog simulator is developed to simulate concurrency of circuit operations (In contrast, C program is executed in sequential way) Concurrency in Verilog is handled by proceeding simulation in small time steps (which is not real time) All activities scheduled at one time step are completed and then simulator advances to the next time step If sequence operation is required, use appropriate sequential constructs in Verilog Digital System Design 3-22

23 Testbench or Stimulus block(1) Functionality of design block can be tested by applying stimulus and checking result. Stimulus block (also called testbench) is written in Verilog Two styles of stimulus application 1) Stimulus block instantiates design block & directly drives the signals in design block Stimulus Block a b (Design Block) Ripple Carry adder sum c_out - Stimulus block becomes top-level block Digital System Design 3-23

24 Testbench or Stimulus block(2) 2) Stimulus and design blocks instantiated in a dummy top-level module Top-Level Block A B Stimulus Block SUM C_OUT DUT (RCA) - The stimulus block interacts with design block only thru the interface Digital System Design 3-24

25 3.4 Verilog Design Example Design block of 4-bit RCA Digital System Design 3-25

26 Design block of 4-bit RCA Verilog Design Example module ripple_carry_adder(a, b, sum, c_out); input [3:0] a; input [3:0] b; output [3:0] output wire sum; c_out; c_out1, c_out2, c_out3; //Four instances of the module full_adder are created. full_adder FA0(a[0], b[0], 1'b0, sum[0], c_out1); full_adder FA1(a[1], b[1], c_out1, sum[1], c_out2); full_adder FA2(a[2], b[2], c_out2, sum[2], c_out3); full_adder FA3(a[3], b[3], c_out3, sum[3], c_out); endmodule // Define the module full adder. // It instantiates And and OR gates module full_adder(a, b, c_in, sum, c_out); input a, b, c_in; output sum, c_out; wire w1, w2, w3, w4; xor xor1(w1, a, b ); xor xor2(sum, w1, c_in); or or1(w2, a, b); and and1(w3, w2, c_in); and and2(w4, a, b); or or2(c_out, w3, w4); endmodule Digital System Design 3-26

27 Example of Stimulus block * Stimulus and output waveforms to test the design 100 ns A 4'b0001 4'b1110 4'b0101 4'b0001 B 4'b0011 4'b1010 4'b0001 SUM 4'b0100 4'b0001 4'b1111 4'b0010 C_OUT Digital System Design 3-27

28 Stimulus block // compiler directive to specify time unit for simulation // time delay is 100ns // System task for monitoring Digital System Design 3-28

29 Output of the simulation 0 output sum = 4, carry out = output sum = 1, carry out = output sum = 15, carry out = output sum = 2, carry out = 0 Digital System Design 3-29

30 3.5 Basic features: Lexical Conventions(1) 1. Identifiers - Identifiers: names given to objects - made up of alphanumeric characters, _ or $ - The first character: alphabetic character or _ - $ sign as the first character is reserved for system tasks - Underscore(_) can be used for readability of numbers and ignored by verilog except the first character - Case-sensitive (like C) - All keywords (reserved for language) are in lowercase (list of keywords in Appendix) Digital System Design 3-30

31 2. White spaces Lexical Conventions(2) - Blanks(/b), tabs(/t), and new lines(/n) form the white space characters in Verilog - They are used to separate tokens - But, not ignored in string 3. Comments - Two ways of writing Comments (for readability & documentation)» One-line comment: Start with // to the end of line» Multiple-line comment: Start with /* ends with */ Multiple-line comments cannot be nested Digital System Design 3-31

32 4. Numbers a) Integer numbers Numbers(1)» Declared by keyword integer» Default width is host-machine word size (at least 32 bits) integer counter; // counter is defined as integer counter = 10; // variable b) Real numbers» Declared by keyword real» Can be specified in decimal or scientific notation Decimal notation : -a.b Scientific notation : 4.3e6(=4.3 X 10 6 ) Digital System Design 3-32

33 Numbers(2) c) Alternate form of number representation :» Represented as (sign) <size>`<base format><number>» Optional sign bit is allowed only for decimal numbers. If negative sign is used, number is in 2 s complement form» <size> : use decimal number to specify the bit width of the number» No <size> specification : size is machine-dependent (32-bit)» <base format> : `b(`b), `o(`o), `d(`d), `h(`h)» If no <base format> specification, decimal number by default 4'b1001 // 4-bit binary number 'o62 //32-bit octal number 1234 //32-bit decimal number 12'habc //12-bit hexadecimal number -8'd2 //8-bit negative number Digital System Design 3-33

34 -? mark Numbers(3)»? mark is the alternative for z(high impedance) in context of numbers - Underscore(_) character» Underscore(_) is allowed anywhere in a number except 1 st character for readability of number (ignored by verilog) 4'b10?? // Equivalent of a 4`b10zz 12'b1111_0000_1010 //Use of underline characters for readability Digital System Design 3-34

35 5. Strings Strings - A sequence of characters enclosed within double quotes( ) - Must be contained on a single line - Special characters are specified by preceding with \ character - Can be stored in reg string_value = Hello Verilog World ;» Special Characters Escaped Characters \n \t \% \\ \ Character Displayed newline tab % \ Digital System Design 3-35

36 Logic Values & Strengths - Verilog supports 4 logic values & 8 strengths a) Value levels Value Level 0 1 x z Condition in Hardware Circuit Logic zero, false condition Logic one, true condition Unknown logic value High impedance, floating state b) Strength levels (for 0 & 1) Useful for accurate modeling of signal contention Strength Level supply strong pull large weak medium small highz Type Driving Driving Driving Storage Driving Storage Storage High Impedance Degree strongest weakest Digital System Design 3-36

37 Data Types(1) Two main data types : net and register (variable) 1) Net - Represents a connection between hardware elements - Declared with keyword wire (or tri) - Net gets the output value of their drivers (if no driver -> z) - Default value is z (except trireg net to x) wire a, b; // Declare two wires a, b wire c = 1'b0; // Net c is assigned to logic value 0 at declaration Digital System Design 3-37

38 2) Register Data Types(2) - Represents a variable that can hold a value (different with H/W register) - Declared by keyword reg - Keep value until another value is placed onto it - Default value is x reg reset; // declare a variable reset that can hold its value reset = 1'b1; // initialize reset to 1 Digital System Design 3-38

39 Scalars and Vectors(1) - Net or reg data type can be declared as scalar or vector - Scalar: Entity representing single bit (default) - Vector: Entity representing multiple bit widths [MSB:LSB] wire a; // scalar net variable reg clock; // scalar register wire [7:0] bus; // 8-bit bus (vector) wire [31:0] busa; // 32-bit width busa a) Vector Part Select : Possible to address parts of vectors bus[3:0] // Four least significant bits of vector bus busa[5] // bit # 5 of vector busa Digital System Design 3-39

40 Scalars and Vectors(2) Vector Indexed Part Select : - Specifies starting index and the number of bits to be selected - Two special part-select operators : [<starting_bit>+:width] part-select increments from starting bit [<starting_bit> :width] part-select decrements from starting bit bus[2+:4]; busa[31-:8]; // selects bit 2, 3, 4, and 5 of vector bus // selects bit 31~24 of vector busa Digital System Design 3-40

41 Time Variable - Used to store simulation time - Declared with keyword time - System function $time can be called to get current simulation time time save_sim_time; // Define a time variable save_sim_time save_sim_time = $time; // Save the current simulation time Digital System Design 3-41

42 Arrays - Allowed for reg, integer, time, real and vector register data types - Multiple elements that are 1-bit or n-bit wide - Multi-dimensional arrays can be declared with any number of dimensions - Arrays are accessed by <array-name>[<subscript>] integer count[0:7]; reg [4:0] port_id[0:7]; integer matrix[3:0][0:255]; // An array of 8 count variables // Array of 8 port_ids; each port_id is 5bits wide // Two dimensional array of integers named matrix Digital System Design 3-42

43 Memories - Memories (RAM, ROM, register files) are modeled as a onedimensional array of registers - Each element of array is an element or word and is addressed by a single array index reg mem1bit[0:1023]; // Memory mem1bit with 1K 1-bit words reg [7:0] membyte[0:1023]; // Memory membyte with 1K 8-bit words(bytes) membyte[511]; // Fetches 1 byte word whose address is 511 Digital System Design 3-43

44 Parameters - Constants to be defined in a module by keyword parameter - parameter assignments are made at compile time - parameter values can be changed at module instantiation or by using defparam statement - localparam keyword used to define parameters when their values should not be changed parameter port_id = 5; // Defines a constant port_id parameter cache_line_width = 256; // Constant defines width of cache line localparam state1 = 4 b0001, state2 = 4 b0010, state3 = 4 b0100, state4 = 4 b1000; Digital System Design 3-44

45 Operators - Three types : Unary, binary and ternary a = ~ b; a = b && c; a = b? c : d; // ~ is a unary operator. b is the operand // && is a binary operator. b and c are operands //?: is a ternary operator. b, c and d are operands - Details for operator types and symbols will be covered in data-flow modeling section Digital System Design 3-45

46 Hierarchical Names Every module, signal or variable is defined with an identifier Hierarchical name referencing allows to denote every identifier in the design hierarchy with a unique name A hierarchical name is a list of identifiers separated by dots(.) for each level of hierarchy Digital System Design 3-46

47 Hierarchical Names - Design Hierarchy for RCA1 module RCA1 F1 (Full Adder) F2 (Full Adder) AND1 (AND) A0 B0 - Hierarchical Names of signals OR1 (OR) Digital System Design 3-47

48 3.6 Basic System Tasks(1) System Tasks - Carry out some system-related routine operations during simulation of any design such as displaying on screen, monitoring values of nets, and controlling simulation process - All system tasks has the format $<keyword> a) $display» System task for displaying value of variables or expressions (similar to printf in C)» Usage: $display(p1,p2,...,pn); (where p1,p2,...,pn can be variables or expressions) // Display the string in quotes $display( Hello Verilog World ); -- Hello Verilog World // Display value of current simulation time 100 $display($time); Digital System Design 3-48

49 Basic System Tasks(2) * String format specification for display of arguments Format %d of %D %b of %B %s of %S %h of %H %c of %C %m of %M %v of %V %o of %O %t of %T %e of %E %f of %F %g of %G Display Display variable in decimal Display variable in binary Display string Display variable in hex Display ASCII character Display hierarchical name (no argument required) Display strength Display variable in octal Display in current time format Display real number in scientific format (e.g., 3e10) Display real number in decimal format (e.g., 2.13) Display real number in scientific or decimal, whenever is shorter Digital System Design 3-49

50 b) $monitor Basic System Tasks(3)» Monitors a signal when its value changes» Usage: $monitor(p1,p2,...,pn);» Only one monitoring list can be active at a time» $monitoron; or $monitoroff; // Monitor time and value of the signals clock and reset // Clock toggles every 5 time units and reset goes down at 10 time units initial begin $monitor($time, Value of signals clock = %b reset = %b, clock, reset); end //Partial output of the monitor statement -- 0 Value of signals clock = 0 reset = Value of signals clock = 1 reset = Value of signals clock = 0 reset = 0 Digital System Design 3-50

51 Basic System Tasks(4) c) $stop & $finish» $stop; suspends simulation» $finish; terminates simulation // Stop at time 100 in the simulation and examine the results // Finish the simulation at time 500. initial // time = 0 begin clock = 0; #100 $stop; // This will suspend the simulation at time = 100 #400 $finish; // This will terminate the simulation at time = 500 end Digital System Design 3-51

52 3.7 Compiler Directives * Compiler Directives - A number of compiler directives are provided -Defined by using `<keyword> a) `define - Used to define text macros (similar to #define in C) - Compiler substitutes text of macro whenever it encounters `<macro_name> // define a text macro that defines default word size // Used as `WORD_SIZE in the code `define WORD_SIZE 32 // define an alias. A $stop will be substituted whenever `S appaers `define S $stop; // define a frequently used text string `define WORD_REG reg [31:0] // you can then define a 32-bit register as `WORD_REG reg32; Digital System Design 5-52

53 b) `include Compiler Directives - Allows to include contents of a source file in another file during compilation (similar to #include in C) - Used to include header files // Include the file header.v, which contains declarations in the // main verilog file design.v. `include header.v // to be explained later. time = <Verilog code in file design.v> Digital System Design 5-53

54 Compiler Directive : Time Scales c) `timescale Specify a certain time unit for module simulation Usage : `timescale <reference_time_unit> / <time_percision> The <reference_time_unit> specifies the unit of measurement for times and delays The <time_percision> specifies the precision to which the delays are rounded off during simulation Only 1, 10 and 100 are valid integers for specifying time unit Digital System Design 5-54

55 Example : `timescale //Define a time scale for the module dummy1 //Reference time unit is 100 nanoseconds //and precision is 1 ns `timescale 100 ns / 1 ns module dummy1; reg toggle; //initialize toggle initial toggle = 1 b0; //Flip the toggle register every 5 time units //In this module 5 time units = 500 ns =.5 us always #5 begin toggle = ~toggle; $display( %d, In %m toggle = %b, $time, toggle); end endmodule //Define a time scale for the module dummy2 //Reference time unit is 1 microsecond //and precision is 10 ns `timescale 1 us / 10 ns module dummy2; reg toggle; //initialize toggle initial toggle = 1 b0; //Flip the toggle register every 5 time units //In this module 5 time units = 5 us = 5000 ns always #5 begin toggle = ~toggle; $display( %d, In %m toggle = %b, $time, toggle); end endmodule Digital System Design 5-55

56 Summary(1) Modeling structure of Verilog language - Verilog design = Interconnected modules - Concept of module, port, module instance - Connecting ports Description of module body - Behavioral style - Data flow style - Primitive gate style - Instantiation of lower-level modules Simulation with testbench program - Concurrency of Verilog simulation - Example of Verilog design & simulation: 4-bit RCA adder Digital System Design 3-56

57 Summary(2) Basic features of Verilog language - Lexical conventions for identifiers, comments, numbers, strings - Logic values, data types (net & register), scalars & vectors - time variables - Arrays, memories, parameters, operators - Hierarchical names Basic system tasks - $display, $ monitor, $stop, & $ finish Compiler directives - `define, ` include, `timescale Digital System Design 3-57

P-1/74. Samir Palnitkar. Prentice-Hall, Inc. INSTRUCTOR : CHING-LUNG SU.

P-1/74. Samir Palnitkar. Prentice-Hall, Inc. INSTRUCTOR : CHING-LUNG SU. : P-1/74 Textbook: Verilog HDL 2 nd. Edition Samir Palnitkar Prentice-Hall, Inc. : INSTRUCTOR : CHING-LUNG SU E-mail: kevinsu@yuntech.edu.tw Chapter 3 P-2/74 Chapter 3 Basic Concepts Outline of Chapter

More information

EN2911X: Reconfigurable Computing Topic 02: Hardware Definition Languages

EN2911X: Reconfigurable Computing Topic 02: Hardware Definition Languages EN2911X: Reconfigurable Computing Topic 02: Hardware Definition Languages Professor Sherief Reda http://scale.engin.brown.edu School of Engineering Brown University Spring 2014 1 Introduction to Verilog

More information

Verilog HDL [As per Choice Based Credit System (CBCS) scheme]

Verilog HDL [As per Choice Based Credit System (CBCS) scheme] Verilog HDL [As per Choice Based Credit System (CBCS) scheme] Subject Code IA Marks 20 Number of Lecture 04 Exam Marks 80 Hours/Week Total Number of 50 (10 Hours / Module) Exam Hours 03 Lecture Hours CREDITS

More information

Computer Aided Design Basic Syntax Gate Level Modeling Behavioral Modeling. Verilog

Computer Aided Design Basic Syntax Gate Level Modeling Behavioral Modeling. Verilog Verilog Radek Pelánek and Šimon Řeřucha Contents 1 Computer Aided Design 2 Basic Syntax 3 Gate Level Modeling 4 Behavioral Modeling Computer Aided Design Hardware Description Languages (HDL) Verilog C

More information

A Verilog Primer. An Overview of Verilog for Digital Design and Simulation

A Verilog Primer. An Overview of Verilog for Digital Design and Simulation A Verilog Primer An Overview of Verilog for Digital Design and Simulation John Wright Vighnesh Iyer Department of Electrical Engineering and Computer Sciences College of Engineering, University of California,

More information

Lab #1. Topics. 3. Introduction to Verilog 2/8/ Programmable logic. 2. Design Flow. 3. Verilog --- A Hardware Description Language

Lab #1. Topics. 3. Introduction to Verilog 2/8/ Programmable logic. 2. Design Flow. 3. Verilog --- A Hardware Description Language Lab #1 Lecture 8, 9, &10: FPGA Dataflow and Verilog Modeling February 9, 11, 13, 2015 Prof R Iris Bahar Lab #1 is posted on the webpage wwwbrownedu/departments/engineering/courses/engn1640 Note for problem

More information

ENGN1640: Design of Computing Systems Topic 02: Design/Lab Foundations

ENGN1640: Design of Computing Systems Topic 02: Design/Lab Foundations ENGN1640: Design of Computing Systems Topic 02: Design/Lab Foundations Professor Sherief Reda http://scale.engin.brown.edu School of Engineering Brown University Spring 2017 1 Topics 1. Programmable logic

More information

ENGN1640: Design of Computing Systems Topic 02: Lab Foundations

ENGN1640: Design of Computing Systems Topic 02: Lab Foundations ENGN1640: Design of Computing Systems Topic 02: Lab Foundations Professor Sherief Reda http://scale.engin.brown.edu School of Engineering Brown University Spring 2014 1 Topics 1. Programmable logic 2.

More information

N-input EX-NOR gate. N-output inverter. N-input NOR gate

N-input EX-NOR gate. N-output inverter. N-input NOR gate Hardware Description Language HDL Introduction HDL is a hardware description language used to design and document electronic systems. HDL allows designers to design at various levels of abstraction. It

More information

Verilog Design Principles

Verilog Design Principles 16 h7fex // 16-bit value, low order 4 bits unknown 8 bxx001100 // 8-bit value, most significant 2 bits unknown. 8 hzz // 8-bit value, all bits high impedance. Verilog Design Principles ECGR2181 Extra Notes

More information

ENGN1640: Design of Computing Systems Topic 02: Design/Lab Foundations

ENGN1640: Design of Computing Systems Topic 02: Design/Lab Foundations ENGN1640: Design of Computing Systems Topic 02: Design/Lab Foundations Professor Sherief Reda http://scale.engin.brown.edu School of Engineering Brown University Spring 2016 1 Topics 1. Programmable logic

More information

Schematic design. Gate level design. 0 EDA (Electronic Design Assistance) 0 Classical design. 0 Computer based language

Schematic design. Gate level design. 0 EDA (Electronic Design Assistance) 0 Classical design. 0 Computer based language 1 / 15 2014/11/20 0 EDA (Electronic Design Assistance) 0 Computer based language 0 HDL (Hardware Description Language) 0 Verilog HDL 0 Created by Gateway Design Automation Corp. in 1983 First modern hardware

More information

ECE 4514 Digital Design II. Spring Lecture 2: Hierarchical Design

ECE 4514 Digital Design II. Spring Lecture 2: Hierarchical Design ECE 4514 Digital Design II Spring 2007 Abstraction in Hardware Design Remember from last lecture that HDLs offer a textual description of a netlist. Through abstraction in the HDL, we can capture more

More information

Verilog Design Principles

Verilog Design Principles 16 h7fex // 16-bit value, low order 4 bits unknown 8 bxx001100 // 8-bit value, most significant 2 bits unknown. 8 hzz // 8-bit value, all bits high impedance. Verilog Design Principles ECGR2181 Extra Notes

More information

FPGA: FIELD PROGRAMMABLE GATE ARRAY Verilog: a hardware description language. Reference: [1]

FPGA: FIELD PROGRAMMABLE GATE ARRAY Verilog: a hardware description language. Reference: [1] FPGA: FIELD PROGRAMMABLE GATE ARRAY Verilog: a hardware description language Reference: [] FIELD PROGRAMMABLE GATE ARRAY FPGA is a hardware logic device that is programmable Logic functions may be programmed

More information

Introduction. Why Use HDL? Simulation output. Explanation

Introduction. Why Use HDL? Simulation output. Explanation Introduction Verilog HDL is a Hardware Description Language (HDL) HDL is a language used to describe a digital system, for example, a computer or a component of a computer. Most popular HDLs are VHDL and

More information

Contents. Appendix D Verilog Summary Page 1 of 16

Contents. Appendix D Verilog Summary Page 1 of 16 Appix D Verilog Summary Page 1 of 16 Contents Appix D Verilog Summary... 2 D.1 Basic Language Elements... 2 D.1.1 Keywords... 2 D.1.2 Comments... 2 D.1.3 Identifiers... 2 D.1.4 Numbers and Strings... 3

More information

Verilog. Like VHDL, Verilog HDL is like a programming language but:

Verilog. Like VHDL, Verilog HDL is like a programming language but: Verilog Verilog Like VHDL, Verilog HDL is like a programming language but: Statements can execute simultaneously unlike programming e.g. nand(y1,a1,b1); nand(y2,a2,b2); or (out,y1,y2); a1 b1 all statements

More information

Course Topics - Outline

Course Topics - Outline Course Topics - Outline Lecture 1 - Introduction Lecture 2 - Lexical conventions Lecture 3 - Data types Lecture 4 - Operators Lecture 5 - Behavioral modeling A Lecture 6 Behavioral modeling B Lecture 7

More information

Verilog HDL Introduction

Verilog HDL Introduction EEE3050 Theory on Computer Architectures (Spring 2017) Prof. Jinkyu Jeong Verilog HDL Introduction 2017.05.14 TA 이규선 (GYUSUN LEE) / 안민우 (MINWOO AHN) Modules The Module Concept Basic design unit Modules

More information

Online Verilog Resources

Online Verilog Resources EECS 427 Discussion 6: Verilog HDL Reading: Many references EECS 427 F08 Discussion 6 1 Online Verilog Resources ASICs the book, Ch. 11: http://www.ge.infn.it/~pratolo/verilog/verilogtutorial.pdf it/ pratolo/verilog/verilogtutorial

More information

EN164: Design of Computing Systems Lecture 06: Lab Foundations / Verilog 2

EN164: Design of Computing Systems Lecture 06: Lab Foundations / Verilog 2 EN164: Design of Computing Systems Lecture 06: Lab Foundations / Verilog 2 Professor Sherief Reda http://scaleenginbrownedu Electrical Sciences and Computer Engineering School of Engineering Brown University

More information

Verilog. What is Verilog? VHDL vs. Verilog. Hardware description language: Two major languages. Many EDA tools support HDL-based design

Verilog. What is Verilog? VHDL vs. Verilog. Hardware description language: Two major languages. Many EDA tools support HDL-based design Verilog What is Verilog? Hardware description language: Are used to describe digital system in text form Used for modeling, simulation, design Two major languages Verilog (IEEE 1364), latest version is

More information

CSE241 VLSI Digital Circuits Winter Recitation 1: RTL Coding in Verilog

CSE241 VLSI Digital Circuits Winter Recitation 1: RTL Coding in Verilog CSE241 VLSI Digital Circuits Winter 2003 Recitation 1: RTL Coding in Verilog CSE241 R1 Verilog.1 Kahng & Cichy, UCSD 2003 Topic Outline Introduction Verilog Background Connections Modules Procedures Structural

More information

14:332:231 DIGITAL LOGIC DESIGN. Hardware Description Languages

14:332:231 DIGITAL LOGIC DESIGN. Hardware Description Languages 14:332:231 DIGITAL LOGIC DESIGN Ivan Marsic, Rutgers University Electrical & Computer Engineering Fall 2013 Lecture #22: Introduction to Verilog Hardware Description Languages Basic idea: Language constructs

More information

Chap 6 Introduction to HDL (d)

Chap 6 Introduction to HDL (d) Design with Verilog Chap 6 Introduction to HDL (d) Credit to: MD Rizal Othman Faculty of Electrical & Electronics Engineering Universiti Malaysia Pahang Ext: 6036 VERILOG HDL Basic Unit A module Module

More information

LANGUAGE CONSTRUCTS AND CONVENTIONS IN VERILOG

LANGUAGE CONSTRUCTS AND CONVENTIONS IN VERILOG LANGUAGE CONSTRUCTS AND CONVENTIONS IN VERILOG Dr.K.Sivasankaran Associate Professor, VLSI Division School of Electronics Engineering, VIT University Outline White Space Operators Comments Identifiers

More information

P-1/26. Samir Palnitkar. Prentice-Hall, Inc. INSTRUCTOR : CHING-LUNG SU.

P-1/26. Samir Palnitkar. Prentice-Hall, Inc. INSTRUCTOR : CHING-LUNG SU. : P-1/26 Textbook: Verilog HDL 2 nd. Edition Samir Palnitkar Prentice-Hall, Inc. : INSTRUCTOR : CHING-LUNG SU E-mail: kevinsu@yuntech.edu.tw Chapter 4 P-2/26 Chapter 4 Modules and Outline of Chapter 4

More information

Introduction to Verilog HDL. Verilog 1

Introduction to Verilog HDL. Verilog 1 Introduction to HDL Hardware Description Language (HDL) High-Level Programming Language Special constructs to model microelectronic circuits Describe the operation of a circuit at various levels of abstraction

More information

Design Using Verilog

Design Using Verilog EGC220 Design Using Verilog Baback Izadi Division of Engineering Programs bai@engr.newpaltz.edu Basic Verilog Lexical Convention Lexical convention are close to C++. Comment // to the of the line. /* to

More information

EECS 427 Lecture 14: Verilog HDL Reading: Many handouts/references. EECS 427 W07 Lecture 14 1

EECS 427 Lecture 14: Verilog HDL Reading: Many handouts/references. EECS 427 W07 Lecture 14 1 EECS 427 Lecture 14: Verilog HDL Reading: Many handouts/references EECS 427 W07 Lecture 14 1 Online Verilog Resources ASICs the book, Ch. 11: http://www.ge.infn.it/~pratolo/verilog/verilogtutorial.pdf

More information

Introduction To Verilog Design. Chun-Hung Chou

Introduction To Verilog Design. Chun-Hung Chou Introduction To Verilog Design Chun-Hung Chou 1 Outline Typical Design Flow Design Method Lexical Convention Data Type Data Assignment Event Control Conditional Description Register Description Synthesizable

More information

Speaker: Shao-Wei Feng Adviser: Prof. An-Yeu Wu Date: 2010/09/28

Speaker: Shao-Wei Feng Adviser: Prof. An-Yeu Wu Date: 2010/09/28 99-1 Under-Graduate Project Verilog Simulation & Debugging Tools Speaker: Shao-Wei Feng Adviser: Prof. An-Yeu Wu Date: 2010/09/28 ACCESS IC LAB Outline Basic Concept of Verilog HDL Gate Level Modeling

More information

Lecture #2: Verilog HDL

Lecture #2: Verilog HDL Lecture #2: Verilog HDL Paul Hartke Phartke@stanford.edu Stanford EE183 April 8, 2002 EE183 Design Process Understand problem and generate block diagram of solution Code block diagram in verilog HDL Synthesize

More information

Chapter 2 Using Hardware Description Language Verilog. Overview

Chapter 2 Using Hardware Description Language Verilog. Overview Chapter 2 Using Hardware Description Language Verilog CSE4210 Winter 2012 Mokhtar Aboelaze based on slides by Dr. Shoab A. Khan Overview Algorithm development isa usually done in MATLAB, C, or C++ Code

More information

Verilog Tutorial (Structure, Test)

Verilog Tutorial (Structure, Test) Digital Circuit Design and Language Verilog Tutorial (Structure, Test) Chang, Ik Joon Kyunghee University Hierarchical Design Top-down Design Methodology Bottom-up Design Methodology Module START Example)

More information

FPGA Design Challenge :Techkriti 14 Digital Design using Verilog Part 1

FPGA Design Challenge :Techkriti 14 Digital Design using Verilog Part 1 FPGA Design Challenge :Techkriti 14 Digital Design using Verilog Part 1 Anurag Dwivedi Digital Design : Bottom Up Approach Basic Block - Gates Digital Design : Bottom Up Approach Gates -> Flip Flops Digital

More information

Introduction to Digital Design with Verilog HDL

Introduction to Digital Design with Verilog HDL Introduction to Digital Design with Verilog HDL Modeling Styles 1 Levels of Abstraction n Behavioral The highest level of abstraction provided by Verilog HDL. A module is implemented in terms of the desired

More information

Tutorial on Verilog HDL

Tutorial on Verilog HDL Tutorial on Verilog HDL HDL Hardware Description Languages Widely used in logic design Verilog and VHDL Describe hardware using code Document logic functions Simulate logic before building Synthesize code

More information

DIGITAL SYSTEM DESIGN

DIGITAL SYSTEM DESIGN DIGITAL SYSTEM DESIGN Prepared By: Engr. Yousaf Hameed Lab Engineer BASIC ELECTRICAL & DIGITAL SYSTEMS LAB DEPARTMENT OF ELECTRICAL ENGINEERING Digital System Design 1 Name: Registration No: Roll No: Semester:

More information

Course Topics - Outline

Course Topics - Outline Course Topics - Outline Lecture 1 - Introduction Lecture 2 - Lexical conventions Lecture 3 - Data types Lecture 4 - Operators Lecture 5 - Behavioral modeling A Lecture 6 Behavioral modeling B Lecture 7

More information

Module 2.1 Gate-Level/Structural Modeling. UNIT 2: Modeling in Verilog

Module 2.1 Gate-Level/Structural Modeling. UNIT 2: Modeling in Verilog Module 2.1 Gate-Level/Structural Modeling UNIT 2: Modeling in Verilog Module in Verilog A module definition always begins with the keyword module. The module name, port list, port declarations, and optional

More information

Introduction. Purpose. Intended Audience. Conventions. Close

Introduction. Purpose. Intended Audience. Conventions. Close Introduction Introduction Verilog-XL is a simulator that allows you to test the logic of a design. The process of logic simulation in Verilog-XL is as follows: 1. Describe the design to Verilog-XL. 2.

More information

Introduction to Verilog

Introduction to Verilog Introduction to Verilog COE 202 Digital Logic Design Dr. Muhamed Mudawar King Fahd University of Petroleum and Minerals Presentation Outline Hardware Description Language Logic Simulation versus Synthesis

More information

Verilog HDL. Gate-Level Modeling

Verilog HDL. Gate-Level Modeling Verilog HDL Verilog is a concurrent programming language unlike C, which is sequential in nature. block - executes once at time 0. If there is more then one block, each execute concurrently always block

More information

Combinational Logic II

Combinational Logic II Combinational Logic II Ranga Rodrigo July 26, 2009 1 Binary Adder-Subtractor Digital computers perform variety of information processing tasks. Among the functions encountered are the various arithmetic

More information

INTRODUCTION TO VLSI DESIGN

INTRODUCTION TO VLSI DESIGN INTRODUCTION TO VLSI DESIGN 1.1 INTRODUCTION The word digital has made a dramatic impact on our society. More significant is a continuous trend towards digital solutions in all areas from electronic instrumentation,

More information

register:a group of binary cells suitable for holding binary information flip-flops + gates

register:a group of binary cells suitable for holding binary information flip-flops + gates 9 차시 1 Ch. 6 Registers and Counters 6.1 Registers register:a group of binary cells suitable for holding binary information flip-flops + gates control when and how new information is transferred into the

More information

Hardware Description Languages (HDLs) Verilog

Hardware Description Languages (HDLs) Verilog Hardware Description Languages (HDLs) Verilog Material from Mano & Ciletti book By Kurtulus KULLU Ankara University What are HDLs? A Hardware Description Language resembles a programming language specifically

More information

Verilog Language Concepts

Verilog Language Concepts Verilog Language Concepts Adapted from Z. Navabi Portions Copyright Z. Navabi, 2006 1 Verilog Language Concepts Characterizing Hardware Languages Timing Concurrency Timing and concurrency example Module

More information

Digital Design with FPGAs. By Neeraj Kulkarni

Digital Design with FPGAs. By Neeraj Kulkarni Digital Design with FPGAs By Neeraj Kulkarni Some Basic Electronics Basic Elements: Gates: And, Or, Nor, Nand, Xor.. Memory elements: Flip Flops, Registers.. Techniques to design a circuit using basic

More information

Hardware Description Language VHDL (1) Introduction

Hardware Description Language VHDL (1) Introduction Hardware Description Language VHDL (1) Introduction Digital Radiation Measurement and Spectroscopy NE/RHP 537 Introduction Hardware description language (HDL) Intended to describe circuits textually, for

More information

Introduction to Verilog/System Verilog

Introduction to Verilog/System Verilog NTUEE DCLAB Feb. 27, 2018 Introduction to Verilog/System Verilog Presenter: Yao-Pin Wang 王耀斌 Advisor: Prof. Chia-Hsiang Yang 楊家驤 Dept. of Electrical Engineering, NTU National Taiwan University What is

More information

Department of Computer Science and Electrical Engineering. Intro to Verilog II

Department of Computer Science and Electrical Engineering. Intro to Verilog II Department of Computer Science and Electrical Engineering Intro to Verilog II http://6004.csail.mit.edu/6.371/handouts/l0{2,3,4}.pdf http://www.asic-world.com/verilog/ http://www.verilogtutorial.info/

More information

Synthesizable Verilog

Synthesizable Verilog Synthesizable Verilog Courtesy of Dr. Edwards@Columbia, and Dr. Franzon@NCSU http://csce.uark.edu +1 (479) 575-6043 yrpeng@uark.edu Design Methodology Structure and Function (Behavior) of a Design HDL

More information

Spring 2017 EE 3613: Computer Organization Chapter 5: Processor: Datapath & Control - 2 Verilog Tutorial

Spring 2017 EE 3613: Computer Organization Chapter 5: Processor: Datapath & Control - 2 Verilog Tutorial Spring 2017 EE 3613: Computer Organization Chapter 5: Processor: Datapath & Control - 2 Verilog Tutorial Avinash Kodi Department of Electrical Engineering & Computer Science Ohio University, Athens, Ohio

More information

Chapter 3: Dataflow Modeling

Chapter 3: Dataflow Modeling Chapter 3: Dataflow Modeling Prof. Soo-Ik Chae Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 3-1 Objectives After completing this chapter, you will be able to: Describe

More information

Verilog Dataflow Modeling

Verilog Dataflow Modeling Verilog Dataflow Modeling Lan-Da Van ( 范倫達 ), Ph. D. Department of Computer Science National Chiao Tung University Taiwan, R.O.C. Spring, 2017 ldvan@cs.nctu.edu.tw http://www.cs.nctu.edu.tw/~ldvan/ Source:

More information

Abi Farsoni, Department of Nuclear Engineering and Radiation Health Physics, Oregon State University

Abi Farsoni, Department of Nuclear Engineering and Radiation Health Physics, Oregon State University Hardware description language (HDL) Intended to describe circuits textually, for a computer to read Evolved starting in the 1970s and 1980s Popular languages today include: VHDL Defined in 1980s by U.S.

More information

VLSI Design 13. Introduction to Verilog

VLSI Design 13. Introduction to Verilog Last module: Sequential circuit design Design styles This module Synthesis Brief introduction to Verilog Synthesis in the Design Flow Designer Tasks Tools Architect Logic Designer Circuit Designer Define

More information

Chapter 6: Hierarchical Structural Modeling

Chapter 6: Hierarchical Structural Modeling Chapter 6: Hierarchical Structural Modeling Prof. Soo-Ik Chae Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 6-1 Objectives After completing this chapter, you will

More information

ECE 2300 Digital Logic & Computer Organization. More Sequential Logic Verilog

ECE 2300 Digital Logic & Computer Organization. More Sequential Logic Verilog ECE 2300 Digital Logic & Computer Organization Spring 2018 More Sequential Logic Verilog Lecture 7: 1 Announcements HW3 will be posted tonight Prelim 1 Thursday March 1, in class Coverage: Lectures 1~7

More information

LAB K Basic Verilog Programming

LAB K Basic Verilog Programming LAB K Basic Verilog Programming Perform the following groups of tasks: LabK1.v 1. Create a directory to hold the files of this lab. 2. Launch your favourite editor and a command-prompt console; you will

More information

Lab 7 (All Sections) Prelab: Introduction to Verilog

Lab 7 (All Sections) Prelab: Introduction to Verilog Lab 7 (All Sections) Prelab: Introduction to Verilog Name: Sign the following statement: On my honor, as an Aggie, I have neither given nor received unauthorized aid on this academic work 1 Objective The

More information

A Brief Introduction to Verilog Hardware Definition Language (HDL)

A Brief Introduction to Verilog Hardware Definition Language (HDL) www.realdigital.org A Brief Introduction to Verilog Hardware Definition Language (HDL) Forward Verilog is a Hardware Description language (HDL) that is used to define the structure and/or behavior of digital

More information

ECE 353 Lab 4. Verilog Review. Professor Daniel Holcomb With material by Professor Moritz and Kundu UMass Amherst Fall 2016

ECE 353 Lab 4. Verilog Review. Professor Daniel Holcomb With material by Professor Moritz and Kundu UMass Amherst Fall 2016 ECE 353 Lab 4 Verilog Review Professor Daniel Holcomb With material by Professor Moritz and Kundu UMass Amherst Fall 2016 Recall What You Will Do Design and implement a serial MIDI receiver Hardware in

More information

EECS150 - Digital Design Lecture 10 Logic Synthesis

EECS150 - Digital Design Lecture 10 Logic Synthesis EECS150 - Digital Design Lecture 10 Logic Synthesis September 26, 2002 John Wawrzynek Fall 2002 EECS150 Lec10-synthesis Page 1 Logic Synthesis Verilog and VHDL stated out as simulation languages, but quickly

More information

Lecture 15: System Modeling and Verilog

Lecture 15: System Modeling and Verilog Lecture 15: System Modeling and Verilog Slides courtesy of Deming Chen Intro. VLSI System Design Outline Outline Modeling Digital Systems Introduction to Verilog HDL Use of Verilog HDL in Synthesis Reading

More information

SYSTEM SPECIFICATIONS USING VERILOG HDL. Dr. Mohammed M. Farag

SYSTEM SPECIFICATIONS USING VERILOG HDL. Dr. Mohammed M. Farag SYSTEM SPECIFICATIONS USING VERILOG HDL Dr. Mohammed M. Farag Outline Introduction Basic Concepts Modules and Ports Gate-Level Modeling Dataflow Modeling Behavioral Modeling Tasks and Functions Textbook:

More information

Verilog HDL. A Guide to Digital Design and Synthesis. Samir Palnitkar. SunSoft Press A Prentice Hall Title

Verilog HDL. A Guide to Digital Design and Synthesis. Samir Palnitkar. SunSoft Press A Prentice Hall Title Verilog HDL A Guide to Digital Design and Synthesis Samir Palnitkar SunSoft Press A Prentice Hall Title Table of Contents About the Author Foreword Preface Acknowledgments v xxxi xxxiii xxxvii Part 1:

More information

תכן חומרה בשפת VERILOG הפקולטה להנדסה

תכן חומרה בשפת VERILOG הפקולטה להנדסה תכן חומרה בשפת VERILOG סמסטר ב' תשע"ג משה דורון מרצה: מתרגלים: אריאל בורג, חג'ג' חן הפקולטה להנדסה 1 Course Topics - Outline Lecture 1 - Introduction Lecture 2 - Lexical conventions Lecture 3 - Data types

More information

The Verilog Language COMS W Prof. Stephen A. Edwards Fall 2002 Columbia University Department of Computer Science

The Verilog Language COMS W Prof. Stephen A. Edwards Fall 2002 Columbia University Department of Computer Science The Verilog Language COMS W4995-02 Prof. Stephen A. Edwards Fall 2002 Columbia University Department of Computer Science The Verilog Language Originally a modeling language for a very efficient event-driven

More information

Lecture 32: SystemVerilog

Lecture 32: SystemVerilog Lecture 32: SystemVerilog Outline SystemVerilog module adder(input logic [31:0] a, input logic [31:0] b, output logic [31:0] y); assign y = a + b; Note that the inputs and outputs are 32-bit busses. 17:

More information

CSE140L: Components and Design Techniques for Digital Systems Lab. Verilog HDL. Instructor: Mohsen Imani UC San Diego. Source: Eric Crabill, Xilinx

CSE140L: Components and Design Techniques for Digital Systems Lab. Verilog HDL. Instructor: Mohsen Imani UC San Diego. Source: Eric Crabill, Xilinx CSE140L: Components and Design Techniques for Digital Systems Lab Verilog HDL Instructor: Mohsen Imani UC San Diego Source: Eric Crabill, Xilinx 1 Hardware description languages Used to describe & model

More information

Advanced Digital Design Using FPGA. Dr. Shahrokh Abadi

Advanced Digital Design Using FPGA. Dr. Shahrokh Abadi Advanced Digital Design Using FPGA Dr. Shahrokh Abadi 1 Venue Computer Lab: Tuesdays 10 12 am (Fixed) Computer Lab: Wednesday 10-12 am (Every other odd weeks) Note: Due to some unpredicted problems with

More information

Introduction to Verilog

Introduction to Verilog Introduction to Verilog Structure of a Verilog Program A Verilog program is structured as a set of modules, which may represent anything from a collection of logic gates to a complete system. A module

More information

VLSI II E. Özgür ATES

VLSI II E. Özgür ATES VERILOG TUTORIAL VLSI II E. Özgür ATES Outline Introduction Language elements Gate-level modeling Data-flow modeling Behavioral modeling Modeling examples Simulation and test bench Hardware Description

More information

Chapter 3 Part 2 Combinational Logic Design

Chapter 3 Part 2 Combinational Logic Design University of Wisconsin - Madison ECE/Comp Sci 352 Digital Systems Fundamentals Kewal K. Saluja and Yu Hen Hu Spring 2002 Chapter 3 Part 2 Combinational Logic Design Originals by: Charles R. Kime and Tom

More information

Hardware description language (HDL)

Hardware description language (HDL) Hardware description language (HDL) A hardware description language (HDL) is a computer-based language that describes the hardware of digital systems in a textual form. It resembles an ordinary computer

More information

Verilog for Combinational Circuits

Verilog for Combinational Circuits Verilog for Combinational Circuits Lan-Da Van ( 范倫達 ), Ph. D. Department of Computer Science National Chiao Tung University Taiwan, R.O.C. Fall, 2014 ldvan@cs.nctu.edu.tw http://www.cs.nctu.edu.tw/~ldvan/

More information

Digital Circuit Design and Language. Datapath Design. Chang, Ik Joon Kyunghee University

Digital Circuit Design and Language. Datapath Design. Chang, Ik Joon Kyunghee University Digital Circuit Design and Language Datapath Design Chang, Ik Joon Kyunghee University Typical Synchronous Design + Control Section : Finite State Machine + Data Section: Adder, Multiplier, Shift Register

More information

VERILOG 2: LANGUAGE BASICS

VERILOG 2: LANGUAGE BASICS VERILOG 2: LANGUAGE BASICS Verilog module Modules are basic building blocks. These are two example module definitions which you should use: // Safer traditional method module abc (in1, in2, out); input

More information

271/469 Verilog Tutorial

271/469 Verilog Tutorial 271/469 Verilog Tutorial Prof. Scott Hauck, last revised 8/14/17 Introduction The following tutorial is inted to get you going quickly in circuit design in Verilog. It isn t a comprehensive guide to System

More information

Lecture 2: Data Types, Modeling Combinational Logic in Verilog HDL. Variables and Logic Value Set. Data Types. Why use an HDL?

Lecture 2: Data Types, Modeling Combinational Logic in Verilog HDL. Variables and Logic Value Set. Data Types. Why use an HDL? Why use an HDL? Lecture 2: Data Types, Modeling Combinational Logic in Verilog HDL Increase digital design engineer s productivity (from Dataquest) Behavioral HDL RTL HDL Gates Transistors 2K 10K gates/week

More information

Advanced Digital Design with the Verilog HDL

Advanced Digital Design with the Verilog HDL Copyright 2001, 2003 MD Ciletti 1 Advanced Digital Design with the Verilog HDL M. D. Ciletti Department of Electrical and Computer Engineering University of Colorado Colorado Springs, Colorado ciletti@vlsic.uccs.edu

More information

Synthesis of Combinational and Sequential Circuits with Verilog

Synthesis of Combinational and Sequential Circuits with Verilog Synthesis of Combinational and Sequential Circuits with Verilog What is Verilog? Hardware description language: Are used to describe digital system in text form Used for modeling, simulation, design Two

More information

101-1 Under-Graduate Project Digital IC Design Flow

101-1 Under-Graduate Project Digital IC Design Flow 101-1 Under-Graduate Project Digital IC Design Flow Speaker: Ming-Chun Hsiao Adviser: Prof. An-Yeu Wu Date: 2012/9/25 ACCESS IC LAB Outline Introduction to Integrated Circuit IC Design Flow Verilog HDL

More information

EECS150 - Digital Design Lecture 10 Logic Synthesis

EECS150 - Digital Design Lecture 10 Logic Synthesis EECS150 - Digital Design Lecture 10 Logic Synthesis February 13, 2003 John Wawrzynek Spring 2003 EECS150 Lec8-synthesis Page 1 Logic Synthesis Verilog and VHDL started out as simulation languages, but

More information

EEL 4783: HDL in Digital System Design

EEL 4783: HDL in Digital System Design EEL 4783: HDL in Digital System Design Lecture 15: Logic Synthesis with Verilog Prof. Mingjie Lin 1 Verilog Synthesis Synthesis vs. Compilation Descriptions mapped to hardware Verilog design patterns for

More information

Lecture 3: Modeling in VHDL. EE 3610 Digital Systems

Lecture 3: Modeling in VHDL. EE 3610 Digital Systems EE 3610: Digital Systems 1 Lecture 3: Modeling in VHDL VHDL: Overview 2 VHDL VHSIC Hardware Description Language VHSIC=Very High Speed Integrated Circuit Programming language for modelling of hardware

More information

Federal Urdu University of Arts, Science and Technology, Islamabad VLSI SYSTEM DESIGN. Prepared By: Engr. Yousaf Hameed.

Federal Urdu University of Arts, Science and Technology, Islamabad VLSI SYSTEM DESIGN. Prepared By: Engr. Yousaf Hameed. VLSI SYSTEM DESIGN Prepared By: Engr. Yousaf Hameed Lab Engineer BASIC ELECTRICAL & DIGITAL SYSTEMS LAB DEPARTMENT OF ELECTRICAL ENGINEERING VLSI System Design 1 LAB 01 Schematic Introduction to DSCH and

More information

a, b sum module add32 sum vector bus sum[31:0] sum[0] sum[31]. sum[7:0] sum sum overflow module add32_carry assign

a, b sum module add32 sum vector bus sum[31:0] sum[0] sum[31]. sum[7:0] sum sum overflow module add32_carry assign I hope you have completed Part 1 of the Experiment. This lecture leads you to Part 2 of the experiment and hopefully helps you with your progress to Part 2. It covers a number of topics: 1. How do we specify

More information

VERILOG. Deepjyoti Borah, Diwahar Jawahar

VERILOG. Deepjyoti Borah, Diwahar Jawahar VERILOG Deepjyoti Borah, Diwahar Jawahar Outline 1. Motivation 2. Basic Syntax 3. Sequential and Parallel Blocks 4. Conditions and Loops in Verilog 5. Procedural Assignment 6. Timing controls 7. Combinatorial

More information

ENGIN 241 Digital Systems with Lab

ENGIN 241 Digital Systems with Lab ENGIN 241 Digital Systems with Lab (4) Dr. Honggang Zhang Engineering Department University of Massachusetts Boston 1 Introduction Hardware description language (HDL): Specifies logic function only Computer-aided

More information

What is Verilog HDL? Lecture 1: Verilog HDL Introduction. Basic Design Methodology. What is VHDL? Requirements

What is Verilog HDL? Lecture 1: Verilog HDL Introduction. Basic Design Methodology. What is VHDL? Requirements What is Verilog HDL? Lecture 1: Verilog HDL Introduction Verilog Hardware Description Language(HDL)? A high-level computer language can model, represent and simulate digital design Hardware concurrency

More information

Verilog 1 - Fundamentals

Verilog 1 - Fundamentals Verilog 1 - Fundamentals FA FA FA FA module adder( input [3:0] A, B, output cout, output [3:0] S ); wire c0, c1, c2; FA fa0( A[0], B[0], 1 b0, c0, S[0] ); FA fa1( A[1], B[1], c0, c1, S[1] ); FA fa2( A[2],

More information

Hardware description languages

Hardware description languages Specifying digital circuits Schematics (what we ve done so far) Structural description Describe circuit as interconnected elements Build complex circuits using hierarchy Large circuits are unreadable Hardware

More information

Verilog 1 - Fundamentals

Verilog 1 - Fundamentals Verilog 1 - Fundamentals FA FA FA FA module adder( input [3:0] A, B, output cout, output [3:0] S ); wire c0, c1, c2; FA fa0( A[0], B[0], 1 b0, c0, S[0] ); FA fa1( A[1], B[1], c0, c1, S[1] ); FA fa2( A[2],

More information

Synthesis vs. Compilation Descriptions mapped to hardware Verilog design patterns for best synthesis. Spring 2007 Lec #8 -- HW Synthesis 1

Synthesis vs. Compilation Descriptions mapped to hardware Verilog design patterns for best synthesis. Spring 2007 Lec #8 -- HW Synthesis 1 Verilog Synthesis Synthesis vs. Compilation Descriptions mapped to hardware Verilog design patterns for best synthesis Spring 2007 Lec #8 -- HW Synthesis 1 Logic Synthesis Verilog and VHDL started out

More information

Verilog HDL. Lecture #6. Madhu Mutyam Dept. of Computer Science and Engineering Indian Institute of Technology, Madras

Verilog HDL. Lecture #6. Madhu Mutyam Dept. of Computer Science and Engineering Indian Institute of Technology, Madras Verilog HDL Lecture #6 Madhu Mutyam Dept. of Computer Science and Engineering Indian Institute of Technology, Madras madhu@cse.iitm.ac.in 2 Verilog RTL Structural Level Verilog allows a designer to develop

More information