# Combinational Logic II

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2 x y x y S x y C Figure 1: Half adder. x y S C Figure 2: Half adder, XOR implementation. Figure 1 shows this implementation. Following is equivalent: Figure 2 shows this implementation. S = x y, C = x y. Full Adder A full adder is a combinational circuit that forms the arithmetic sum of three bits. Two of the input variables, x and y, represent the two significant bits to be added. The third input, z, represents the carry from the previous lower significant position. Table 2 is the truth table of a full adder. Table 2: Full adder. x y z C S

5 The output sum and carry can be expressed as S i = P i C i, C i+1 = G i + P i C i. G i is called a carry generator and it produces a carry of 1 when both A i and B i are 1, regardless of the input carry C i. P i is called the carry propagate, because it determines whether a carry into state i will propagate into stage i + 1 (i.e., whether the assertion of C i will propagate to an assertion of C i+1 ). Now we write Boolean functions for the carry outputs of each stage and substitute the value of each C i form the previous equations: C 0 = input carry, C 1 = G 0 + P 0 C 0, C 2 = G 1 + P 1 C 1 = G 1 + P 1 (G 0 + P 0 C 0 ) = G 1 + P 1 G 0 + P 1 P 0 C 0, C 3 = G 2 + P 2 C 2 == G 2 + P 2 G 1 + P 2 P 1 G 0 + P 2 P 1 P 0 C 0. Since the Boolean function of each output carry is expressed in sum-of-product form, each function can be implemented withe one level of AND gates followed by and OR gate. In this case, C 3 does not have to wait for C 2 and C 1 to propagate; in fact, C 3 is propagated at the same time as C 1 and C 2. This gain in speed is achieved at the expense of additional complexity. 5

7 computers detect the occurrence of an overflow, and when it occurs, a corresponding flip-flop is se that can be checked by the user. 2 Binary Multiplier Multiplication of binary numbers is performed the same way as multiplication of decimal numbers. B 1 B 0 A 1 A 0 A 0 B 1 A 0 B 0 A 1 B 1 A 1 B 0 C 3 C 2 C 1 C 0 In relation to the partial products such as A 0 B 0, we notice that the operation is identical to an AND operation. Therefore, partial products can be implemented with AND gates. Addition of partial products can be done using half adders. 7

8 3 Magnitude Comparator The comparison of two numbers is an operation that determines whether one number is greater than, less than, or equal to another number. Consider two numbers, A and B, with four digits each. Let s write the coefficients of the numbers in decreasing order of significance: A = A 3 A 2 A 1 A 0, B = B 3 B 2 B 1 B 0. The two numbers are qual if pairs of significant digits are equal: A 3 = B 3, A 2 = B 2, A 1 = B 1, and A 0 = B 0. When the number are binary, the equality of each pair can be expressed logically with and XNOR function: x i = A i B i + A i B i, for i = 0,1,2,3, where x i = 1 only if the pair of bits in position i are equal. For equality to exist, all x i must be equal to 1: (A = B) = x 3 x 2 x 1 x 0. to determine whether A is greater than or less than B, we inspect the relative magnitudes of pairs of significant digits, starting from the most significant position. If the two digits of a pair are equal, we compare the next lower significant pair of digits. The comparison continues until a pair of unequal digits are reached. If the corresponding digit of A is 0 and that of B is 1, we have A < B. (A > B) = A 3 B 3 + x 3 A 2 B 2 + x 3x 2 A 1 B 1 + x 3x 2 x 1 A 0 B 0, (A < B) = A 3 B 3 + x 3 A 2 B 2 + x 3 x 2 A 1 B 1 + x 3 x 2 x 1 A 0 B 0. 8

9 A 2 A 1 A 0 D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 Figure 5: A 3-to-8 decoder. 4 Combinational Logic Using Decoders We studied that a decoder is a combinational circuit that converts binary information from n input lines to a maximum of 2 n unique output lines. In the n-bit coded information has unused combinations, the decoder may have fewer than 2 n outputs. These decoders are called n-tom-line decoders, where m 2 n. Their purpose is to generate the 2 n (or fewer) minterms of n variables. Figure 5 shows a 3-to-8 decoder. A decoder provides 2 n minterms of n input variables. Each asserted output of the decoder is associated with a unique pattern of bits. Since any Boolean function can be expressed in sum-of-minterm form, a decoder generates the minterms of a function, together with an external OR gate, that forms their logical sum, provides a hardware implementation of the function. In this way, any combinational circuit with n inputs and m outputs can be implemented with an n-to-2 n decoder and m OR gates. Example 1. Implement a full adder using a 3 8 decoder. 9

10 Table 3: Truth table for octal-to-binary encoder. Inputs Outputs D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 A 2 A 1 A Table 4: Truth table for priority encoder. Inputs Outputs D 0 D 1 D 2 D 3 x y V X X X X X X X X Encoders An encoder is a digital circuit that performs the inverse operation of a decoder. An encoder has 2 n (or fewer) input lines and n output lines. The output lines, as an aggregate, generate the binary code corresponding to the input value. An example of an encoder is the octal-to-binary encoder whose truth table is given in Table 3. It has eight inputs one for each of the octal digits and three outputs that generate the corresponding binary number. It is assumed that only one input has the value of 1 at any given time. Priority Encoder A priority encoder is an encoder circuit that includes a priority function. The operation of the priority encoder is such that if two or more inputs are equal to 1 at the same time, the input having the highest priority will take precedence. The truth table of a priority encoder is shown in 4. In addition to the two outputs x and y, the circuit has a third output designated by V ; this is a valid bit indicator that is set to 1 when one or more inputs ar equal to 1. If all the inputs are 0, there is no valid input and V is equal to 0. Example 2. Design the priority encoder represented by the truth table in Table 4. 10

11 I 0 Y I 1 S Figure 6: An 2-to-1 multiplexer. Table 5: Truth table for priority encoder. x y z F F = z F = z F = F = Multiplexers A multiplexer is a combinational circuit that selects binary information from one of many input lines and directs it to a single output line. The selection of a particular input line is controlled by a set of selection lines. Normally, there are 2 n input lines and n selection lines whose bit combination determines which output is selected. Figure 6 shows a 2-to-1 multiplexer. Figure 7 shows a 8-to-1 multiplexer. Boolean Function Implementation Using Multiplexers Logic diagram of a multiplexer reveals that it is essentially a decoder that includes the OR gate within the unit. The minterms of a function are generated in a multiplexer by the circuit associated with the selection inputs. The individual minterms can be selected by the data inputs, thereby providing a method of implementing a Boolean function of n variables with a multiplexer that has n selection inputs and 2 n data inputs, one for each minterm. However, it is possible to implement an n-variable Boolean function using a multiplexer that has n 1 selection inputs. the first n 1 variables of the function are connected to the selection inputs of the multiplexer. the remaining single variable of the function is used for the data inputs. Example 3. Implement the Boolean function F (x, y, x) = (1,2,6,7) using a 2-to-1 multiplexer. Table 5 shows the truth table. 11

12 I 0 I 1 I 2 I 3 I 4 I 5 I 6 I 7 S 2 S 1 S 0 Ē Ȳ Y Figure 7: An 8-to-1 multiplexer. Example 4. Implement F (A,B,C,D) = (1,3,4,11,12,13,14,15) using a suitable multiplexer. Three-State Gates A multiplexer can be constructed with three-state gates digital circuits that exhibit three states. Two of the states are signal equivalent of logic 1 and logic 0 as in a conventional gate. The third state is a high-impedance state in which 1. the logic behaves like an open circuit, which means that the output appears to be disconnected, 2. the circuit has not logic significance, and 3. the circuit connected to the output of the three-state gate is not affected by the inputs to the gate. The three-state gate most commonly used is a buffer gate. Example 5. Draw a 2-to-1 multiplexer using three-state buffers. 12

13 7 HDL Models for Combinational Circuits As mentioned previously, the module is the basic building block for modeling hardware with the Verilog HDL. The logic of a module can be described in any one (or a combination) of the following modeling styles: 1. gate-level modeling using instantiations of predefined and user-defined primitive gates, 2. dataflow modeling using continuous assignment statements with the keyword assign, and 3. behavioral modeling using procedural assignment statements with the keyword always. Gate-level (structural) modeling describes a circuit by specifying its gates and how they are connected with each other. Dataflow modeling is used mostly for describing the Boolean equations of combinational logic. Behavioral modeling describes combinational and sequential logic at a higher level of abstraction. There is another modeling style, called switch-level modeling, which is sometimes used in the MOS transistor models, but not in logic synthesis. Gate-Level Modeling We studied gate-level modeling previously. Gate-level modeling provides a textual description of a schematic diagram. The Verilog HDL includes 12 basic gates as predefined primitives. Four of these primitive gates are three-state type. The other eight are the same are regular types. They are all declared with the lowercase keywords and, nand, or, nor, xor, xnor, not, and buf. Primitives such as and are n- input primitives. The buf and not primitives are n-output primitives. A single input can drive multiple output lines distinguished by their identifiers. The logic of each gate is based on a four-valued system. When the gates are simulated, the simulator assigns one value to the output of each gate at any instant. In addition to the two logic values of 0 and 1, there are two other values: unknown and high impedance. An unknown values is demoted by x and a high impedance by z. An unknown value is assigned during the simulation when the logic value of the signal is ambiguous for instance, if it cannot be determined whether its value is 0 or 1. A high-impedance condition occurs at the output of three-state gates that are not enabled or if a wire is inadvertently left unconnected. The four-valued logic truth tables for and, or, xor, and not are shown in Table 6. Identifiers Having Multiple-Bit Widths (Vectors) The syntax for specifying a vector includes within square brackets two numbers separated with a colon. output [ 0 : 3 ] D; wire [ 7 : 0 ] SUM; The first (leftmost) number (array index) listed is always the most significant bit of the vector. The individual bits are specified using square brackets, so D[2] specifies the bit 2 of D. It is possible to address contiguous parts of vectors. For example, SUM[2:0] specifies the three least significant bits of vector SUM. Listing 1 shows a 2-to-4 decoder (already discussed). 13

14 Table 6: Truth tables for predefined primitive gates. and 0 1 x z or 0 1 x z x x x x x 0 x x x x x 1 x x z 0 x x x z x 1 x x xor 0 1 x z x x x x x x x x x z x x x x not input output x x z x Listing 1: 2-to-4 Decoder module decoder_2x4_gates (D, A, B, enable ) ; output [ 0 : 3] D; input A, B ; input enable ; wire A_not, B_not, enable_not ; not G1 ( A_not, A), G2 ( B_not, B), G3 ( enable_not, enable ) ; nand G4 (D[ 0 ], A_not, B_not, enable_not ), G5 (D[ 1 ], A_not, B, enable_not ), G6 (D[ 2 ], A, B_not, enable_not ), G7 (D[ 3 ], A, B, enable_not ) ; endmodule Two or more modules can be combined to build a hierarchical description of a design. There are two basic types of design methodologies: top-down and bottomup. In a top-down design the top-level block is defined and then the subblocks necessary to build the top-level block are identified. In a bottom-up design, the building blocks are first identified and then combined to build the top-level block. Example 6. Using a bottom-up methodology design a four-bit adder in HDL. Modules can be instantiated (nested) within other modules, but module declarations cannot be nested. The only way one module definition can be incorporated into another is module is by instantiation it. Instantiating modules within other modules creates a hierarchical decomposition of a design. A description of a module is said to be a structural description if it is composed of instantiations of other modules. Instance names (e.g., FA0) must be specified when defined modules are instantiated. Three-State Gates A three-state gate has a control input that can place the grate into a high0impedance state. The high-impedance state is symbolized by z in Verilog. There are four types of three-state gates. 14

15 Table 7: Some Verilog HDL operators. + binary addition binary subtraction & bitwise AND bitwise OR ^ bitwise XOR ~ bitwise NOT == equality > greater than < less than { } concatenation?: conditional bufif1 bufif0 bnotif1 bnotif0 behaves like a normal buffer if control = 1. The output goes to a highimpedance state z when control = 0. behaves like a normal buffer if control = 0. The output goes to a highimpedance state z when control = 1. operate in a similar manner as bufif1, except that the output is the complement of the input. operate in a similar manner as bufif0, except that the output is the complement of the input. Listing 2 shows a 2-to-1 multiplexer implementation using three-state gates. Listing 3 is a simple test bench for the multiplexer. Listing 2: Mux with three-state output. module mux_tri ( output m_out, input A, B, sel ) ; bufif1 B1(m_out, A, sel ) ; bufif0 B2(m_out, B, sel ) ; endmodule module tmux_tri ; reg A, B, sel ; wire m_out ; Listing 3: Test bench for the mux. mux_tri dut (m_out, A, B, sel ) ; i n i t i a l begin s e l = 1 b1 ; A = 1 b0 ; #100 A = 1 b1 ; #100 sel = 1 b0 ; B = 1 b0 ; #100 B = 1 b1 ; end endmodule Dataflow Modeling Dataflow modeling of combinational logic uses a number of operators that act on operands to produce desired results. Verilog HDL provides about 30 different operators. Table 7 shows some of these. Dataflow modeling uses continuous assignments and the keyword assign. A continuous assignment is a statement that assigns a value to a net. The data type 15

16 family net is used in Verilog to represent a physical connection between circuit elements. A net is declared explicitly by a net keyword (e.g., wire) or by declaring an identifier to be an output port. The logic values associated with the net is determined by what the net is connected to. If the net is connected to the output of a gate, the net is said to be driven by the gate, and the logic value of the net is determined by the logic value of the inputs to the gate and the truth table of the gate. If the identifier of a net is the left-hand side of a continuous assignment statement, the value assigned to the net is specified by an expression that uses operands and operators. As an example, assuming that the variables were declared, a two-to-one-line multiplexer with data inputs A and B, select input S, and output Y is described with the continuous assignment assign Y = (A&S ) ( B&~S ) ; Example 7. Design a two-to-four-line decoder using dataflow assignment. 16

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