CprE 281: Digital Logic

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1 CprE 281: Digital Logic Instructor: Alexander Stoytchev

2 Intro to Verilog CprE 281: Digital Logic Iowa State University, Ames, IA Copyright Alexander Stoytchev

3 Administrative Stuff HW3 is due on Monday Sep 4p

4 Administrative Stuff HW4 is out It is due on Monday Sep 4pm. Please write clearly on the first page (in BLOCK CAPITAL letters) the following three things: Your First and Last Name Your Student ID Number Your Lab Section Letter Also, please Staple your pages

5 Administrative Stuff TA Office Hours: 11:00am-1:00pm on Wednesdays (Jinyuan Jia) Location: TLA (Coover Hall - first floor) 9:50am-11:50am on Thursday (Siyuan Lu) Location: TLA (Coover Hall - first floor)

6 Midterm Exam #1 Administrative Stuff When: Friday Sep 23. Where: This classroom What: Chapter 1 and Chapter 2 plus number systems The exam will be open book and open notes (you can bring up to 3 pages of handwritten notes). More details to follow.

7 Quick Review

8 NAND followed by NOT = AND x 1 x x 1 2 x x 1 2 x 1 x x 1 2 x 2 x 2 x 1 x 2 f f x 1 x 2 f

9 DeMorgan s Theorem

10 DeMorgan s Theorem x y x y = x y x y x + y

11 Sum-Of-Products x 1 x 2 x 3 x 4

12 Sum-Of-Products AND x 1 x 2 OR x 3 x 4 AND

13 Sum-Of-Products AND x 1 x 2 OR x 3 x 4 AND x 1 x x 1 2 x x 1 2 x 2 + x x 1 x x x 3 x 4 x x 3 4 x x 3 4

14 Sum-Of-Products AND x 1 x 2 OR x 3 x 4 AND AND x 1 x 2 x x 1 2 x x OR x x 1 x x x 3 x x 3 4 x x 3 4 x 4 AND

15 Sum-Of-Products AND x 1 x 2 OR x 3 x 4 AND x 1 x x 1 2 x x 1 2 x 2 + x x 1 x x x 3 x 4 x x 3 4 x x 3 4

16 Sum-Of-Products AND x 1 x 2 OR x 3 x 4 AND x 1 x x 1 2 x x 1 2 NAND x 2 + x x 1 x x x 3 x x 3 4 x x 3 4 x 4

17 Sum-Of-Products AND x 1 x 2 OR x 3 x 4 AND x 1 x x 1 2 x 2 + x x 1 x x x 3 x x 3 4 x 4

18 Sum-Of-Products x 1 x 2 x 3 x 4 x 5 x 1 x 2 x 3 x 4 x 5 x 1 x 2 x 3 x 4 x 5

19 2-1 Multiplexer (Definition) Has two inputs: x 1 and x 2 Also has another input line s If s=0, then the output is equal to x 1 If s=1, then the output is equal to x 2

20 Graphical Symbol for a 2-1 Multiplexer s x 1 x f [ Figure 2.33c from the textbook ]

21 Let s Derive the SOP form s x 1 x 2 s x 1 x 2 s x 1 x 2 s x 1 x 2 f (s, x 1, x 2 ) = s x 1 x 2 + s x 1 x 2 + s x 1 x 2 + s x 1 x 2

22 Let s simplify this expression f (s, x 1, x 2 ) = s x 1 x 2 + s x 1 x 2 + s x 1 x 2 + s x 1 x 2 f (s, x 1, x 2 ) = s x 1 (x 2 + x 2 ) + s (x 1 +x 1 )x 2 f (s, x 1, x 2 ) = s x 1 + s x 2

23 Circuit for 2-1 Multiplexer x 1 s s x 2 f x 1 x f (b) Circuit (c) Graphical symbol [ Figure 2.33b-c from the textbook ]

24 Analogy: Railroad Switch

25 Analogy: Railroad Switch x 1 x 2 select f

26 Analogy: Railroad Switch x 1 x 2 select f This is not a perfect analogy because the trains can go in either direction, while the multiplexer would only allow them to go from top to bottom.

27 More Compact Truth-Table Representation s x 1 x 2 f (s, x 1, x 2 ) (a) Truth table s 0 1 f (s, x 1, x 2 ) x 1 x 2 [ Figure 2.33 from the textbook ]

28 4-1 Multiplexer (Definition) Has four inputs: w 0, w 1, w 2, w 3 Also has two select lines: s 1 and s 0 If s 1 =0 and s 0 =0, then the output f is equal to w 0 If s 1 =0 and s 0 =1, then the output f is equal to w 1 If s 1 =1 and s 0 =0, then the output f is equal to w 2 If s 1 =1 and s 0 =1, then the output f is equal to w 3 We ll talk more about this when we get to chapter 4, but here is a quick preview.

29 Graphical Symbol and Truth Table [ Figure 4.2a-b from the textbook ]

30 The long-form truth table [

31 4-1 Multiplexer (SOP circuit) [ Figure 4.2c from the textbook ]

32 Using three 2-to-1 multiplexers to build one 4-to-1 multiplexer s 1 s 0 w 0 w f w 2 w [ Figure 4.3 from the textbook ]

33 Analogy: Railroad Switches

34 Analogy: Railroad Switches w 0 w 1 w 2 w 3 s 1 f

35 Analogy: Railroad Switches w 0 w 1 w 2 w 3 s 0 these two switches are controlled together s 1 f

36 Using three 2-to-1 multiplexers to build one 4-to-1 multiplexer

37 Using three 2-to-1 multiplexers to build one 4-to-1 multiplexer w 0 s 1 s 0 w 1 w 2 f w 3

38 That is different from the SOP form of the 4-1 multiplexer shown below, which uses less gates

39 16-1 Multiplexer s 0 s 1 w 0 w 3 w 4 s 2 s 3 w 7 f w 8 w 11 w 12 w 15 [ Figure 4.4 from the textbook ]

40 [

41 7-Segment Display Example

42 Display of numbers [ Figure 2.34 from the textbook ]

43 Display of numbers

44 Display of numbers a = s 0 c = s 1 e = s 0 g = s 1 s 0 b = 1 d = s 0 f = s 1 s 0

45 Intro to Verilog

46 Created in 1983/1984 History Verilog-95 (IEEE standard ) Verilog 2001 (IEEE Standard ) Verilog 2005 (IEEE Standard ) SystemVerilog SystemVerilog 2009 (IEEE Standard ).

47 HDL Hardware Description Language Verilog HDL VHDL

48 Verilog HDL!= VHDL These are two different Languages! Verilog is closer to C VHDL is closer to Ada

49 [ Figure 2.35 from the textbook ]

50 Hello World in Verilog [

51 The Three Basic Logic Gates x x x 1 x x 1 x 2 2 x 1 x x 1 + x 2 2 NOT gate AND gate OR gate [ Figure 2.8 from the textbook ]

52 How to specify a NOT gate in Verilog x x NOT gate

53 How to specify a NOT gate in Verilog we ll use the letter y for the output x y NOT gate

54 How to specify a NOT gate in Verilog x y not (y, x) NOT gate Verilog code

55 How to specify an AND gate in Verilog x 1 f= x x 1 x 2 2 and (f, x1, x2) AND gate Verilog code

56 How to specify an OR gate in Verilog x 1 f= x x 1 + x 2 2 or (f, x1, x2) OR gate Verilog code

57 2-1 Multiplexer [ Figure 2.36 from the textbook ]

58 Verilog Code for a 2-1 Multiplexer [ Figure 2.36 from the textbook ] [ Figure 2.37 from the textbook ]

59 Verilog Code for a 2-1 Multiplexer [ Figure 2.36 from the textbook ] [ Figure 2.40 from the textbook ]

60 Verilog Code for a 2-1 Multiplexer [ Figure 2.36 from the textbook ] [ Figure 2.42 from the textbook ]

61 Verilog Code for a 2-1 Multiplexer [ Figure 2.36 from the textbook ] [ Figure 2.43 from the textbook ]

62 Another Example

63 Let s Write the Code for This Circuit [ Figure 2.39 from the textbook ]

64 Let s Write the Code for This Circuit module example2 (x1, x2, x3, x4, f, g, h); input x1, x2, x3, x4; output f, g, h; endmodule and (z1, x1, x3); and (z2, x2, x4); or (g, z1, z2); or (z3, x1, ~x3); or (z4, ~x2, x4); and (h, z3, z4); or (f, g, h); [ Figure 2.39 from the textbook ] [ Figure 2.38 from the textbook ]

65 Let s Write the Code for This Circuit module example4 (x1, x2, x3, x4, f, g, h); input x1, x2, x3, x4; output f, g, h; endmodule assign g = (x1 & x3) (x2 & x4); assign h = (x1 ~x3) & (~x2 x4); assign f = g h; [ Figure 2.39 from the textbook ] [ Figure 2.41 from the textbook ]

66 Yet Another Example

67 A logic circuit with two modules [ Figure 2.44 from the textbook ]

68 The adder module [ Figure 2.12 from the textbook ]

69 The adder module [ Figure 2.45 from the textbook ]

70 The display module a = s 0 c = s 1 e = s 0 g = s 1 s 0 b = 1 d = s 0 f = s 1 s 0

71 The display module a = s 0 b = 1 c = s 1 d = s 0 e = s 0 f = s 1 s 0 g = s 1 s 0 [ Figure 2.46 from the textbook ]

72 Putting it all together

73 Questions?

74 THE END

CprE 281: Digital Logic

CprE 281: Digital Logic Instructor: Alexander Stoytchev http://www.ece.iastate.edu/~alexs/classes/ Intro to Verilog CprE 281: Digital Logic Iowa State University, Ames, IA Copyright Alexander Stoytchev