Fundamentals of Computer Systems

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1 Fundamentals of Computer Systems Combinational Logic Martha. Kim Columbia University Spring 6 /

2 Combinational Circuits Combinational circuits are stateless. Their output is a function only of the current input. Inputs Combinational Circuit Outputs /

3 Basic Combinational Circuits Encoders and Decoders Multiplexers Shifters Circuit Timing Critical and Shortest Paths Glitches rithmetic Circuits Ripple Carry dder dder/subtractor Carry Lookahead dder /

4 Overview: Decoder decoder takes a k bit input and produces k single-bit outputs. The input determines which output will be, all others. This representation is called one-hot encoding. O I O I O O 4 /

5 : Decoder The smallest decoder: one bit input, two bit outputs 5 /

6 :4 Decoder Decoder outputs are simply minterms. Those values can be constructed as a flat schematic (manageable at small sizes) or hierarchically, as below. B B : DEC B B B : DEC B B 6 /

7 :8 Decoder pplying hierarchical design again, the :4 DEC helps construct a :8 DEC. : DEC BC BC BC B C BC BC :4 DEC BC B C B C BC BC BC B C 7 /

8 Priority Encoder n encoder designed to accept any input bit pattern. I I I I V O O X X X X X X X X V = I + I + I + I O = I + I I O = I + I I I 8 /

9 Overview: Multiplexer (or Mux) mux has a k bit selector input and k data inputs (multi or single bit). It outputs a single data output, which has the value of one of the data inputs, according to the selector. D IN C B IN IN OUT B IN S S 9 /

10 : Mux Circuit There are a handful of implementation strategies. E.g., a truth table and k-map are feasible for a design of this size. S I I /

11 : Mux Circuit There are a handful of implementation strategies. E.g., a truth table and k-map are feasible for a design of this size. S I I I S I O

12 : Mux Circuit There are a handful of implementation strategies. E.g., a truth table and k-map are feasible for a design of this size. S I I I S I : Decoder! O /

13 4: Mux Circuit I I O I I EN EN EN EN :4 DEC S S /

14 Muxing Wider Values (Overview) I I O I I EN EN EN EN :4 DEC S S /

15 Muxing Wider Values (Components) X X X X Y Y Y Y EN X X X X Z Z Z Z Y Y Y Y /

16 Overview: Shifters shifter shifts the inputs bits to the left or to the right. IN n SHIFTER k CNTL n OUT There are various types of shifters. Barrel: Selector bits indicate (in binary) how far to the left to shift the input. L/R with enable: Two control bits (upper enables, lower indicates direction). In either case, bits may roll out or wraparound 4 /

17 Example: Barrel Shifter with Wraparound 8 SHIFTER 8 5 /

18 Implementation of Barrel Shifter with Wraparound (Part ) Main idea: wire up all possible shift amounts and use muxes to select correct one. IN IN IN IN OUT OUT OUT OUT

19 Implementation of Barrel Shifter with Wraparound (Part ) Main idea: wire up all possible shift amounts and use muxes to select correct one. IN IN IN IN CNTL, CNTL OUT OUT OUT OUT

20 Implementation of Barrel Shifter with Wraparound (Part ) Main idea: wire up all possible shift amounts and use muxes to select correct one. IN IN IN IN CNTL, CNTL OUT OUT OUT OUT

21 Implementation of Barrel Shifter with Wraparound (Part ) Main idea: wire up all possible shift amounts and use muxes to select correct one. IN IN IN IN CNTL, CNTL OUT OUT OUT OUT

22 Implementation of Barrel Shifter with Wraparound (Part ) Main idea: wire up all possible shift amounts and use muxes to select correct one. IN IN IN IN CNTL, CNTL OUT OUT OUT OUT

23 Implementation of Barrel Shifter with Wraparound (Part ) Main idea: wire up all possible shift amounts and use muxes to select correct one. IN IN IN IN CNTL, CNTL OUT OUT OUT OUT 6 /

24 Computation lways Takes Time 74LS There is a delay between inputs and outputs, due to: Limited currents charging capacitance The speed of light 7 /

25 The Simplest Timing Model In Out t p Each gate has its own propagation delay t p. When an input changes, any changing outputs do so after t p. Wire delay is zero. 8 /

26 More Realistic Timing Model In Out t p(max) t p(min) It is difficult to manufacture two gates with the same delay; better to treat delay as a range. Each gate has a minimum and maximum propagation delay t p(min) and t p(max). Outputs may start changing after t p(min) and stablize no later than t p(max). 9 /

27 Critical Paths and Short Paths B C D Y How slow can this be? /

28 Critical Paths and Short Paths B C D Y How slow can this be? The critical path has the longest possible delay. t p(max) = t p(max, ND) + t p(max, OR) + t p(max, ND) /

29 Critical Paths and Short Paths B C D Y How fast can this be? The shortest path has the least possible delay. t p(min) = t p(min, ND) /

30 Glitches glitch is when a single change in input values can cause multiple output changes. B F C Glitches may occur when there are multiple paths of different length from input I to output O.

31 Glitches glitch is when a single change in input values can cause multiple output changes. B F C Glitches may occur when there are multiple paths of different length from input I to output O.

32 Glitches glitch is when a single change in input values can cause multiple output changes. B F C Glitches may occur when there are multiple paths of different length from input I to output O.

33 Glitches glitch is when a single change in input values can cause multiple output changes. B F C Glitches may occur when there are multiple paths of different length from input I to output O. /

34 Preventing Single Input Glitches dditional terms can prevent single input glitches (at a cost of a few extra gates). B C B F C /

35 Preventing Single Input Glitches dditional terms can prevent single input glitches (at a cost of a few extra gates). B C B F C /

36 rithmetic: ddition dding two one-bit numbers: and B Produces a two-bit result: C and S (carry and sum) B C S B Half dder C S /

37 Full dder In general, due to a possible carry in, you need to add three bits: C o C i B C o S C i B C o S C i B S 4 /

38 Four-Bit Ripple-Carry dder B B B B B C o F C i F F F F S S 4 S S S S 5 /

39 Two s Complement dder/subtractor To subtract B from, add and B. Neat trick: carry in takes care of the + operation. B B B B SUBTRCT/DD F F F F S 4 S S S S 6 /

40 Overflow in Two s-complement Representation When is the result too positive or too negative? /

41 Overflow in Two s-complement Representation When is the result too positive or too negative? + + % + % + The result does not fit when the top two carry bits differ. n Bn n Bn S n S n % Overflow 7 /

42 Ripple-Carry dders are Slow B B B B C C4 S S S S The depth of a circuit is the number of gates on a critical path. This four-bit adder has a depth of 8. n-bit ripple-carry adders have a depth of n. 8 /

43 Carry Generate and Propagate The carry chain is the slow part of an adder; carry-lookahead adders reduce its depth using the following trick: C B K-map for the carry-out function of a full adder For bit i, C i+ = i B i + i C i + B i C i = i B i + C i ( i + B i ) = G i + C i P i Generate G i = i B i sets carry-out regardless of carry-in. Propagate P i = i + B i copies carry-in to carry-out. 9 /

44 Carry Lookahead dder Expand the carry functions into sum-of-products form: C i+ = G i + C i P i C = G + C P C = G + C P = G + (G + C P )P = G + G P + C P P C = G + C P = G + (G + G P + C P P )P = G + G P + G P P + C P P P C 4 = G + C P = G + (G + G P + G P P + C P P P )P = G + G P + G P P + G P P P + C P P P P /

45 Carry-Lookahead dder Size and Timing B4 4 9 C4 Σ4 Carry out i has i + product terms, largest of which has i + literals. B B B C The 748 Binary Carry-Lookahead dder (From National Semiconductor) 4 Σ Σ Σ If wide gates don t slow down, delay is independent of number of bits. More realistic: if limited to two-input gates, depth is O(log n). /

Fundamentals of Computer Systems

Fundamentals of Computer Systems Combinational Logic Stephen. Edwards Columbia University Summer 7 Combinational Circuits Combinational circuits are stateless. Their output is a function only of the current