Cache Memories. Andrew Case. Slides adapted from Jinyang Li, Randy Bryant and Dave O Hallaron
|
|
- Noel West
- 5 years ago
- Views:
Transcription
1 Cache Memories Andrew Case Slides adapted from Jinyang Li, Randy Bryant and Dave O Hallaron 1
2 Topics Cache memory organiza3on and opera3on Performance impact of caches 2
3 Cache Memories Cache memories are small, fast SRAM- based memories Hold frequently accessed blocks of main memory Managed automaecally in hardware CPU looks first for data in caches (e.g., L1, L2, and L3), then in main memory. Typical system structure: CPU chip Register file Cache memories ALU System bus Memory bus Bus interface I/O bridge Main memory 3
4 General Cache Organiza3on (S, E, B) E = lines per set (2 e ) S = num sets (2 s ) line set valid bit v tag B- 1 Cache size: C = S x E x B data bytes most significant memory bits B = bytes per cache block (the data) (2 b ) 4
5 Cache Read E = 2 e lines per set Locate set Check if any line in set has matching tag If Match + valid: hit Locate data starang at offset Address of word: t bits s bits b bits S = 2 s sets tag set index block offset MSB memory address (address_size s - b) data begins at this offset v tag B- 1 valid bit B = 2 b bytes per cache block (the data) 5
6 Example: Direct Mapped Cache (E = 1) Direct mapped: One line per set Assume: cache block size 8 bytes S = 2 s sets v tag v tag v tag Address of int: t bits find set v tag
7 Example: Direct Mapped Cache (E = 1) Direct mapped: One line per set Assume: cache block size 8 bytes valid? + match = hit Address of int: t bits v tag block offset 7
8 Example: Direct Mapped Cache (E = 1) Direct mapped: One line per set Assume: cache block size 8 bytes valid? + match = hit Address of int: t bits v tag block offset int (4 Bytes) is here On cache miss: old line is evicted and replaced 8
9 Direct- Mapped (E=1) Cache Simula3on t=1 s=2 b=1 x xx x M=16 byte addresses B=2 bytes/block S=4 sets E=1 Blocks/set Address trace (reads, one byte per read): 0 [ ], miss 1 [ ], hit 7 [ ], miss 8 [ ], miss 0 [ ] miss Set 0 Set 1 Set 2 Set 3 v Tag Block ? M[8-9] M[0-1]? 1 0 M[6-7] 9
10 A Higher Level Example int sum_array_rows(double a[16][16]) { int i, j; double sum = 0; Ignore the variables sum, i, j (stored in registers) assume: cold (empty) cache, a[0][0] goes here for (i = 0; i < 16; i++) for (j = 0; j < 16; j++) sum += a[i][j]; return sum; int sum_array_cols(double a[16][16]) { int i, j; double sum = 0; for (j = 0; i < 16; i++) for (i = 0; j < 16; j++) sum += a[i][j]; return sum; 32 B = 4 doubles (line size) AdministraAve flag and tag bits not shown 10
11 A Higher Level Example int sum_array_rows(double a[16][16]) { int i, j; double sum = 0; Ignore the variables sum, i, j (stored in registers) assume: cold (empty) cache, a[0][0] goes here for (i = 0; i < 16; i++) for (j = 0; j < 16; j++) sum += a[i][j]; return sum; int sum_array_cols(double a[16][16]) { int i, j; double sum = 0; for (j = 0; i < 16; i++) for (i = 0; j < 16; j++) sum += a[i][j]; return sum; 32 B = 4 doubles (line size) AdministraAve flag and tag bits not shown 11
12 A Higher Level Example int sum_array_rows(double a[16][16]) { int i, j; double sum = 0; Ignore the variables sum, i, j (stored in registers) assume: cold (empty) cache, a[0][0] goes here a[0][0] a[0][1] a[0][2] a[0][3] for (i = 0; i < 16; i++) for (j = 0; j < 16; j++) sum += a[i][j]; return sum; Miss ra3o =? 32 B = 4 doubles (line size) AdministraAve flag and tag bits not shown 12
13 A Higher Level Example int sum_array_rows(double a[16][16]) { int i, j; double sum = 0; Ignore the variables sum, i, j (stored in registers) assume: cold (empty) cache, a[0][0] goes here a[0][0] a[0][1] a[0][2] a[0][3] for (i = 0; i < 16; i++) for (j = 0; j < 16; j++) sum += a[i][j]; return sum; Miss ra3o = B = 4 doubles (line size) AdministraAve flag and tag bits not shown 13
14 A Higher Level Example int sum_array_rows(double a[16][16]) { int i, j; double sum = 0; for (i = 0; i < 16; i++) for (j = 0; j < 16; j++) sum += a[i][j]; return sum; Ignore the variables sum, i, j (stored in registers) assume: cold (empty) cache, a[0][0] goes here a[0][0] a[0][1] a[0][2] a[0][3] a[0][4] a[0][5] a[0][6] a[0][7] Miss ra3o =? 32 B = 4 doubles (line size) AdministraAve flag and tag bits not shown 14
15 A Higher Level Example int sum_array_rows(double a[16][16]) { int i, j; double sum = 0; for (i = 0; i < 16; i++) for (j = 0; j < 16; j++) sum += a[i][j]; return sum; a[0][0] Ignore the variables sum, i, j (stored in registers) assume: cold (empty) cache, a[0][0] goes here a[0][1] a[0][2] a[0][3] a[0][4] a[0][5] a[0][6] a[0][7] a[0][8] a[0][9] a[0][10] a[0][11] a[0][12] a[0][13] a[0][14] a[0][15] a[1][0] a[1][1] a[1][2] a[1][3] a[1][4] a[1][5] a[1][6] a[1][7] Miss ra3o =? a[1][8] a[1][9] a[1][10] a[1][11] a[1][12] a[1][13] a[1][14] a[1][15] 32 B = 4 doubles (line size) AdministraAve flag and tag bits not shown 15
16 A Higher Level Example int sum_array_rows(double a[16][16]) { int i, j; double sum = 0; for (i = 0; i < 16; i++) for (j = 0; j < 16; j++) sum += a[i][j]; return sum; Ignore the variables sum, i, j (stored in registers) assume: cold (empty) cache, a[0][0] goes here a[0][0] a[0][1] a[0][2] a[0][3] a[0][4] a[0][5] a[0][6] a[0][7] a[0][8] a[0][9] a[0][10] a[0][11] a[0][12] a[0][13] a[0][14] a[0][15] a[1][0] a[1][1] a[1][2] a[1][3] a[1][4] a[1][5] a[1][6] a[1][7] Miss ra3o = 0.25 a[1][8] a[1][9] a[1][10] a[1][11] a[1][12] a[1][13] a[1][14] a[1][15] 32 B = 4 doubles (line size) AdministraAve flag and tag bits not shown 16
17 A Higher Level Example int sum_array_rows(double a[16][16]) { int i, j; double sum = 0; for (i = 0; i < 16; i++) for (j = 0; j < 16; j++) sum += a[i][j]; return sum; Ignore the variables sum, i, j (stored in registers) a[0][0] swapped for a[2][0] a[2][0] a[2][1] a[2][2] a[2][3] a[0][4] a[0][5] a[0][6] a[0][7] a[0][8] a[0][9] a[0][10] a[0][11] a[0][12] a[0][13] a[0][14] a[0][15] a[1][0] a[1][1] a[1][2] a[1][3] a[1][4] a[1][5] a[1][6] a[1][7] Miss ra3o = 0.25 a[1][8] a[1][9] a[1][10] a[1][11] a[1][12] a[1][13] a[1][14] a[1][15] 32 B = 4 doubles (line size) AdministraAve flag and tag bits not shown 17
18 A Higher Level Example Ignore the variables sum, i, j (stored in registers) assume: cold (empty) cache, a[0][0] goes here Miss ra3o =? a[0][0] a[0][1] a[0][2] a[0][3] int sum_array_cols(double a[16][16]) { int i, j; double sum = 0; for (j = 0; i < 16; i++) for (i = 0; j < 16; j++) sum += a[i][j]; return sum; 32 B = 4 doubles (line size) AdministraAve flag and tag bits not shown 18
19 A Higher Level Example Ignore the variables sum, i, j (stored in registers) assume: cold (empty) cache, a[0][0] goes here Miss ra3o = 1.0 a[0][0] a[0][1] a[0][2] a[0][3] int sum_array_cols(double a[16][16]) { int i, j; double sum = 0; for (j = 0; i < 16; i++) for (i = 0; j < 16; j++) sum += a[i][j]; return sum; 32 B = 4 doubles (line size) AdministraAve flag and tag bits not shown 19
20 A Higher Level Example Ignore the variables sum, i, j (stored in registers) assume: cold (empty) cache, a[0][0] goes here Miss ra3o =? a[0][0] a[0][1] a[0][2] a[0][3] a[1][0] a[1][1] a[1][2] a[1][3] int sum_array_cols(double a[16][16]) { int i, j; double sum = 0; for (j = 0; i < 16; i++) for (i = 0; j < 16; j++) sum += a[i][j]; return sum; 32 B = 4 doubles (line size) AdministraAve flag and tag bits not shown 20
21 A Higher Level Example Ignore the variables sum, i, j (stored in registers) assume: cold (empty) cache, a[0][0] goes here Miss ra3o = 1.0 a[0][0] a[0][1] a[0][2] a[0][3] a[1][0] a[1][1] a[1][2] a[1][3] int sum_array_cols(double a[16][16]) { int i, j; double sum = 0; for (j = 0; i < 16; i++) for (i = 0; j < 16; j++) sum += a[i][j]; return sum; 32 B = 4 doubles (line size) AdministraAve flag and tag bits not shown 21
22 A Higher Level Example Ignore the variables sum, i, j (stored in registers) assume: cold (empty) cache, a[0][0] goes here Miss ra3o =? a[0][0] a[0][1] a[0][2] a[0][3] a[1][0] a[1][1] a[1][2] a[1][3] int sum_array_cols(double a[16][16]) { int i, j; double sum = 0; for (j = 0; i < 16; i++) for (i = 0; j < 16; j++) sum += a[i][j]; return sum; a[2][0] a[2][1] a[2][2] a[2][3] a[3][0] a[3][1] a[3][2] a[3][3] a[4][0] a[4][1] a[4][2] a[4][3] a[5][0] a[5][1] a[5][2] a[5][3] a[6][0] a[6][1] a[6][2] a[6][3] a[7][0] a[7][1] a[7][2] a[7][3] 32 B = 4 doubles (line size) AdministraAve flag and tag bits not shown 22
23 A Higher Level Example Ignore the variables sum, i, j (stored in registers) assume: cold (empty) cache, a[0][0] goes here Miss ra3o = 1.0 a[0][0] a[0][1] a[0][2] a[0][3] a[1][0] a[1][1] a[1][2] a[1][3] int sum_array_cols(double a[16][16]) { int i, j; double sum = 0; for (j = 0; i < 16; i++) for (i = 0; j < 16; j++) sum += a[i][j]; return sum; a[2][0] a[2][1] a[2][2] a[2][3] a[3][0] a[3][1] a[3][2] a[3][3] a[4][0] a[4][1] a[4][2] a[4][3] a[5][0] a[5][1] a[5][2] a[5][3] a[6][0] a[6][1] a[6][2] a[6][3] a[7][0] a[7][1] a[7][2] a[7][3] 32 B = 4 doubles (line size) AdministraAve flag and tag bits not shown 23
24 A Higher Level Example Ignore the variables sum, i, j (stored in registers) a[0][0] is swapped with a[8][0] Miss ra3o = 1.0 a[8][0] a[8][1] a[8][2] a[8][3] a[1][0] a[1][1] a[1][2] a[1][3] int sum_array_cols(double a[16][16]) { int i, j; double sum = 0; for (j = 0; i < 16; i++) for (i = 0; j < 16; j++) sum += a[i][j]; return sum; a[2][0] a[2][1] a[2][2] a[2][3] a[3][0] a[3][1] a[3][2] a[3][3] a[4][0] a[4][1] a[4][2] a[4][3] a[5][0] a[5][1] a[5][2] a[5][3] a[6][0] a[6][1] a[6][2] a[6][3] a[7][0] a[7][1] a[7][2] a[7][3] 32 B = 4 doubles (line size) AdministraAve flag and tag bits not shown 24
25 E- way Set Associa3ve Cache (Here: E = 2) E = 2: Two lines per set Assume: cache block size 8 bytes Address of short int: t bits v tag v tag v tag v tag find set v tag v tag v tag v tag
26 E- way Set Associa3ve Cache (Here: E = 2) E = 2: Two lines per set Assume: cache block size 8 bytes compare both Address of short int: t bits valid? + match: yes = hit v tag v tag block offset 26
27 E- way Set Associa3ve Cache (Here: E = 2) E = 2: Two lines per set Assume: cache block size 8 bytes compare both Address of short int: t bits valid? + match: yes = hit v tag v tag short int (2 Bytes) is here block offset On cache miss: One line in set is selected for evic3on and replacement Replacement policies: random, least recently used (LRU), 27
28 2- Way Set Associa3ve Cache Simula3on t=2 s=1 b=1 xx x x M=16 byte addresses B=2 bytes/block, S=2 sets E=2 blocks/set Address trace (reads, one byte per read): 0 [ ], miss 1 [ ], hit 7 [ ], miss 8 [ ], miss 0 [ ] hit Set 0 v Tag Block 01? 00? M[0-1] M[8-9] Set M[6-7] 0 28
29 E- Way Set Associa3ve Cache Simula3on Increased associa3vity decreases miss rate But with diminishing returns Simula3on of a system with 64KB D- cache, 16- word blocks, SPEC way: 10.3% 2- way: 8.6% 4- way: 8.3% 8- way: 8.1% 29
30 What about writes? Mul3ple copies of data exist: L1, L2, Main Memory, Disk What to do on a write- hit? Write- through (write immediately to memory) Write- back (write to memory on eviceon) Dirty bit (keeps track if line is different from memory) What to do on a write- miss? Write- allocate (load into cache, update line in cache) Good if more writes to the locaeon follow No- write- allocate (writes immediately to memory) Typical Write- through + No- write- allocate Write- back + Write- allocate 30
31 Intel Core i7 Cache Hierarchy Processor package Core 0 Regs Core 3 Regs L1 i- cache and d- cache: 32 KB, 8- way, Access: 4 CPU cycles L1 d-cache L1 i-cache L1 d-cache L1 i-cache L2 unified cache: 256 KB, 8- way, Access: 11 cycles L2 unified cache L2 unified cache L3 unified cache: 8 MB, 16- way, Access: cycles L3 unified cache (shared by all cores) Block size: 64 bytes for all caches. Main memory i instruceon d data 31
32 Topics Cache organiza3on and opera3on Performance impact of caches The memory mountain Rearranging loops to improve spaeal locality Using blocking to improve temporal locality 32
33 Cache Performance Miss Rate FracEon of memory references not found in cache Typical numbers (in percentages): 3-10% miss rate for L1 can be quite small (e.g., < 1%) for L2, depending on L2 size, etc. Hit Time Time to deliver a line in the cache to the processor includes Eme to determine whether the line is in the cache Typical numbers: 1-2 clock cycle for L clock cycles for L2 (~10x L1 hit Eme) Miss Penalty AddiEonal Eme required because of a miss typically cycles for main memory (Trend: increasing!) 33
34 Think about those numbers Huge difference between a hit and a miss Could be 100x, if just L1 and main memory Would you believe 99% hits is twice as good as 97%? Consider: cache hit Eme of 1 cycle miss penalty of 100 cycles Average access Eme: 97% hits: 1 cycle * 100 cycles = 4 cycles 99% hits: 1 cycle * 100 cycles = 2 cycles 34
35 Wri3ng Cache Friendly Code Make the common case go fast Focus on the inner loops of the core funceons Minimize the misses in the inner loops Repeated references to variables are good (temporal locality) Stride- 1 reference paperns are good (spaeal locality) Key idea: Locality is quan3fied through understanding of cache memories. 35
36 The Memory Mountain Based on Intel Core i7 Read throughput (MB/s) s1 s3 s5 s7 s9 Element size (x8 byte strides) s11 s13 s15 s32 64M 8M 1M 128K 16K 2K Data size (bytes) 36
37 The Memory Mountain Based on Intel Core i7 Read throughput (MB/s) Slopes of spaaal locality s1 s3 s5 s7 s9 Element size (x8 byte strides) s11 s13 s15 s32 64M 8M 1M 128K 16K 2K Data size (bytes) 37
38 The Memory Mountain Based on Intel Core i7 Read throughput (MB/s) Slopes of spaaal locality s1 s3 s5 s7 s9 Element size (x8 byte strides) s11 s13 Mem s15 L3 s32 64M L1 L2 8M 1M 128K 16K 2K Data size (bytes) Ridges of Temporal locality 38
39 Topics Cache organiza3on and opera3on Performance impact of caches The memory mountain Rearranging loops to improve spaeal locality Using blocking to improve temporal locality 39
40 Miss Rate Analysis for Matrix Mul3ply Assume: Line size = 32B (big enough for four 64- bit words) Matrix dimension (N) is very large Cache size > 1 row Cache size < muleple rows Analysis Method: Look at access papern of inner loop k j j i * k = i A B C 40
41 Matrix Mul3plica3on Example Variables i, j, sum held in registers Descrip3on: MulEply N x N matrices O(N 3 ) total operaeons N reads per source element /* ijk */ for (i=0; i<n; i++) { for (j=0; j<n; j++) { sum = 0.0; for (k=0; k<n; k++) sum += a[i][k] * b[k][j]; c[i][j] = sum; 41
42 Layout of C Arrays in Memory (review) C arrays allocated in row- major order each row in coneguous memory locaeons Stepping through columns in one row: accesses successive elements exploit spaeal locality! Stepping through rows in one column: accesses distant elements no spaeal locality! 42
43 Matrix Mul3plica3on (ijk) /* ijk */ for (i=0; i<n; i++) { for (j=0; j<n; j++) { sum = 0.0; for (k=0; k<n; k++) sum += a[i][k] * b[k][j]; c[i][j] = sum; Misses per inner loop iteraeon: A B C Inner loop: (i,*) (*,j) (i,j) A B C Row- wise Column- wise Fixed 43
44 Matrix Mul3plica3on (kij) /* kij */ for (k=0; k<n; k++) { for (i=0; i<n; i++) { r = a[i][k]; for (j=0; j<n; j++) c[i][j] += r * b[k][j]; Inner loop: (i,k) (k,*) (i,*) A B C Fixed Row- wise Row- wise Misses per inner loop iteraeon: A B C
45 Matrix Mul3plica3on (jki) /* jki */ for (j=0; j<n; j++) { for (k=0; k<n; k++) { r = b[k][j]; for (i=0; i<n; i++) c[i][j] += a[i][k] * r; Inner loop: (*,k) (k,j) (*,j) A B C Column- wise Fixed Column- wise Misses per inner loop iteraeon: A B C
46 Summary of Matrix Mul3plica3on for (i=0; i<n; i++) { for (j=0; j<n; j++) { sum = 0.0; for (k=0; k<n; k++) sum += a[i][k] * b[k][j]; c[i][j] = sum; for (k=0; k<n; k++) { for (i=0; i<n; i++) { r = a[i][k]; for (j=0; j<n; j++) c[i][j] += r * b[k][j]; for (j=0; j<n; j++) { for (k=0; k<n; k++) { r = b[k][j]; for (i=0; i<n; i++) c[i][j] += a[i][k] * r; ijk (& jik): 2 loads, 0 stores misses/iter = 1.25 kij (& ikj): 2 loads, 1 store misses/iter = 0.5 jki (& kji): 2 loads, 1 store misses/iter =
47 Core i7 Matrix Mul3ply Performance 60 jki / kji Cycles per inner loop iteration ijk / jik kij / ikj jki kji ijk jik kij ikj Array size (n) 47
48 Topics Cache organiza3on and opera3on Performance impact of caches The memory mountain Rearranging loops to improve spaeal locality Using blocking to improve temporal locality 48
49 Using blocking to improve temporal locality c = (double *) calloc(sizeof(double), n*n); /* Example: Multiply n x n matrices a and b */ void mmm(double *a, double *b, double *c, int n) { int i, j, k; for (i = 0; i < n; i++) for (j = 0; j < n; j++) for (k = 0; k < n; k++) c[i*n+j] += a[i*n + k]*b[k*n + j]; c = i a * b j 49
50 Cache Miss Analysis Assume: Matrix elements are doubles Cache block = 8 doubles Cache size C << n (much smaller than n) First itera3on: n/8 + n = 9n/8 misses = * n Aterwards in cache: = * 8 wide C A B 50
51 Cache Miss Analysis Assume: Matrix elements are doubles Cache block = 8 doubles Cache size C << n (much smaller than n) Second itera3on: Again in cache: n/8 + n = 9n/8 misses = * n Total misses: 9n/8 * n 2 = (9/8) * n 3 8 wide C A B 51
52 Blocked Matrix Mul3plica3on c = (double *) calloc(sizeof(double), n*n); /* Multiply n x n matrices a and b */ void mmm(double *a, double *b, double *c, int n) { int i, j, k; for (i = 0; i < n; i+=b) for (j = 0; j < n; j+=b) for (k = 0; k < n; k+=b) /* B x B mini matrix multiplications */ for (i1 = i; i1 < i+b; i++) for (j1 = j; j1 < j+b; j++) for (k1 = k; k1 < k+b; k++) c[i1*n+j1] += a[i1*n + k1]*b[k1*n + j1]; c = i1 a * b j1 + c Block size B x B 52
53 Cache Miss Analysis Assume: Cache block = 8 doubles Cache size C << n (much smaller than n) Three blocks fit into cache: 3B 2 < C First (block) itera3on: B 2 /8 misses for each block 2n/B * B 2 /8 = nb/4 (omivng matrix c) = * n/b blocks Aterwards in cache = Block size B x B * 53
54 Cache Miss Analysis Assume: Cache block = 8 doubles Cache size C << n (much smaller than n) Three blocks fit into cache: 3B 2 < C Second (block) itera3on: Same as first iteraeon 2n/B * B 2 /8 = nb/4 = * n/b blocks Total misses: nb/4 * (n/b) 2 = n 3 /(4B) Block size B x B 54
55 Summary No blocking: (9/8) * n 3 Blocking: 1/(4B) * n 3 Suggest largest possible block size B, but limit 3B 2 < C! Reason for drama3c difference: Matrix muleplicaeon has inherent temporal locality: Input data: 3n 2, computaeon 2n 3 Every array elements used O(n) Emes! But program has to be wripen properly 55
56 Concluding Observa3ons Programmer can op3mize for cache performance How data structures are organized How data are accessed Nested loop structure Blocking is a general technique All systems favor cache friendly code Gevng absolute opemum performance is very plaworm specific Cache sizes, line sizes, associaeviees, etc. Can get most of the advantage with generic code Keep working set reasonably small (temporal locality) Use small strides (spaeal locality) 56
Carnegie Mellon. Cache Memories. Computer Architecture. Instructor: Norbert Lu1enberger. based on the book by Randy Bryant and Dave O Hallaron
Cache Memories Computer Architecture Instructor: Norbert Lu1enberger based on the book by Randy Bryant and Dave O Hallaron 1 Today Cache memory organiza7on and opera7on Performance impact of caches The
More informationToday Cache memory organization and operation Performance impact of caches
Cache Memories 1 Today Cache memory organization and operation Performance impact of caches The memory mountain Rearranging loops to improve spatial locality Using blocking to improve temporal locality
More informationToday. Cache Memories. General Cache Concept. General Cache Organization (S, E, B) Cache Memories. Example Memory Hierarchy Smaller, faster,
Today Cache Memories CSci 2021: Machine Architecture and Organization November 7th-9th, 2016 Your instructor: Stephen McCamant Cache memory organization and operation Performance impact of caches The memory
More informationCarnegie Mellon. Cache Memories
Cache Memories Thanks to Randal E. Bryant and David R. O Hallaron from CMU Reading Assignment: Computer Systems: A Programmer s Perspec4ve, Third Edi4on, Chapter 6 1 Today Cache memory organiza7on and
More informationCache memories are small, fast SRAM based memories managed automatically in hardware.
Cache Memories Cache memories are small, fast SRAM based memories managed automatically in hardware. Hold frequently accessed blocks of main memory CPU looks first for data in caches (e.g., L1, L2, and
More informationAgenda Cache memory organization and operation Chapter 6 Performance impact of caches Cache Memories
Agenda Chapter 6 Cache Memories Cache memory organization and operation Performance impact of caches The memory mountain Rearranging loops to improve spatial locality Using blocking to improve temporal
More informationDenison University. Cache Memories. CS-281: Introduction to Computer Systems. Instructor: Thomas C. Bressoud
Cache Memories CS-281: Introduction to Computer Systems Instructor: Thomas C. Bressoud 1 Random-Access Memory (RAM) Key features RAM is traditionally packaged as a chip. Basic storage unit is normally
More informationCache Memories /18-213/15-513: Introduction to Computer Systems 12 th Lecture, October 5, Today s Instructor: Phil Gibbons
Cache Memories 15-213/18-213/15-513: Introduction to Computer Systems 12 th Lecture, October 5, 2017 Today s Instructor: Phil Gibbons 1 Today Cache memory organization and operation Performance impact
More informationMemory Hierarchy. Computer Systems Organization (Spring 2017) CSCI-UA 201, Section 3. Instructor: Joanna Klukowska
Memory Hierarchy Computer Systems Organization (Spring 2017) CSCI-UA 201, Section 3 Instructor: Joanna Klukowska Slides adapted from Randal E. Bryant and David R. O Hallaron (CMU) Mohamed Zahran (NYU)
More informationMemory Hierarchy. Cache Memory Organization and Access. General Cache Concept. Example Memory Hierarchy Smaller, faster,
Memory Hierarchy Computer Systems Organization (Spring 2017) CSCI-UA 201, Section 3 Cache Memory Organization and Access Instructor: Joanna Klukowska Slides adapted from Randal E. Bryant and David R. O
More informationCache memories are small, fast SRAM-based memories managed automatically in hardware. Hold frequently accessed blocks of main memory
Cache Memories Cache memories are small, fast SRAM-based memories managed automatically in hardware. Hold frequently accessed blocks of main memory CPU looks first for data in caches (e.g., L1, L2, and
More informationCS 33. Caches. CS33 Intro to Computer Systems XVIII 1 Copyright 2017 Thomas W. Doeppner. All rights reserved.
CS 33 Caches CS33 Intro to Computer Systems XVIII 1 Copyright 2017 Thomas W. Doeppner. All rights reserved. Cache Performance Metrics Miss rate fraction of memory references not found in cache (misses
More informationCache Memories. Topics. Next time. Generic cache memory organization Direct mapped caches Set associative caches Impact of caches on performance
Cache Memories Topics Generic cache memory organization Direct mapped caches Set associative caches Impact of caches on performance Next time Dynamic memory allocation and memory bugs Fabián E. Bustamante,
More informationCache Memories : Introduc on to Computer Systems 12 th Lecture, October 6th, Instructor: Randy Bryant.
Cache Memories 15-213: Introduc on to Computer Systems 12 th Lecture, October 6th, 2016 Instructor: Randy Bryant 1 Today Cache memory organiza on and opera on Performance impact of caches The memory mountain
More informationMemory Hierarchy. Jin-Soo Kim Computer Systems Laboratory Sungkyunkwan University
Memory Hierarchy Jin-Soo Kim (jinsookim@skku.edu) Computer Systems Laboratory Sungkyunkwan University http://csl.skku.edu Time (ns) The CPU-Memory Gap The gap widens between DRAM, disk, and CPU speeds
More informationGiving credit where credit is due
CSCE 23J Computer Organization Cache Memories Dr. Steve Goddard goddard@cse.unl.edu http://cse.unl.edu/~goddard/courses/csce23j Giving credit where credit is due Most of slides for this lecture are based
More informationCache Memories October 8, 2007
15-213 Topics Cache Memories October 8, 27 Generic cache memory organization Direct mapped caches Set associative caches Impact of caches on performance The memory mountain class12.ppt Cache Memories Cache
More information211: Computer Architecture Summer 2016
211: Computer Architecture Summer 2016 Liu Liu Topic: Assembly Programming Storage - Assembly Programming: Recap - Call-chain - Factorial - Storage: - RAM - Caching - Direct - Mapping Rutgers University
More informationCISC 360. Cache Memories Nov 25, 2008
CISC 36 Topics Cache Memories Nov 25, 28 Generic cache memory organization Direct mapped caches Set associative caches Impact of caches on performance Cache Memories Cache memories are small, fast SRAM-based
More informationCache Memories. EL2010 Organisasi dan Arsitektur Sistem Komputer Sekolah Teknik Elektro dan Informatika ITB 2010
Cache Memories EL21 Organisasi dan Arsitektur Sistem Komputer Sekolah Teknik Elektro dan Informatika ITB 21 Topics Generic cache memory organization Direct mapped caches Set associative caches Impact of
More informationCache Memories. From Bryant and O Hallaron, Computer Systems. A Programmer s Perspective. Chapter 6.
Cache Memories From Bryant and O Hallaron, Computer Systems. A Programmer s Perspective. Chapter 6. Today Cache memory organization and operation Performance impact of caches The memory mountain Rearranging
More informationLast class. Caches. Direct mapped
Memory Hierarchy II Last class Caches Direct mapped E=1 (One cache line per set) Each main memory address can be placed in exactly one place in the cache Conflict misses if two addresses map to same place
More informationProblem: Processor Memory BoJleneck
Today Memory hierarchy, caches, locality Cache organiza:on Program op:miza:ons that consider caches CSE351 Inaugural Edi:on Spring 2010 1 Problem: Processor Memory BoJleneck Processor performance doubled
More informationSystems Programming and Computer Architecture ( ) Timothy Roscoe
Systems Group Department of Computer Science ETH Zürich Systems Programming and Computer Architecture (252-0061-00) Timothy Roscoe Herbstsemester 2016 AS 2016 Caches 1 16: Caches Computer Architecture
More informationCache Memories. Cache Memories Oct. 10, Inserting an L1 Cache Between the CPU and Main Memory. General Org of a Cache Memory
5-23 The course that gies CMU its Zip! Topics Cache Memories Oct., 22! Generic cache memory organization! Direct mapped caches! Set associatie caches! Impact of caches on performance Cache Memories Cache
More informationLecture 15: Caches and Optimization Computer Architecture and Systems Programming ( )
Systems Group Department of Computer Science ETH Zürich Lecture 15: Caches and Optimization Computer Architecture and Systems Programming (252-0061-00) Timothy Roscoe Herbstsemester 2012 Last time Program
More informationCache memories The course that gives CMU its Zip! Cache Memories Oct 11, General organization of a cache memory
5-23 The course that gies CMU its Zip! Cache Memories Oct, 2 Topics Generic cache memory organization Direct mapped caches Set associatie caches Impact of caches on performance Cache memories Cache memories
More informationν Hold frequently accessed blocks of main memory 2 CISC 360, Fa09 Cache is an array of sets. Each set contains one or more lines.
Topics CISC 36 Cache Memories Dec, 29 ν Generic cache memory organization ν Direct mapped caches ν Set associatie caches ν Impact of caches on performance Cache Memories Cache memories are small, fast
More informationSystems I. Optimizing for the Memory Hierarchy. Topics Impact of caches on performance Memory hierarchy considerations
Systems I Optimizing for the Memory Hierarchy Topics Impact of caches on performance Memory hierarchy considerations Cache Performance Metrics Miss Rate Fraction of memory references not found in cache
More informationExample. How are these parameters decided?
Example How are these parameters decided? Comparing cache organizations Like many architectural features, caches are evaluated experimentally. As always, performance depends on the actual instruction mix,
More informationComputer Systems CSE 410 Autumn Memory Organiza:on and Caches
Computer Systems CSE 410 Autumn 2013 10 Memory Organiza:on and Caches 06 April 2012 Memory Organiza?on 1 Roadmap C: car *c = malloc(sizeof(car)); c->miles = 100; c->gals = 17; float mpg = get_mpg(c); free(c);
More informationHigh-Performance Parallel Computing
High-Performance Parallel Computing P. (Saday) Sadayappan Rupesh Nasre Course Overview Emphasis on algorithm development and programming issues for high performance No assumed background in computer architecture;
More informationThe course that gives CMU its Zip! Memory System Performance. March 22, 2001
15-213 The course that gives CMU its Zip! Memory System Performance March 22, 2001 Topics Impact of cache parameters Impact of memory reference patterns memory mountain range matrix multiply Basic Cache
More informationTypes of Cache Misses. The Hardware/So<ware Interface CSE351 Winter Cache Read. General Cache OrganizaJon (S, E, B) Memory and Caches II
Types of Cache Misses The Hardware/So
More informationMemory Hierarchy. Instructor: Adam C. Champion, Ph.D. CSE 2431: Introduction to Operating Systems Reading: Chap. 6, [CSAPP]
Memory Hierarchy Instructor: Adam C. Champion, Ph.D. CSE 2431: Introduction to Operating Systems Reading: Chap. 6, [CSAPP] Motivation Up to this point we have relied on a simple model of a computer system
More informationMemory Hierarchy. Announcement. Computer system model. Reference
Announcement Memory Hierarchy Computer Organization and Assembly Languages Yung-Yu Chuang 26//5 Grade for hw#4 is online Please DO submit homework if you haen t Please sign up a demo time on /6 or /7 at
More informationCache Memories. Lecture, Oct. 30, Bryant and O Hallaron, Computer Systems: A Programmer s Perspective, Third Edition
Cache Memories Lecture, Oct. 30, 2018 1 General Cache Concept Cache 84 9 14 10 3 Smaller, faster, more expensive memory caches a subset of the blocks 10 4 Data is copied in block-sized transfer units Memory
More informationRoadmap. Java: Assembly language: OS: Machine code: Computer system:
Roadmap C: car *c = malloc(sizeof(car)); c->miles = 100; c->gals = 17; float mpg = get_mpg(c); free(c); Assembly language: Machine code: get_mpg: pushq movq... popq ret %rbp %rsp, %rbp %rbp 0111010000011000
More informationCSCI-UA.0201 Computer Systems Organization Memory Hierarchy
CSCI-UA.0201 Computer Systems Organization Memory Hierarchy Mohamed Zahran (aka Z) mzahran@cs.nyu.edu http://www.mzahran.com Programmer s Wish List Memory Private Infinitely large Infinitely fast Non-volatile
More informationThe Memory Hierarchy. Fall Instructors: Aykut & Erkut Erdem
The Memory Hierarchy Fall 2012 Instructors: Aykut & Erkut Erdem Acknowledgement: The course slides are adapted from the slides prepared by R.E. Bryant, D.R. O Hallaron, G. Kesden and Markus Püschel of
More informationCS 33. Architecture and Optimization (3) CS33 Intro to Computer Systems XVI 1 Copyright 2018 Thomas W. Doeppner. All rights reserved.
CS 33 Architecture and Optimization (3) CS33 Intro to Computer Systems XVI 1 Copyright 2018 Thomas W. Doeppner. All rights reserved. Hyper Threading Instruction Control Instruction Control Retirement Unit
More informationLecture 12. Memory Design & Caches, part 2. Christos Kozyrakis Stanford University
Lecture 12 Memory Design & Caches, part 2 Christos Kozyrakis Stanford University http://eeclass.stanford.edu/ee108b 1 Announcements HW3 is due today PA2 is available on-line today Part 1 is due on 2/27
More informationCaches Spring 2016 May 4: Caches 1
May 4: Caches 1 Roadmap C: car *c = malloc(sizeof(car)); c->miles = 100; c->gals = 17; float mpg = get_mpg(c); free(c); Assembly language: Machine code: Computer system: get_mpg: pushq movq... popq ret
More informationMemory hierarchies: caches and their impact on the running time
Memory hierarchies: caches and their impact on the running time Irene Finocchi Dept. of Computer and Science Sapienza University of Rome A happy coincidence A fundamental property of hardware Different
More informationRoadmap. Java: Assembly language: OS: Machine code: Computer system:
Roadmap C: car *c = malloc(sizeof(car)); c->miles = 100; c->gals = 17; float mpg = get_mpg(c); free(c); Assembly language: Machine code: get_mpg: pushq movq... popq ret %rbp %rsp, %rbp %rbp 0111010000011000
More informationCache Memory and Performance
Cache Memory and Performance Cache Organization 1 Many of the following slides are taken with permission from Complete Powerpoint Lecture Notes for Computer Systems: A Programmer's Perspective (CS:APP)
More informationCSCI 402: Computer Architectures. Performance of Multilevel Cache
CSCI 402: Computer Architectures Memory Hierarchy (5) Fengguang Song Department of Computer & Information Science IUPUI Performance of Multilevel Cache Main Memory CPU L1 cache L2 cache Given CPU base
More informationCache Memory and Performance
Cache Memory and Performance Cache Performance 1 Many of the following slides are taken with permission from Complete Powerpoint Lecture Notes for Computer Systems: A Programmer's Perspective (CS:APP)
More informationCaches III. CSE 351 Spring Instructor: Ruth Anderson
Caches III CSE 351 Spring 2017 Instructor: Ruth Anderson Teaching Assistants: Dylan Johnson Kevin Bi Linxing Preston Jiang Cody Ohlsen Yufang Sun Joshua Curtis Administrivia Office Hours Changes check
More informationCarnegie Mellon. Cache Lab. Recitation 7: Oct 11 th, 2016
1 Cache Lab Recitation 7: Oct 11 th, 2016 2 Outline Memory organization Caching Different types of locality Cache organization Cache lab Part (a) Building Cache Simulator Part (b) Efficient Matrix Transpose
More informationCS 240 Stage 3 Abstractions for Practical Systems
CS 240 Stage 3 Abstractions for Practical Systems Caching and the memory hierarchy Operating systems and the process model Virtual memory Dynamic memory allocation Victory lap Memory Hierarchy: Cache Memory
More informationCS241 Computer Organization Spring Principle of Locality
CS241 Computer Organization Spring 2015 Principle of Locality 4-21 2015 Outline! Optimization! Memory Hierarchy Locality temporal spatial Cache Readings: CSAPP2: Chapter 5, sections 5.1-5.6; 5.13 CSAPP2:
More informationKathryn Chan, Kevin Bi, Ryan Wong, Waylon Huang, Xinyu Sui
Caches III CSE 410 Winter 2017 Instructor: Justin Hsia Teaching Assistants: Kathryn Chan, Kevin Bi, Ryan Wong, Waylon Huang, Xinyu Sui Please stop charging your phone in public ports "Just by plugging
More informationLecture 17: Memory Hierarchy and Cache Coherence Concurrent and Mul7core Programming
Lecture 17: Memory Hierarchy and Cache Coherence Concurrent and Mul7core Programming Department of Computer Science and Engineering Yonghong Yan yan@oakland.edu www.secs.oakland.edu/~yan 1 Parallelism
More informationComputer Organization: A Programmer's Perspective
Computer Architecture and The Memory Hierarchy Oren Kapah orenkapah.ac@gmail.com Typical Computer Architecture CPU chip PC (Program Counter) register file AL U Main Components CPU Main Memory Input/Output
More informationCISC 360. Cache Memories Exercises Dec 3, 2009
Topics ν CISC 36 Cache Memories Exercises Dec 3, 29 Review of cache memory mapping Cache Memories Cache memories are small, fast SRAM-based memories managed automatically in hardware. ν Hold frequently
More information211: Computer Architecture Summer 2016
211: Computer Architecture Summer 2016 Liu Liu Topic: Storage Project3 Digital Logic - Storage: Recap - Direct - Mapping - Fully Associated - 2-way Associated - Cache Friendly Code Rutgers University Liu
More informationCaches III. CSE 351 Winter Instructor: Mark Wyse
Caches III CSE 351 Winter 2018 Instructor: Mark Wyse Teaching Assistants: Kevin Bi Parker DeWilde Emily Furst Sarah House Waylon Huang Vinny Palaniappan https://what-if.xkcd.com/111/ Administrative Midterm
More informationCache Performance II 1
Cache Performance II 1 cache operation (associative) 111001 index offset valid tag valid tag data data 1 10 1 00 00 11 AA BB tag 1 11 1 01 B4 B5 33 44 = data (B5) AND = AND OR is hit? (1) 2 cache operation
More informationCS 261 Fall Caching. Mike Lam, Professor. (get it??)
CS 261 Fall 2017 Mike Lam, Professor Caching (get it??) Topics Caching Cache policies and implementations Performance impact General strategies Caching A cache is a small, fast memory that acts as a buffer
More informationHow to Write Fast Numerical Code
How to Write Fast Numerical Code Lecture: Memory hierarchy, locality, caches Instructor: Markus Püschel TA: Alen Stojanov, Georg Ofenbeck, Gagandeep Singh Organization Temporal and spatial locality Memory
More informationProblem: Processor- Memory Bo<leneck
Storage Hierarchy Instructor: Sanjeev Se(a 1 Problem: Processor- Bo
More informationCaches Concepts Review
Caches Concepts Review What is a block address? Why not bring just what is needed by the processor? What is a set associative cache? Write-through? Write-back? Then we ll see: Block allocation policy on
More informationCS429: Computer Organization and Architecture
CS429: Computer Organization and Architecture Warren Hunt, Jr. and Bill Young Department of Computer Sciences University of Texas at Austin Last updated: August 26, 2014 at 08:54 CS429 Slideset 20: 1 Cache
More informationCS429: Computer Organization and Architecture
CS429: Computer Organization and Architecture Dr. Bill Young Department of Computer Sciences University of Texas at Austin Last updated: April 5, 2018 at 13:55 CS429 Slideset 19: 1 Cache Vocabulary Much
More informationComputer Organization - Overview
Computer Organization - Overview Hyunyoung Lee CSCE 312 1 Course Overview Topics: Theme Five great realities of computer systems Computer system overview Summary NOTE: Most slides are from the textbook
More informationCS24: INTRODUCTION TO COMPUTING SYSTEMS. Spring 2017 Lecture 15
CS24: INTRODUCTION TO COMPUTING SYSTEMS Spring 2017 Lecture 15 LAST TIME: CACHE ORGANIZATION Caches have several important parameters B = 2 b bytes to store the block in each cache line S = 2 s cache sets
More informationCache Lab Implementation and Blocking
Cache Lab Implementation and Blocking Lou Clark February 24 th, 2014 1 Welcome to the World of Pointers! 2 Class Schedule Cache Lab Due Thursday. Start soon if you haven t yet! Exam Soon! Start doing practice
More informationIntroduction to Computer Systems
CSCE 230J Computer Organization Introduction to Computer Systems Dr. Steve Goddard goddard@cse.unl.edu http://cse.unl.edu/~goddard/courses/csce230j Giving credit where credit is due Most of slides for
More informationIntroduction to Computer Systems
CSCE 230J Computer Organization Introduction to Computer Systems Dr. Steve Goddard goddard@cse.unl.edu Giving credit where credit is due Most of slides for this lecture are based on slides created by Drs.
More informationHow to Write Fast Numerical Code
How to Write Fast Numerical Code Lecture: Memory hierarchy, locality, caches Instructor: Markus Püschel TA: Daniele Spampinato & Alen Stojanov Left alignment Attractive font (sans serif, avoid Arial) Calibri,
More informationF28HS Hardware-Software Interface: Systems Programming
F28HS Hardware-Software Interface: Systems Programming Hans-Wolfgang Loidl School of Mathematical and Computer Sciences, Heriot-Watt University, Edinburgh Semester 2 2016/17 0 No proprietary software has
More informationCS24: INTRODUCTION TO COMPUTING SYSTEMS. Spring 2015 Lecture 15
CS24: INTRODUCTION TO COMPUTING SYSTEMS Spring 2015 Lecture 15 LAST TIME! Discussed concepts of locality and stride Spatial locality: programs tend to access values near values they have already accessed
More informationAdvanced Memory Organizations
CSE 3421: Introduction to Computer Architecture Advanced Memory Organizations Study: 5.1, 5.2, 5.3, 5.4 (only parts) Gojko Babić 03-29-2018 1 Growth in Performance of DRAM & CPU Huge mismatch between CPU
More informationCS 61C: Great Ideas in Computer Architecture (Machine Structures) Caches Part 2
CS 61C: Great Ideas in Computer Architecture (Machine Structures) Caches Part 2 Instructors: John Wawrzynek & Vladimir Stojanovic http://insteecsberkeleyedu/~cs61c/ Typical Memory Hierarchy Datapath On-Chip
More informationAgenda. Cache-Memory Consistency? (1/2) 7/14/2011. New-School Machine Structures (It s a bit more complicated!)
7/4/ CS 6C: Great Ideas in Computer Architecture (Machine Structures) Caches II Instructor: Michael Greenbaum New-School Machine Structures (It s a bit more complicated!) Parallel Requests Assigned to
More informationComputer Architecture and System Software Lecture 09: Memory Hierarchy. Instructor: Rob Bergen Applied Computer Science University of Winnipeg
Computer Architecture and System Software Lecture 09: Memory Hierarchy Instructor: Rob Bergen Applied Computer Science University of Winnipeg Announcements Midterm returned + solutions in class today SSD
More informationCS 61C: Great Ideas in Computer Architecture Direct- Mapped Caches. Increasing distance from processor, decreasing speed.
CS 6C: Great Ideas in Computer Architecture Direct- Mapped s 9/27/2 Instructors: Krste Asanovic, Randy H Katz hdp://insteecsberkeleyedu/~cs6c/fa2 Fall 2 - - Lecture #4 New- School Machine Structures (It
More informationSE-292 High Performance Computing. Memory Hierarchy. R. Govindarajan Memory Hierarchy
SE-292 High Performance Computing Memory Hierarchy R. Govindarajan govind@serc Memory Hierarchy 2 1 Memory Organization Memory hierarchy CPU registers few in number (typically 16/32/128) subcycle access
More informationCS356: Discussion #9 Memory Hierarchy and Caches. Marco Paolieri Illustrations from CS:APP3e textbook
CS356: Discussion #9 Memory Hierarchy and Caches Marco Paolieri (paolieri@usc.edu) Illustrations from CS:APP3e textbook The Memory Hierarchy So far... We modeled the memory system as an abstract array
More informationLocality. CS429: Computer Organization and Architecture. Locality Example 2. Locality Example
Locality CS429: Computer Organization and Architecture Dr Bill Young Department of Computer Sciences University of Texas at Austin Principle of Locality: Programs tend to reuse data and instructions near
More informationHow to Write Fast Numerical Code Spring 2011 Lecture 7. Instructor: Markus Püschel TA: Georg Ofenbeck
How to Write Fast Numerical Code Spring 2011 Lecture 7 Instructor: Markus Püschel TA: Georg Ofenbeck Last Time: Locality Temporal and Spatial memory memory Last Time: Reuse FFT: O(log(n)) reuse MMM: O(n)
More information5. Memory Hierarchy Computer Architecture COMP SCI 2GA3 / SFWR ENG 2GA3. Emil Sekerinski, McMaster University, Fall Term 2015/16
5. Memory Hierarchy Computer Architecture COMP SCI 2GA3 / SFWR ENG 2GA3 Emil Sekerinski, McMaster University, Fall Term 2015/16 Movie Rental Store You have a huge warehouse with every movie ever made.
More informationEE108B Lecture 13. Caches Wrap Up Processes, Interrupts, and Exceptions. Christos Kozyrakis Stanford University
EE108B Lecture 13 Caches Wrap Up Processes, Interrupts, and Exceptions Christos Kozyrakis Stanford University http://eeclass.stanford.edu/ee108b 1 Announcements Lab3 and PA2.1 are due ton 2/27 Don t forget
More informationPrinceton University. Computer Science 217: Introduction to Programming Systems. The Memory/Storage Hierarchy and Virtual Memory
Princeton University Computer Science 27: Introduction to Programming Systems The Memory/Storage Hierarchy and Virtual Memory Goals of this Lecture Help you learn about: Locality and caching The memory
More informationCSF Cache Introduction. [Adapted from Computer Organization and Design, Patterson & Hennessy, 2005]
CSF Cache Introduction [Adapted from Computer Organization and Design, Patterson & Hennessy, 2005] Review: The Memory Hierarchy Take advantage of the principle of locality to present the user with as much
More informationChapter 5A. Large and Fast: Exploiting Memory Hierarchy
Chapter 5A Large and Fast: Exploiting Memory Hierarchy Memory Technology Static RAM (SRAM) Fast, expensive Dynamic RAM (DRAM) In between Magnetic disk Slow, inexpensive Ideal memory Access time of SRAM
More informationBasic Memory Hierarchy Principles. Appendix C (Not all will be covered by the lecture; studying the textbook is recommended!)
Basic Memory Hierarchy Principles Appendix C (Not all will be covered by the lecture; studying the textbook is recommended!) Cache memory idea Use a small faster memory, a cache memory, to store recently
More informationLECTURE 4: LARGE AND FAST: EXPLOITING MEMORY HIERARCHY
LECTURE 4: LARGE AND FAST: EXPLOITING MEMORY HIERARCHY Abridged version of Patterson & Hennessy (2013):Ch.5 Principle of Locality Programs access a small proportion of their address space at any time Temporal
More informationwrite-through v. write-back write-through v. write-back write-through v. write-back option 1: write-through write 10 to 0xABCD CPU RAM Cache ABCD: FF
write-through v. write-back option 1: write-through 1 write 10 to 0xABCD CPU Cache ABCD: FF RAM 11CD: 42 ABCD: FF 1 2 write-through v. write-back option 1: write-through write-through v. write-back option
More informationCS 61C: Great Ideas in Computer Architecture (Machine Structures) Caches Part 2
CS 61C: Great Ideas in Computer Architecture (Machine Structures) Caches Part 2 Instructors: Krste Asanović & Randy H. Katz http://inst.eecs.berkeley.edu/~cs61c/ 10/16/17 Fall 2017 - Lecture #15 1 Outline
More information10/16/17. Outline. Outline. Typical Memory Hierarchy. Adding Cache to Computer. Key Cache Concepts
// CS C: Great Ideas in Computer Architecture (Machine Structures) s Part Instructors: Krste Asanović & Randy H Katz http://insteecsberkeleyedu/~csc/ Organization and Principles Write Back vs Write Through
More informationChapter 6 Caches. Computer System. Alpha Chip Photo. Topics. Memory Hierarchy Locality of Reference SRAM Caches Direct Mapped Associative
Chapter 6 s Topics Memory Hierarchy Locality of Reference SRAM s Direct Mapped Associative Computer System Processor interrupt On-chip cache s s Memory-I/O bus bus Net cache Row cache Disk cache Memory
More informationCS3350B Computer Architecture
CS3350B Computer Architecture Winter 2015 Lecture 3.1: Memory Hierarchy: What and Why? Marc Moreno Maza www.csd.uwo.ca/courses/cs3350b [Adapted from lectures on Computer Organization and Design, Patterson
More informationAnnouncements. EE108B Lecture 13. Caches Wrap Up Processes, Interrupts, and Exceptions. Measuring Performance. Memory Performance
Announcements EE18B Lecture 13 Caches Wrap Up Processes, Interrupts, and Exceptions Lab3 and PA2.1 are due ton 2/27 Don t forget to study the textbook Don t forget the review sessions Christos Kozyrakis
More informationCS 61C: Great Ideas in Computer Architecture (Machine Structures) Caches Part 2
CS 61C: Great Ideas in Computer Architecture (Machine Structures) Caches Part 2 Instructors: Bernhard Boser & Randy H Katz http://insteecsberkeleyedu/~cs61c/ 10/18/16 Fall 2016 - Lecture #15 1 Outline
More informationGeneral Cache Mechanics. Memory Hierarchy: Cache. Cache Hit. Cache Miss CPU. Cache. Memory CPU CPU. Cache. Cache. Memory. Memory
Hierarchy: hierarchy basics Locality organization -aware programming General Mechanics CP 8 9 4 Data is moved in units 4 5 6 7 8 9 4 5 Block: unit of data in cache and memory. (a.k.a. line) Smaller, faster,
More informationQuestion 13 1: (Solution, p 4) Describe the inputs and outputs of a (1-way) demultiplexer, and how they relate.
Questions 1 Question 13 1: (Solution, p ) Describe the inputs and outputs of a (1-way) demultiplexer, and how they relate. Question 13 : (Solution, p ) In implementing HYMN s control unit, the fetch cycle
More informationStorage Management 1
Storage Management Goals of this Lecture Help you learn about: Locality and caching Typical storage hierarchy Virtual memory How the hardware and OS give applications the illusion of a large, contiguous,
More information