CS222: Processor Design

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1 CS222: Processor Design Dr. A. Sahu Dept of Comp. Sc. & Engg. Indian Institute of Technology Guwahati

2 Processor Design building blocks Outline A simple implementation: Single Cycle Data pathandcontrol and Performance considerations Multi cycle l design Data path and control Micro programmed control Exception handling 2

3 Simple Processor Design MIPS subset for implementation Design overview Division iii into data path and control Building blocks combinational and sequential Clock and timings Components required for MIPS subset

4 MIPS subset for implementation Arithmetic logic instructions add, sub, and, or, slt Memory reference instructions lw, sw Control lflow instructions ti beq, j Incremental changes in the design to include other instructions will be discussed later

5 Generic Implementation Use the program counter (PC) to supply instruction address Get the instruction from memory Read registers Use the instruction to decide exactly what to do

6 Design overview Instruction Memory Data PC Instruction Address Reg# Register Reg# FILE Reg# ALU Address Data Memory Data 6

7 Division into Data path and Control DATA PATH control signals CONTROLLER status signals

8 Building block types Two types of functional units: Elements that operate on data values (combinational) Output is function of current input No memory Elements that contain state (sequential) Output is function of current and previous inputs State = memory

9 Combinational circuit examples Gates: and, or, nand, nor, xor, inverter Multiplexer Decoder Adder, subtractor, comparator ALU Array multipliers

10 Sequential circuit examples Flip flops Counters Registers Register files Memories

11 Clocked vs. unclocked circuit Clocked state element State changes only with clock edge Unclocked state element State changes can occur with changes in other inputs falling edge cycle time rising edge

12 Unclocked state elements R Q C Q S _ Q D _ Q D C Q

13 Clocked State Elements D D C D latch Q D C D latch Q _ Q Q _ Q C D C Q

14 Clock and timings D Set-up time Hold time C State Element Combinational Logic State Element 2 Clock Cycle

15 Components for MIPS subset Register Adder ALU Multiplexer Register file Program memory Data memory Bit manipulation components

16 MIPS Components Register PC clock

17 MIPS Components Adder PC PC offset

18 MIPS Components ALU operation a a=b overflow 32 result b ALU 32 32

19 MIPS components Multiplexers PC+4 32 mux PC+4+offset select

20 MIPS Components register file Register Number 5 5 Read Reg Read Reg 2 Read Data 32 5 Registers Wit Write Reg Data Data 32 Write data Read Data 2 32 Reg Write

21 MIPS Components: Program memory Instruction Address Instruction Memory Instruction

22 MIPS Components Data memory Mem Write Address Write data Data Memory Mem Read Read data

23 MIPS Components Bit manipulation i circuits i 6 32 sign xtend MSB LSB shift MSB LSB

24 A Processor Design Method Build the datapath step by step as follows Start with R class instructions Include other instructions one by one Identify control signals Interconnect datapath and controller

25 MIPS subset for implementation Arithmetic logic instructions add, sub, and, or, slt Memory reference instructions lw, sw Control flow instructions beq, j

26 Division into data path and control DATA PATH control signals CONTROLLER status signals

27 Datapath for add,sub,and,or,slt fetch instruction address the register file pass operands to ALU pass result to register file increment PC Format: add $t, $s, $s2 actions required op rs rt rd shamt funct

28 Fetching instruction PC ad IM ins

29 Addressing RF PC ad IM ins ins[25 2] 2] ins[2 6] rad rad2 wad wd RF rd rd2

30 Passing operands to ALU PC ad IM ins ins[25 2] 2] ins[2 6] rad rad2 wad wd RF rd rd2 ALU

31 Passing the result to RF PC ad IM ins ins[25 2] 2] ins[2 6] ins[5 ] rad rad2 wad wd RF rd rd2 ALU

32 Incrementing PC 4 + PC ad IM ins ins[25 2] 2] ins[2 6] ins[5 ] rad rad2 wad wd RF rd rd2 ALU

33 Load and Store instructions format : I Example: lw $t, 32($s2) 2) op rs rt 6 bit number

34 Adding sw instruction 4 + PC ad IM ins ins[25 2] 2] ins[2 6] ins[5 ] ins[5 ] rad rad2 wad wd 6 RF rd rd2 sx ALU ad rd DM wd

35 Adding lw instruction 4 + PC ad IM ins ins[25 2] 2] ins[2 6] ins[5 ] ins[5 ] rad rad2 wad wd 6 RF rd rd2 sx ALU ad rd DM wd

36 Format of beq instruction beq I format op rs rt 6 bit number

37 Adding beq instruction 4 + s2 + PC ad IM ins ins[25 2] 2] ins[2 6] ins[5 ] ins[5 ] rad rad2 wad wd 6 RF rd rd2 sx ALU ad rd DM wd

38 MIPS components bit manipulation circuits 6 sign 32 xtend MSB LSB shift MSB LSB

39 Format of jump instruction j J format op 26 bit number

40 Adding j instruction s2 s2 ins[25 ] ja[3 ] 28 g j + + s2 s2 4 PC+4[3 28] ins[25 2] PC IM ad ins RF rad rad2 wad wd rd rd2 DM ad rd ALU ins[25 2] ins[2 6] ins[5 ] wd DM wd sx sx ins[5 ] 6

41 Control signals s2 s2 jmp ins[25 ] ja[3 ] 28 g + + s2 s2 4 PC+4[3 28] Psrc RW ins[25 2] PC IM ad ins RF rad rad2 wad wd rd rd2 DM ad rd ALU Z ins[25 2] ins[2 6] ins[5 ] MW Asrc M2R wd DM wd sx sx Rdst MR ins[5 ] 6 op 3

42 Datapath + Control s2 s2 jmp ins[25 ] ja[3 ] s2 s2 4 Psrc brn ol ol PC+4[3 28] RW contro ins[3 26] ins[25 2] PC IM ad ins RF rad rad2 wad wd rd rd2 DM ad rd ALU Z MW M2R Asrc ins[25 2] ins[2 6] ins[5 ] wd DM wd sx sx Rdst MR op ins[5 ] Actrl Actrl ins[5 ] ins[5 ] opc 2

43 Summary Processor designed for {add, sub, and, or, slt, lw, sw, beq, j} Step by step approach Started with {add, sub, and, or, slt} Added {sw, lw}, then added {beq, j} Identified control signals and connected to a g controller (black box).

44 44

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