CMSC 313 COMPUTER ORGANIZATION & ASSEMBLY LANGUAGE PROGRAMMING LECTURE 02, FALL 2012


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1 CMSC 33 COMPUTER ORGANIZATION & ASSEMBLY LANGUAGE PROGRAMMING LECTURE 2, FALL 22
2 TOPICS TODAY Bits of Memory Data formats for negative numbers Modulo arithmetic & two s complement Floating point formats (briefly) Characters & strings
3 BITS OF MEMORY
4 Random Access Memory (RAM) A single byte of memory holds 8 binary digits (bits). Each byte of memory has its own address. A 32bit CPU can address 4 gigabytes of memory, but a machine may have much less (e.g., 256MB). For now, think of RAM as one big array of bytes. The data stored in a byte of memory is not typed. The assembly language programmer must remember whether the data stored in a byte is a character, an unsigned number, a signed number, part of a multibyte number,... UMBC, CMSC33, Richard Chang
5 45 Chapter 4: The Instruction Set Architecture Common Sizes for Data Types A byte is composed of 8 bits. Two nibbles make up a byte. Halfwords, words, doublewords, and quadwords are composed of bytes as shown below: Bit Nibble Byte 6bit word (halfword) 32bit word 64bit word (double) 28bit word (quad) Principles of Computer Architecture by M. Murdocca and V. Heuring 999 M. Murdocca and V. Heuring
6 46 Chapter 4: The Instruction Set Architecture BigEndian and LittleEndian Formats In a byteaddressable machine, the smallest datum that can be referenced in memory is the byte. Multibyte words are stored as a sequence of bytes, in which the address of the multibyte word is the same as the byte of the word that has the lowest address. When multibyte words are used, two choices for the order in which the bytes are stored in memory are: most significant byte at lowest address, referred to as bigendian, or least significant byte stored at lowest address, referred to as littleendian. Byte 3 BigEndian 3 LittleEndian MSB LSB MSB LSB x x+ x+2 x+3 x+3 x+2 x+ x Word address is x for both bigendian and littleendian formats. Principles of Computer Architecture by M. Murdocca and V. Heuring 999 M. Murdocca and V. Heuring
7 NEGATIVE NUMBERS
8 2 Chapter 2: Data Representation Signed Fixed Point Numbers For an 8bit number, there are 2 8 = 256 possible bit patterns. These bit patterns can represent negative numbers if we choose to assign bit patterns to numbers in this way. We can assign half of the bit patterns to negative numbers and half of the bit patterns to positive numbers. Four signed representations we will cover are: Signed Magnitude One s Complement Two s Complement Excess (Biased) Principles of Computer Architecture by M. Murdocca and V. Heuring 999 M. Murdocca and V. Heuring
9 22 Chapter 2: Data Representation Signed Magnitude Also know as sign and magnitude, the leftmost bit is the sign ( = positive, = negative) and the remaining bits are the magnitude. Example: +25 = 225 = 2 Two representations for zero: + = 2,  = 2. Largest number is +27, smallest number is 27, using an 8bit representation. Principles of Computer Architecture by M. Murdocca and V. Heuring 999 M. Murdocca and V. Heuring
10 23 Chapter 2: Data Representation One s Complement The leftmost bit is the sign ( = positive, = negative). Negative of a number is obtained by subtracting each bit from 2 (essentially, complementing each bit from to or from to ). This goes both ways: converting positive numbers to negative numbers, and converting negative numbers to positive numbers. Example: +25 = 225 = 2 Two representations for zero: + = 2,  = 2. Largest number is +27, smallest number is 27, using an 8 bit representation. Principles of Computer Architecture by M. Murdocca and V. Heuring 999 M. Murdocca and V. Heuring
11 24 Chapter 2: Data Representation Two s Complement The leftmost bit is the sign ( = positive, = negative). Negative of a number is obtained by adding to the one s complement negative. This goes both ways, converting between positive and negative numbers. Example (recall that 25 in one s complement is 2 ): +25 = 225 = 2 One representation for zero: + = 2,  = 2. Largest number is +27, smallest number is 28, using an 8 bit representation. Principles of Computer Architecture by M. Murdocca and V. Heuring 999 M. Murdocca and V. Heuring
12 25 Excess (Biased) Chapter 2: Data Representation The leftmost bit is the sign (usually = positive, = negative). Positive and negative representations of a number are obtained by adding a bias to the two s complement representation. This goes both ways, converting between positive and negative numbers. The effect is that numerically smaller numbers have smaller bit patterns, simplifying comparisons for floating point exponents. Example (excess 28 adds 28 to the two s complement version, ignoring any carry out of the most significant bit) : +2 = 22 = 2 One representation for zero: + = 2,  = 2. Largest number is +27, smallest number is 28, using an 8 bit representation. Principles of Computer Architecture by M. Murdocca and V. Heuring 999 M. Murdocca and V. Heuring
13 Signed Magnitude Example: Convert = = 223 => 2 One s Complement (flip the bits) 23 => 2 Two s Complement (add to one s complement) 23 => 2 Excess 28 (add 28 to two s complement) 23 => 2 UMBC, CMSC33, Richard Chang
14 3bit Signed Integer Representations Decimal Unsigned Sign Mag s Comp 2 s Comp Excess / / UMBC, CMSC33, Richard Chang
15 2 Chapter 2: Data Representation Binary Addition This simple binary addition example provides background for the signed number representations to follow. Carry in Operands Carry out Sum Carry Addend: A Augend: B Sum + Example: (24) (9) (24) Principles of Computer Architecture by M. Murdocca and V. Heuring 999 M. Murdocca and V. Heuring
16 34 Number Circle for 3Bit Two s Complement Numbers Chapter 3: Arithmetic Numbers can be added or subtracted by traversing the number circle clockwise for addition and counterclockwise for subtraction. Overflow occurs when a transition is made from +3 to 4 while proceeding around the number circle when adding, or from 4 to +3 while subtracting.  Subtracting numbers Adding numbers Principles of Computer Architecture by M. Murdocca and V. Heuring 999 M. Murdocca and V. Heuring
17 8bit Two s Complement Addition 54 = = 6 = 44 = = 4 = 44 = = 92 = UMBC, CMSC33, Richard Chang
18 Two s Complement Overflow An overflow occurs if adding two positive numbers yields a negative result or if adding two negative numbers yields a positive result. Adding a positive and a negative number never causes an overflow. Carry out of the most significant bit does not indicate an overflow. An overflow occurs when the carry into the most significant bit differs from the carry out of the most significant bit. UMBC, CMSC33, Richard Chang
19 Two s Complement Overflow Examples 54 = + 8 = 623 = = 5 UMBC, CMSC33, Richard Chang
20 Two s Complement Sign Extension Decimal 8bit 6bit +55 Why does sign extension work? x is represented as x in 8bit x is represented as x in 6bit x +??? = x??? = = = 256 = 6528 UMBC, CMSC33, Richard Chang
21 MODULO ARITHMETIC
22 Is Two s Complement Magic? Why does adding positive and negative numbers work? Why do we add to the one s complement to negate? Answer: Because modulo arithmetic works. UMBC, CMSC33, Richard Chang
23 Modulo Arithmetic Definition: Let a and b be integers and let m be a positive integer. We say that a b (mod m) if the remainder of a divided by m is equal to the remanider of b divided by m. In the C programming language, a b (mod m) would be written a % m == b % m We use the theorem: If a b (mod m) and c d (mod m) then a + c b + d (mod m).
24 ATheoremofModuloArithmetic Thm: If a b (mod m) and c d (mod m) then a + c b + d (mod m). Example: Let m =8, a =3, b =27, c =2and d = (mod 8) and 2 8 (mod 8) (mod 8). Proof: Write a = q a m + r a, b = q b m + r b, c = q c m + r c and d = q d m + r d, where r a, r b, r c and r d are between and m. Then, a + c =(q a + q c )m + r a + r c b + d =(q b + q d )m + r b + r d =(q b + q d )m + r a + r c. Thus, a + c r a + r c b + d (mod m). 2
25 Consider Numbers Modulo = = = = = = = = = If 2 thru 2 represents thru 27 and 2 thru 2 represents 28 thru , then the most significant bit can be used to determine the sign. 3
26 Some Answers In 8bit two s complement, we use addition modulo 2 8 =256,soadding 256 or subtracting 256 is equivalent to adding or subtracting. To negate a number x, x 28: x = x 256 x =(255 x)+=( 2 x)+ Note that 2 x is the one s complement of x. Now we can just add positive and negative numbers. For example: 3+( 5) 3+(256 5) = = = 2. or two negative numbers (as long as there s no overflow): ( 3) + ( 5) (256 3) + (256 5) = = 8. 4
27 FLOATING POINT NUMBERS
28 IEEE bit Floating Point Format sign bit, 8bit exponent, 23bit mantissa normalized as.xxxxx leading is hidden 8bit exponent in excess 27 format NOT excess 28 and are reserved + and  is zero exponent and zero mantissa exponent and zero mantissa is infinity UMBC, CMSC33, Richard Chang
29 227 Chapter 2: Data Representation IEEE754 Floating Point Formats 32 bits Single precision Sign ( bit) 8 bits 23 bits Exponent Fraction 64 bits Double precision bits 52 bits Exponent Fraction Principles of Computer Architecture by M. Murdocca and V. Heuring 999 M. Murdocca and V. Heuring
30 229 Chapter 2: Data Representation IEEE754 Conversion Example Represent in single precision IEEE754 format. Step #: Convert to target base = . 2 Step #2: Normalize = Step #3: Fill in bit fields. Sign is negative, so sign bit is. Exponent is in excess 27 (not excess 28!), so exponent is represented as the unsigned integer = 3. Leading of significand is hidden, so final bit pattern is:. Principles of Computer Architecture by M. Murdocca and V. Heuring 999 M. Murdocca and V. Heuring
31 228 Chapter 2: Data Representation IEEE754 Examples Value Bit Pattern (a) Sign Exponent Fraction (b) (c) (d) + (e) (f) + (g) (h) +NaN (i) Principles of Computer Architecture by M. Murdocca and V. Heuring 999 M. Murdocca and V. Heuring
32 CHARACTERS & STRINGS
33 23 Chapter 2: Data Representation ASCII Character Code ASCII is a 7bit code, commonly stored in 8bit bytes. A is at 4 6. To convert upper case letters to lower case letters, add 2 6. Thus a is at = 6 6. The character 5 at position 35 6 is different than the number 5. To convert characternumbers into numbernumbers, subtract 3 6 : = 5. NUL SOH 2 STX 3 ETX 4 EOT 5 ENQ 6 ACK 7 BEL 8 BS 9 HT A LF B VT C FF D CR E SO F SI NUL SOH STX ETX EOT ENQ ACK BEL BS HT LF VT DLE DC 2 DC2 3 DC3 4 DC4 5 NAK 6 SYN 7 ETB 8 CAN 9 EM A SUB B ESC C FS D GS E RS F US 2 SP 2! 22 " 23 # 24 $ 25 % 26 & 27 ' 28 ( 29 ) 2A * 2B + 2C 2D  2E. 2F / Null Start of heading Start of text End of text End of transmission Enquiry Acknowledge Bell Backspace Horizontal tab Line feed Vertical tab FF CR SO SI DLE DC DC2 DC3 DC4 NAK SYN ETB A : 3B ; 3C < 3D = 3E > 3F? 4 A 42 B 43 C 44 D 45 E 46 F 47 G 48 H 49 I 4A J 4B K 4C L 4D M 4E N 4F O 5 P 5 Q 52 R 53 S 54 T 55 U 56 V 57 W 58 X 59 Y 5A Z 5B [ 5C \ 5D ] 5E ^ 5F _ Form feed Carriage return Shift out Shift in Data link escape Device control Device control 2 Device control 3 Device control 4 Negative acknowledge Synchronous idle End of transmission block 6 ` 6 a 62 b 63 c 64 d 65 e 66 f 67 g 68 h 69 i 6A j 6B k 6C l 6D m 6E n 6F o CAN EM SUB ESC FS GS RS US SP DEL 7 p 7 q 72 r 73 s 74 t 75 u 76 v 77 w 78 x 79 y 7A z 7B { 7C 7D } 7E ~ 7F DEL Cancel End of medium Substitute Escape File separator Group separator Record separator Unit separator Space Delete Principles of Computer Architecture by M. Murdocca and V. Heuring 999 M. Murdocca and V. Heuring
34 232 Chapter 2: Data Representation EBCDIC Character Code EBCDIC is an 8bit code. STX Start of text RS Reader Stop DC Device Control BEL Bell DLE Data Link Escape PF Punch Off DC2 Device Control 2 SP Space BS Backspace DS Digit Select DC4 Device Control 4 IL Idle ACK Acknowledge PN Punch On CU Customer Use NUL Null SOH Start of Heading SM Set Mode CU2 Customer Use 2 ENQ Enquiry LC Lower Case CU3 Customer Use 3 ESC Escape CC Cursor Control SYN Synchronous Idle BYP Bypass CR Carriage Return IFS Interchange File Separator CAN Cancel EM End of Medium EOT End of Transmission RES Restore FF Form Feed ETB End of Transmission Block SI Shift In TM Tape Mark NAK Negative Acknowledge SO Shift Out UC Upper Case SMM Start of Manual Message DEL Delete FS Field Separator SOS Start of Significance SUB Substitute HT Horizontal Tab IGS Interchange Group Separator NL New Line VT Vertical Tab IRS Interchange Record Separator LF Line Feed UC Upper Case IUS Interchange Unit Separator NUL 2 DS 4 SP 6 8 A C { E \ SOH 2 SOS 4 6 / 8 a A ~ C A E 2 STX 22 FS b A2 s C2 B E2 S 3 ETX c A3 t C3 C E3 T 4 PF 24 BYP d A4 u C4 D E4 U 5 HT 25 LF e A5 v C5 E E5 V 6 LC 26 ETB f A6 w C6 F E6 W 7 DEL 27 ESC g A7 x C7 G E7 X h A8 y C8 H E8 Y i A9 z C9 I E9 Z A SMM 2A SM 4A 6A 8A AA CA EA B VT 2B CU2 4B 6B, 8B AB CB EB C FF 2C 4C < 6C % 8C AC CC EC D CR 2D ENQ 4D ( 6D _ 8D AD CD ED E SO 2E ACK 4E + 6E > 8E AE CE EE F SI 2F BEL 4F 6F? 8F AF CF EF DLE 3 5 & 7 9 B D } F DC j B D J F 2 DC2 32 SYN k B2 D2 K F2 2 3 TM l B3 D3 L F3 3 4 RES 34 PN m B4 D4 M F4 4 5 NL 35 RS n B5 D5 N F5 5 6 BS 36 UC o B6 D6 O F6 6 7 IL 37 EOT p B7 D7 P F7 7 8 CAN q B8 D8 Q F8 8 9 EM r B9 D9 R F9 9 A CC 3A 5A! 7A : 9A BA DA FA B CU 3B CU3 5B $ 7B # 9B BB DB FB C IFS 3C DC4 5C. 9C BC DC FC D IGS 3D NAK 5D ) 7D ' 9D BD DD FD E IRS 3E 5E ; 7E = 9E BE DE FE F IUS 3F SUB 5F 7F " 9F BF DF FF Principles of Computer Architecture by M. Murdocca and V. Heuring 999 M. Murdocca and V. Heuring
35 233 Unicode Character Code Unicode is a 6 bit code A B C D E F A B C D E F NUL 2 SOH 2 STX 22 ETX 23 EOT 24 ENQ 25 ACK 26 BEL 27 BS HT LF 2A VT 2B FF 2C CR 2D SO 2E SI 2F DLE 3 DC 3 DC2 32 DC3 33 DC4 34 NAK 35 SYN 36 ETB 37 CAN 38 EM 39 SUB ESC FS GS RS US 3A 3B 3C 3D 3E 3F SP! " # $ % & ' ( ) * + . / : ; < = >? A 4B 4C 4D 4E 4F A 5B 5C 5D 5E 5F NUL Null SOH Start of heading CAN Cancel SP Space STX Start of text EOT End of transmission EM End of medium DEL Delete ETX End of text DC Device control SUB Substitute Control ENQ Enquiry DC2 Device control 2 ESC Escape FF Form feed ACK Acknowledge DC3 Device control 3 FS File separator CR Carriage return BEL Bell DC4 Device control 4 GS Group separator SO Shift out BS Backspace NAK Negative acknowledge RS Record separator SI Shift in HT Horizontal tab NBS Nonbreaking space US Unit separator DLE Data link escape LF Line feed ETB End of transmission block SYN Synchronous idle VT Vertical tab Principles of Computer Architecture by M. Murdocca and V. Heuring 999 M. Murdocca and V. A B C D E F G H I J K L M N O P Q R S T U V W X Y Z [ \ ] ^ _ A 6B 6C 6D 6E 6F A 7B 7C 7D 7E 7F ` a b c d e f g h i j k l m n o p q r s t u v w x y z { } ~ DEL A 8B 8C 8D 8E 8F A 9B 9C 9D 9E 9F P Chapter 2: Data Representation A NBS C À E à A C Á E á A2 C2 Â E2 â A3 C3 Ã E3 ã A4 C4 Ä E4 ä A5 C5 Å E5 å A6 & C6 Æ E6 æ A7 C7 Ç E7 ç A8 C8 È E8 è A9 C9 É E9 é AA a CA Ê EA ê AB «CB Ë EB ë AC CC Ì EC ì AD CD Í ED í AE CE Î EE î AF CF Ï EF ï B D D F B ± D Ñ F ñ B2 2 D2 Ò F2 ò B3 3 D3 Ó F3 ó B4 D4 Ô F4 ô B5 µ D5 Õ F5 õ B6 D6 Ö F6 ö B7 D7 F7 B8 Ç D8 Ø F8 ø B9 D9 Ù F9 ù BA o DA Ú FA ú BB» DB Û FB û BC /4 DC Ü FC ü BD /2 DD Y FD BE 3/4 DE y FE p BF DF FF ÿ
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