Lecture 3. Behavioral Modeling Sequential Circuits. Registers Counters Finite State Machines
|
|
- Pearl McKinney
- 5 years ago
- Views:
Transcription
1 Lecture 3 Behavioral Modeling Sequential Circuits Registers Counters Finite State Machines
2 Behavioral Modeling Behavioral Modeling Behavioral descriptions use the keyword always, followed by optional event control expression and a list of procedural assignment statements The event control expression specifies when the statements will execute The target output of a procedural assignment statement must of the reg type // Behavioral description of two-to-one multiplexer // Verilog 2001 module mux_2x1_beh ( output reg m_out, input A, B, select ); B, select) if(select) m_out = A; else m_out = B; module // Behavioral description of two-to-one multiplexer // Verilog 2001 module mux_2x1_beh ( output reg m_out, input A, B, select ); // case(select) 1 b1: m_out = A; 1 b0: m_out = B; case module
3 Sequential Circuit Sequential Circuits A circuit whose state is specified by a time sequence of inputs, outputs and internal states The storage elements are circuits capable of storing binary information The binary information stored in these devices at any given time determine the state of the sequential circuit The sequential circuit receives binary information from the inputs that, together with the present state of the storage elements, determines the outputs
4 Sequential Circuits Two main types of Sequential Circuit Asynchronous, Synchronous Asynchronous Behavior (outputs/state) deps upon the input signals at any instant of time and the order in which the inputs change The storage elements commonly used are time-delay devices» The storage capability varies with logic gate propagation delay Varies with Process, Voltage and Temperature (PVT) May be regarded as a combinational circuit with feedback
5 Sequential Circuits Non-Storage Asynchronous Examples One Shot (Not sequential per definition as no FB) Ring Oscillator Must have odd number of stages Used as: clock source before main clock stable measure of PVT via frequency Voltage controlled Oscillator (VCO)
6 Sequential Circuits Non-Storage Asynchronous Examples Mercury Delay Lines Early computers required delay lines that had to be timed such that the pulses would arrive at the receiver just as the computer was ready to read it. Used acoustic pulses in the mercury to provide delay
7 Synchronous Sequential Circuits Employs signals that affect the storage elements at discrete instants of time Synchronization is achieved by using a clock signal Time stable periodic train of pulses Distributed throughout the device such that storage element are affect only with the arrival of each pulse Modern SoC may have several clock domains, i.e. areas of logic clocked by different clock speeds Timing is easily broken down into indepent discrete steps, each of which can be considered separately
8 Storage Elements: Flip Flops Direct Inputs Asynchronous set and/or reset inputs that force flip flop to a particular state indepently of the clock. Used to bring storage elements to know state upon power up or put system in an initial state May reset part several times during testing Asynchronously assert reset but de-assert synchronously Want all devices to come out of reset at the same time If reset released at or near active clock edge, flip flop output could go metastable FPGA flip flops initialize to zero upon programming.
9 Verilog Register Coding // D Flip Flop Asynchronous Reset Example Clk or posedge R) begin if(r == 1 b1) Q <= 1 b0; else Q <= D; // Another D Flip Flop Asynchronous Reset Example Clk, negedge R) if(!reset ) Q <=!Rb? 1 b0 : Data; // D Flip Flop Synchronous Reset Example Clk) begin if(r) Q <= 1 b0; else Q <= D; R D b b // D Flip Flop Synchronous Reset Example Clk) begin if(rb) Q <= 1 b0; else Q <= D; Rb D
10 Synchronous versus Asynchronous Reset Advantages The biggest advantage to using asynchronous resets is that, as long as the vor library has asynchronously resettable flip-flops, the data path is guaranteed to be clean. Designs that are pushing the limit for data path timing, can not afford to have added gates and additional net delays in the data path due to logic inserted to handle synchronous resets. This argument does not hold if the vor library has flipflops with synchronous reset inputs and the designer can get Synopsys to actually use those pins. Using an asynchronous reset, the designer is guaranteed not to have the reset added to the data path.
11 Synchronous versus Asynchronous Reset Disadvantages The biggest problem with asynchronous resets is that they are asynchronous, both at the assertion and at the deassertion of the reset. The assertion is a non issue, the de-assertion is the issue. If the asynchronous reset is released at or near the active clock edge of a flip-flop, the output of the flipflop could go metastable and thus the reset state of the ASIC could be lost. Another problem that an asynchronous reset can have, deping on its source, is spurious resets due to noise or glitches on the board or system reset.
12 Reset Synchronizer Circuit
13 Transistor count: Without Reset: Total: 10 transistors Asynchronous Reset: Replace upper two inverters with two input NANDs Total: 14 transistors Synchronous Reset: Add NOR in front of D Total: 14 transistors
14 Blocking versus Non-Blocking Blocking = Executed sequentially in the order they are listed in the block of statements initial begin A = B + 1; // Executes first B = W; // Executes second C = Z W; // Executes third Non-blocking <= Executes concurrently by evaluating the set of expressions on the right hand side and then make the left hand side clk) begin if(reset) begin A <= 8 h00; B <= 8 haa; else begin A <= X && Y; B <= W;
15 Blocking versus Non-Blocking What about case statement? Use blocking assignments to model combinational logic within an always block or B or S) begin : mux case (S) 1'b0: y = A; 1'b1: y = B; default: y = 1'bx; case Optional name
16 Inferred Latches Omitting a clause in a control construct (case, if-else) can cause an inferred latch x, y, z, sel) case (sel) 2'b00: out = w; 2'b01: out = x; 2'b10: out = y; 2'b10: out = z; // TYPO. This line not executed, 2 b11 case missing. case x, y, sel) // Missing z case (sel) 2'b00: out = w; 2'b01: out = x; 2'b10: out = y; 2'b10: out = z; // This line will not execute when z changes case Correct coding // out always assigned x, y, sel) begin out = 4 h0; case (sel) 2'b00: out = w; 2'b01: out = x; 2'b10: out = y; case // out always assigned x, y, sel) begin case (sel) 2'b00: out = w; 2'b01: out = x; 2'b10: out = y; default: out = 4 h0; case
17 Registers A register is a group of Flip Flips (FFs), each one of which shares a common clock and is capable of storing one bit of information. An n-bit register consists of a group of n FFs capable of storing n bits of information. Registers may have combinational logic that performs specific data processing tasks The FFs hold the binary information and the comb. Logic determines how the information is transferred into the register A counter is a specific type of register that goes through a predetermined sequence of binary states.
18 Registers Four-bit register with parallel load: Output A[3:0] changes with I[3:0] on Posedge of Clock module figure_6p1( input Clock, Clear_b, input [3:0] I, output reg [3:0] A ); Clock, negedge Clear_b) if (!Clear_b) A <= 4 h0; else A <= I; module
19 Registers Shift Registers: A register capable of shifting the binary information held in each cell to its neighboring cell in a predetermined direction Consists of a chain of FFs in cascade, with the output of one FF connected to the input of the next FF All FFs receive a common clock, which activate the shift of data from one stage to the next Can also incorporate a shift enable to activate/deactivate
20 Registers module fig6p3a( input CLK, SI, output SO); module fig6p3b( input CLK, SI, output SO); Note: blocking assignment reg [3:0] A; CLK) A <= {SI, A[3:1]}; assign SO = A[0]; module or reg [3:0] A; CLK) begin A = A >> 1; A[3] = SI; assign SO = A[0]; module Synopsys for right side example
21 Synchronous Counters: Synchronous Counters A clock pulse is applied to the clock inputs of all counter FFs Binary Counter: LSB FF complemented every clock pulse FFs in any other position are complemented when all the bits in the lower significant positions are equal to 1. module bincntr( input clk, clearb, input [7:0] datain, output reg [7:0] cnt); clk, negedge clearb) if (clearb == 1 b0) cnt <= 8'h00; else cnt <= cnt + 1; module
22 Synchronous Counters Binary Counter with Parallel Load, sync clear module bincntr( input clk, clearb, cntena, load, input [7:0] datain, output reg [7:0] cnt); clk) if (!clearb) cnt <= 8'h00; else if (load) cnt <= datain; else if (cntena) cnt <= cnt + 1; else cnt <= cnt; module
23 Ring Counter: Other Counters A circular shift register with only one flop being set at a given time Useful when trying to meet timing No Decoding (comb. logic) required One FF for each value, thus get big quickly module ringcntr( input clk, clearb, cntena, output reg [7:0] cnt); clk) if (!clearb) cnt <= 8'h80; else if (cntena) cnt <= {cnt[0], cnt[7:1]}; else cnt <= cnt; module
24 Synchronous Counters Up-Down Binary Counter: module bincntr( input clk, clearb, cntena, updwn, output reg [7:0] cnt; clk) if (!clearb) cnt <= 8'h00; else if (cntena) if(updwn) cnt <= cnt + 1; else cnt <= cnt - 1; else cnt <= cnt; module module bincntr_tb(); reg clk = 0; reg cntena = 0; reg clearb = 1; reg updwn = 1; wire [7:0] cnt; bincntr DUT(.clk(clk),.clearb(clearb),.cntEna(cntEna),.upDwn(upDwn),.cnt(cnt)); always #10 clk = ~clk; initial clk) clearb = clk) clearb = clk) cntena = 1; clk); cntena = 0; clk); cntena = 1; clk); updwn = 0; clk); $stop; module
25 Binary Counter: module bincntr( input clk, clearb, cntena, output reg [7:0] cnt); clk) if (!clearb) cnt <= 8'h00; else if (cntena) cnt <= cnt + 1; // else // cnt <= cnt; module Synchronous Counters module bincntr_tb(); reg clk = 0; reg cntena = 0; reg clearb = 1; wire [7:0] cnt; bincntr DUT(.clk(clk),.clearb(clearb),.cntEna(cntEna),.cnt(cnt)); always #10 clk = ~clk; initial clk) clearb = clk) clearb = clk) cntena = 1; clk); cntena = 0; clk); module
26 Synchronous Counters BCD Counter: module bcdcntr( input clk, clearb, cntena, output reg[7:0] cnt); clk) if (!clearb) cnt <= 8'h00; else if (cntena) if(cnt == 4'd9) cnt <= 4'd0; else cnt <= cnt + 1; else cnt <= cnt; module
27 Other Counters
28 Other Counters Johnson Counter: A k-bit ring counter circulates a single bit through the FFs to provide k unique states The number of states can be doubled if the shift register is connected as a switch-tail ring counter A switch-tail counter is a circular shift register with the complemented output of the last FF connected to the input of the last FF A Johnson counter is a k-bit switch tail ring counter with 2k decoded gates to provide 2k timing signals (not shown in Figure 6.18)
29 Fininte State Machines Mealy and Moore Models Finite State Machines Differ only in the way the output(s) is/are generated Mealy: output(s) function of both present state and input(s) Output(s) must be valid (stable) immediately before the clock active edge Moore: output(s) function of present state only Output(s) synchronized with the clock A circuit may have both types of outputs
30 FSM coding styles Many ways are possible Two common ways are: Two always blocks One for sequential logic One for combinational logic One always block Two always block is easiest to implement and understand and will be discuss here.
31 Two always blocks Sequential always block // State Register clk or posedge reset) if (reset) state <= IDLE; else state <= next_state; Combinational always block // Next State Case begin next_state = 2 b00; case (state) IDLE: begin if (!in1) next = IDLE; if (in1 & in2) next = S1; if (in1 &!in2 & in3) next = S2; S1:
32 FSM Output Generation Code the output logic as either a separate block of continuous assignments or within the combinational always block // Mealy Outputs assign y = ((state == S1) (state == S2) (state == S3)) &&!x; begin case({current_state[1:0], x}) 3'b000: begin next_state = 2'b00; y_sd = 0; 3'b001: begin next_state = 2'b01; y_sd = 0; 3'b010: begin next_state = 2'b00; y_sd = 1; 3'b011: begin next_state = 2'b11; y_sd = 0; case // case (current_state[1:0], x) // (*)
33 Two always blocks Source:
34 State Assignment // Binary Encoding parameter definitions parameter [1:0] IDLE = 2 b00, S1 = 2 b01, S2 = 2 b10, S3 = 2 b11; // One Hot Encoding parameter definitions parameter [3:0] IDLE = 4 b0001, S1 = 4 b0010, S2 = 4 b0100, S3 = 4 b1000; // One Cold Encoding parameter definitions parameter [3:0] IDLE = 4 b1110, S1 = 4 b1101, S2 = 4 b1011, S3 = 4 b0111; // Gray Code Encoding parameter definitions parameter [1:0] IDLE = 2 b00, S1 = 2 b01, S2 = 2 b11, S3 = 2 b10; Binary encoding only requires as many FFs as are needed to uniquely encode the number of state. One hot requires a FF for each state in the design and only one FF is set a time. One hot recommed for FPGA designs as FFs are plentiful with FPGAs and the combinational logic required is typically smaller. One hot designs typically run faster
35 module fig5p15(input x, Clock, output reg y_out); reg [1:0] current_state = 2'b00, next_state = 2'b00; reg [2*7:0] StateName; begin StateName = "--"; case(current_state) 2'b00: StateName = "S0"; 2'b01: StateName = "S1"; 2'b10: StateName = "S2"; 2'b11: StateName = "S3"; case Clock) current_state <= next_state; begin StateName = "--"; case(current_state) 2'b00: StateName = "S0"; 2'b01: StateName = "S1"; 2'b10: StateName = "S2"; 2'b11: StateName = "S3"; case begin case({current_state[1:0], x}) 3'b000: begin next_state = 2'b00; y_out = 0; 3'b001: begin next_state = 2'b01; y_out = 0; 3'b010: begin next_state = 2'b00; y_out = 1; 3'b011: begin next_state = 2'b11; y_out = 0; 3'b100: begin next_state = 2'b00; y_out = 1; 3'b101: begin next_state = 2'b10; y_out = 0; 3'b110: begin next_state = 2'b00; y_out = 1; 3'b111: begin next_state = 2'b10; y_out = 0; case module
EECS150 - Digital Design Lecture 20 - Finite State Machines Revisited
EECS150 - Digital Design Lecture 20 - Finite State Machines Revisited April 2, 2009 John Wawrzynek Spring 2009 EECS150 - Lec20-fsm Page 1 Finite State Machines (FSMs) FSM circuits are a type of sequential
More informationLogic Circuits II ECE 2411 Thursday 4:45pm-7:20pm. Lecture 3
Logic Circuits II ECE 2411 Thursday 4:45pm-7:20pm Lecture 3 Lecture 3 Topics Covered: Chapter 4 Discuss Sequential logic Verilog Coding Introduce Sequential coding Further review of Combinational Verilog
More informationEE178 Lecture Verilog FSM Examples. Eric Crabill SJSU / Xilinx Fall 2007
EE178 Lecture Verilog FSM Examples Eric Crabill SJSU / Xilinx Fall 2007 In Real-time Object-oriented Modeling, Bran Selic and Garth Gullekson view a state machine as: A set of input events A set of output
More informationECE 551: Digital System *
ECE 551: Digital System * Design & Synthesis Lecture Set 5 5.1: Verilog Behavioral Model for Finite State Machines (FSMs) 5.2: Verilog Simulation I/O and 2001 Standard (In Separate File) 3/4/2003 1 Explicit
More informationIn the previous lecture, we examined how to analyse a FSM using state table, state diagram and waveforms. In this lecture we will learn how to design
1 In the previous lecture, we examined how to analyse a FSM using state table, state diagram and waveforms. In this lecture we will learn how to design a fininte state machine in order to produce the desired
More informationIn the previous lecture, we examined how to analyse a FSM using state table, state diagram and waveforms. In this lecture we will learn how to design
In the previous lecture, we examined how to analyse a FSM using state table, state diagram and waveforms. In this lecture we will learn how to design a fininte state machine in order to produce the desired
More informationWriting Circuit Descriptions 8
8 Writing Circuit Descriptions 8 You can write many logically equivalent descriptions in Verilog to describe a circuit design. However, some descriptions are more efficient than others in terms of the
More informationBlocking(=) vs Nonblocking (<=) Assignment. Lecture 3: Modeling Sequential Logic in Verilog HDL. Procedural assignments
Blocking(=) vs Nonblocking (
More informationModeling Synchronous Logic Circuits. Debdeep Mukhopadhyay IIT Madras
Modeling Synchronous Logic Circuits Debdeep Mukhopadhyay IIT Madras Basic Sequential Circuits A combinational circuit produces output solely depending on the current input. But a sequential circuit remembers
More informationGraduate Institute of Electronics Engineering, NTU. Lecturer: Chihhao Chao Date:
Design of Datapath Controllers and Sequential Logic Lecturer: Date: 2009.03.18 ACCESS IC LAB Sequential Circuit Model & Timing Parameters ACCESS IC LAB Combinational Logic Review Combinational logic circuits
More informationECE 2300 Digital Logic & Computer Organization. More Verilog Finite State Machines
ECE 2300 Digital Logic & Computer Organization Spring 2018 More Verilog Finite Machines Lecture 8: 1 Prelim 1, Thursday 3/1, 1:25pm, 75 mins Arrive early by 1:20pm Review sessions Announcements Monday
More informationFinite State Machines
Lab Workbook Introduction (FSM) are sequential circuit used in many digital systems to control the behavior of systems and dataflow paths. Examples of FSM include control units and sequencers. This lab
More informationEECS150 - Digital Design Lecture 5 - Verilog Logic Synthesis
EECS150 - Digital Design Lecture 5 - Verilog Logic Synthesis Jan 31, 2012 John Wawrzynek Spring 2012 EECS150 - Lec05-verilog_synth Page 1 Outline Quick review of essentials of state elements Finite State
More informationVerilog Tutorial. Introduction. T. A.: Hsueh-Yi Lin. 2008/3/12 VLSI Digital Signal Processing 2
Verilog Tutorial T. A.: Hsueh-Yi Lin Introduction 2008/3/12 VLSI Digital Signal Processing 2 Verilog: A common language for industry HDL is a common way for hardware design Verilog VHDL Verilog is widely
More informationSynthesis vs. Compilation Descriptions mapped to hardware Verilog design patterns for best synthesis. Spring 2007 Lec #8 -- HW Synthesis 1
Verilog Synthesis Synthesis vs. Compilation Descriptions mapped to hardware Verilog design patterns for best synthesis Spring 2007 Lec #8 -- HW Synthesis 1 Logic Synthesis Verilog and VHDL started out
More informationSequential Logic Design
Sequential Logic Design Design of Digital Circuits 2017 Srdjan Capkun Onur Mutlu (Guest starring: Frank K. Gürkaynak and Aanjhan Ranganathan) http://www.syssec.ethz.ch/education/digitaltechnik_17 Adapted
More informationECE 4514 Digital Design II. Spring Lecture 15: FSM-based Control
ECE 4514 Digital Design II Lecture 15: FSM-based Control A Design Lecture Overview Finite State Machines Verilog Mapping: one, two, three always blocks State Encoding User-defined or tool-defined State
More informationWhy Should I Learn This Language? VLSI HDL. Verilog-2
Verilog Why Should I Learn This Language? VLSI HDL Verilog-2 Different Levels of Abstraction Algorithmic the function of the system RTL the data flow the control signals the storage element and clock Gate
More informationa, b sum module add32 sum vector bus sum[31:0] sum[0] sum[31]. sum[7:0] sum sum overflow module add32_carry assign
I hope you have completed Part 1 of the Experiment. This lecture leads you to Part 2 of the experiment and hopefully helps you with your progress to Part 2. It covers a number of topics: 1. How do we specify
More informationModeling of Finite State Machines. Debdeep Mukhopadhyay
Modeling of Finite State Machines Debdeep Mukhopadhyay Definition 5 Tuple: (Q,Σ,δ,q 0,F) Q: Finite set of states Σ: Finite set of alphabets δ: Transition function QχΣ Q q 0 is the start state F is a set
More informationLecture 32: SystemVerilog
Lecture 32: SystemVerilog Outline SystemVerilog module adder(input logic [31:0] a, input logic [31:0] b, output logic [31:0] y); assign y = a + b; Note that the inputs and outputs are 32-bit busses. 17:
More informationSynthesis of Combinational and Sequential Circuits with Verilog
Synthesis of Combinational and Sequential Circuits with Verilog What is Verilog? Hardware description language: Are used to describe digital system in text form Used for modeling, simulation, design Two
More informationCSE140L: Components and Design Techniques for Digital Systems Lab
CSE140L: Components and Design Techniques for Digital Systems Lab Tajana Simunic Rosing Source: Vahid, Katz, Culler 1 Announcements & Outline Lab 4 due; demo signup times listed on the cse140l site Check
More informationVerilog for High Performance
Verilog for High Performance Course Description This course provides all necessary theoretical and practical know-how to write synthesizable HDL code through Verilog standard language. The course goes
More informationEEL 4783: HDL in Digital System Design
EEL 4783: HDL in Digital System Design Lecture 15: Logic Synthesis with Verilog Prof. Mingjie Lin 1 Verilog Synthesis Synthesis vs. Compilation Descriptions mapped to hardware Verilog design patterns for
More informationDigital Integrated Circuits
Digital Integrated Circuits Lecture 4 Jaeyong Chung System-on-Chips (SoC) Laboratory Incheon National University BCD TO EXCESS-3 CODE CONVERTER 0100 0101 +0011 +0011 0111 1000 LSB received first Chung
More informationFSM and Efficient Synthesizable FSM Design using Verilog
FSM and Efficient Synthesizable FSM Design using Verilog Introduction There are many ways to code FSMs including many very poor ways to code FSMs. This lecture offers guidelines for doing efficient coding,
More informationMCMASTER UNIVERSITY EMBEDDED SYSTEMS
MCMASTER UNIVERSITY EMBEDDED SYSTEMS Computer Engineering 4DS4 Lecture Revision of Digital Systems Amin Vali January 26 Course material belongs to DrNNicolici Field programmable gate arrays (FPGAs) x x
More informationECE 574: Modeling and Synthesis of Digital Systems using Verilog and VHDL. Fall 2017 Final Exam (6.00 to 8.30pm) Verilog SOLUTIONS
ECE 574: Modeling and Synthesis of Digital Systems using Verilog and VHDL Fall 2017 Final Exam (6.00 to 8.30pm) Verilog SOLUTIONS Note: Closed book no notes or other material allowed apart from the one
More informationCSE140L: Components and Design
CSE140L: Components and Design Techniques for Digital Systems Lab Tajana Simunic Rosing Source: Vahid, Katz, Culler 1 Grade distribution: 70% Labs 35% Lab 4 30% Lab 3 20% Lab 2 15% Lab 1 30% Final exam
More informationOutline. EECS Components and Design Techniques for Digital Systems. Lec 11 Putting it all together Where are we now?
Outline EECS 5 - Components and Design Techniques for Digital Systems Lec Putting it all together -5-4 David Culler Electrical Engineering and Computer Sciences University of California Berkeley Top-to-bottom
More informationVerilog Sequential Logic. Verilog for Synthesis Rev C (module 3 and 4)
Verilog Sequential Logic Verilog for Synthesis Rev C (module 3 and 4) Jim Duckworth, WPI 1 Sequential Logic Module 3 Latches and Flip-Flops Implemented by using signals in always statements with edge-triggered
More informationNote: Closed book no notes or other material allowed, no calculators or other electronic devices.
ECE 574: Modeling and Synthesis of Digital Systems using Verilog and VHDL Fall 2017 Exam Review Note: Closed book no notes or other material allowed, no calculators or other electronic devices. One page
More informationECE 2300 Digital Logic & Computer Organization. More Verilog Finite State Machines
ECE 2300 Digital Logic & Computer Organization Spring 2017 More Verilog Finite State Machines Lecture 8: 1 Announcements 1 st batch of (raw) quiz scores released on CMS Solutions to HW 1-3 released on
More informationHANSABA COLLEGE OF ENGINEERING & TECHNOLOGY (098) SUBJECT: DIGITAL ELECTRONICS ( ) Assignment
Assignment 1. What is multiplexer? With logic circuit and function table explain the working of 4 to 1 line multiplexer. 2. Implement following Boolean function using 8: 1 multiplexer. F(A,B,C,D) = (2,3,5,7,8,9,12,13,14,15)
More informationChapter 5 Registers & Counters
University of Wisconsin - Madison ECE/Comp Sci 352 Digital Systems Fundamentals Kewal K. Saluja and Yu Hen Hu Spring 2002 Chapter 5 Registers & Counters Originals by: Charles R. Kime Modified for course
More informationTechniques for Digital Systems Lab. Verilog HDL. Tajana Simunic Rosing. Source: Eric Crabill, Xilinx
CSE140L: Components and Design Techniques for Digital Systems Lab Verilog HDL Tajana Simunic Rosing Source: Eric Crabill, Xilinx 1 More complex behavioral model module life (n0, n1, n2, n3, n4, n5, n6,
More informationChapter 9: Sequential Logic Modules
Chapter 9: Sequential Logic Modules Prof. Soo-Ik Chae Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 9-1 Objectives After completing this chapter, you will be able
More informationECE 2300 Digital Logic & Computer Organization. More Finite State Machines
ECE 2300 Digital Logic & Computer Organization Spring 2018 More Finite State Machines Lecture 9: 1 Announcements Prelab 3(B) due tomorrow Lab 4 to be released tonight You re not required to change partner(s)
More informationControl in Digital Systems
CONTROL CIRCUITS Control in Digital Systems Three primary components of digital systems Datapath (does the work) Control (manager, controller) Memory (storage) B. Baas 256 Control in Digital Systems Control
More informationLogic Synthesis. EECS150 - Digital Design Lecture 6 - Synthesis
Logic Synthesis Verilog and VHDL started out as simulation languages, but quickly people wrote programs to automatically convert Verilog code into low-level circuit descriptions (netlists). EECS150 - Digital
More informationEECS 270 Verilog Reference: Sequential Logic
1 Introduction EECS 270 Verilog Reference: Sequential Logic In the first few EECS 270 labs, your designs were based solely on combinational logic, which is logic that deps only on its current inputs. However,
More informationDate Performed: Marks Obtained: /10. Group Members (ID):. Experiment # 11. Introduction to Verilog II Sequential Circuits
Name: Instructor: Engr. Date Performed: Marks Obtained: /10 Group Members (ID):. Checked By: Date: Experiment # 11 Introduction to Verilog II Sequential Circuits OBJECTIVES: To understand the concepts
More informationVerilog for Synthesis Ing. Pullini Antonio
Verilog for Synthesis Ing. Pullini Antonio antonio.pullini@epfl.ch Outline Introduction to Verilog HDL Describing combinational logic Inference of basic combinational blocks Describing sequential circuits
More informationMealy and Moore examples
CSE 37 Spring 26 Introduction to igital esign ecture 2: uential ogic Technologies ast ecture Moore and Mealy Machines Today uential logic technologies Ving machine: Moore to synch. Mealy OPEN = creates
More informationEECS150 - Digital Design Lecture 10 Logic Synthesis
EECS150 - Digital Design Lecture 10 Logic Synthesis February 13, 2003 John Wawrzynek Spring 2003 EECS150 Lec8-synthesis Page 1 Logic Synthesis Verilog and VHDL started out as simulation languages, but
More informationEECS150 - Digital Design Lecture 10 Logic Synthesis
EECS150 - Digital Design Lecture 10 Logic Synthesis September 26, 2002 John Wawrzynek Fall 2002 EECS150 Lec10-synthesis Page 1 Logic Synthesis Verilog and VHDL stated out as simulation languages, but quickly
More informationEE 231 Fall EE 231 Homework 8 Due October 20, 2010
EE 231 Homework 8 Due October 20, 20 1. Consider the circuit below. It has three inputs (x and clock), and one output (z). At reset, the circuit starts with the outputs of all flip-flops at 0. x z J Q
More informationQuick Introduction to SystemVerilog: Sequental Logic
! Quick Introduction to SystemVerilog: Sequental Logic Lecture L3 8-545 Advanced Digital Design ECE Department Many elements Don Thomas, 24, used with permission with credit to G. Larson Today Quick synopsis
More informationDIGITAL SYSTEM DESIGN
DIGITAL SYSTEM DESIGN Prepared By: Engr. Yousaf Hameed Lab Engineer BASIC ELECTRICAL & DIGITAL SYSTEMS LAB DEPARTMENT OF ELECTRICAL ENGINEERING Digital System Design 1 Name: Registration No: Roll No: Semester:
More informationThe Verilog Language COMS W Prof. Stephen A. Edwards Fall 2002 Columbia University Department of Computer Science
The Verilog Language COMS W4995-02 Prof. Stephen A. Edwards Fall 2002 Columbia University Department of Computer Science The Verilog Language Originally a modeling language for a very efficient event-driven
More informationECE 551 Digital System Design and Synthesis. Instructor: Kewal K. Saluja. Midterm Exam
Last (family) name: First (given) name: Student I.D. #: Department of Electrical and Computer Engineering University of Wisconsin - Madison ECE 551 Digital System Design and Synthesis Instructor: Kewal
More informationFPGA for Software Engineers
FPGA for Software Engineers Course Description This course closes the gap between hardware and software engineers by providing the software engineer all the necessary FPGA concepts and terms. The course
More informationIn this lecture, we will go beyond the basic Verilog syntax and examine how flipflops and other clocked circuits are specified.
1 In this lecture, we will go beyond the basic Verilog syntax and examine how flipflops and other clocked circuits are specified. I will also introduce the idea of a testbench as part of a design specification.
More informationXilinx ASMBL Architecture
FPGA Structure Xilinx ASMBL Architecture Design Flow Synthesis: HDL to FPGA primitives Translate: FPGA Primitives to FPGA Slice components Map: Packing of Slice components into Slices, placement of Slices
More informationFinite State Machines
Finite State Machines Design methodology for sequential logic -- identify distinct states -- create state transition diagram -- choose state encoding -- write combinational Verilog for next-state logic
More informationDigital Circuit Design and Language. Datapath Design. Chang, Ik Joon Kyunghee University
Digital Circuit Design and Language Datapath Design Chang, Ik Joon Kyunghee University Typical Synchronous Design + Control Section : Finite State Machine + Data Section: Adder, Multiplier, Shift Register
More informationDigital Design with SystemVerilog
Digital Design with SystemVerilog Prof. Stephen A. Edwards Columbia University Spring 25 Synchronous Digital Design Combinational Logic Sequential Logic Summary of Modeling Styles Testbenches Why HDLs?
More informationModeling Sequential Circuits in Verilog
Modeling Sequential Circuits in Verilog COE 202 Digital Logic Design Dr. Muhamed Mudawar King Fahd University of Petroleum and Minerals Presentation Outline Modeling Latches and Flip-Flops Blocking versus
More informationLaboratory Exercise 3 Davide Rossi DEI University of Bologna AA
Laboratory Exercise 3 Davide Rossi DEI University of Bologna AA 2017-2018 Objectives Summary of finite state machines (Mealy, Moore) Description of FSMs in System Verilog Design of control blocks based
More information3. The high voltage level of a digital signal in positive logic is : a) 1 b) 0 c) either 1 or 0
1. The number of level in a digital signal is: a) one b) two c) four d) ten 2. A pure sine wave is : a) a digital signal b) analog signal c) can be digital or analog signal d) neither digital nor analog
More informationTopics. Midterm Finish Chapter 7
Lecture 9 Topics Midterm Finish Chapter 7 ROM (review) Memory device in which permanent binary information is stored. Example: 32 x 8 ROM Five input lines (2 5 = 32) 32 outputs, each representing a memory
More informationReadings: Storage unit. Can hold an n-bit value Composed of a group of n flip-flops. Each flip-flop stores 1 bit of information.
Registers Readings: 5.8-5.9.3 Storage unit. Can hold an n-bit value Composed of a group of n flip-flops Each flip-flop stores 1 bit of information ff ff ff ff 178 Controlled Register Reset Load Action
More informationFSM Components. FSM Description. HDL Coding Methods. Chapter 7: HDL Coding Techniques
FSM Components XST features: Specific inference capabilities for synchronous Finite State Machine (FSM) components. Built-in FSM encoding strategies to accommodate your optimization goals. You may also
More informationSequential Circuit Design: Principle
Sequential Circuit Design: Principle Chapter 8 1 Outline 1. Overview on sequential circuits 2. Synchronous circuits 3. Danger of synthesizing asynchronous circuit 4. Inference of basic memory elements
More informationChapter 9: Sequential Logic Modules
Chapter 9: Sequential Logic Modules Prof. Ming-Bo Lin Department of Electronic Engineering National Taiwan University of Science and Technology Digital System Designs and Practices Using Verilog HDL and
More informationVerilog Fundamentals. Shubham Singh. Junior Undergrad. Electrical Engineering
Verilog Fundamentals Shubham Singh Junior Undergrad. Electrical Engineering VERILOG FUNDAMENTALS HDLs HISTORY HOW FPGA & VERILOG ARE RELATED CODING IN VERILOG HDLs HISTORY HDL HARDWARE DESCRIPTION LANGUAGE
More informationSequential Logic Implementation. Mealy vs. Moore Machines. Specifying Outputs for a Mealy Machine. Specifying Outputs for a Moore Machine
uential Logic Implementation! Models for representing sequential circuits " bstraction of sequential elements " Finite state machines and their state diagrams " Inputs/ " Mealy, Moore, and synchronous
More informationIn this lecture, we will focus on two very important digital building blocks: counters which can either count events or keep time information, and
In this lecture, we will focus on two very important digital building blocks: counters which can either count events or keep time information, and shift registers, which is most useful in conversion between
More informationVHDL: RTL Synthesis Basics. 1 of 59
VHDL: RTL Synthesis Basics 1 of 59 Goals To learn the basics of RTL synthesis. To be able to synthesize a digital system, given its VHDL model. To be able to relate VHDL code to its synthesized output.
More informationIntroduction to Verilog HDL. Verilog 1
Introduction to HDL Hardware Description Language (HDL) High-Level Programming Language Special constructs to model microelectronic circuits Describe the operation of a circuit at various levels of abstraction
More informationVerilog introduction. Embedded and Ambient Systems Lab
Verilog introduction Embedded and Ambient Systems Lab Purpose of HDL languages Modeling hardware behavior Large part of these languages can only be used for simulation, not for hardware generation (synthesis)
More informationLast Lecture. Talked about combinational logic always statements. e.g., module ex2(input logic a, b, c, output logic f); logic t; // internal signal
Last Lecture Talked about combinational logic always statements. e.g., module ex2(input logic a, b, c, output logic f); logic t; // internal signal always_comb t = a & b; f = t c; should use = (called
More informationRipple Counters. Lecture 30 1
Ripple Counters A register that goes through a prescribed sequence of states upon the application of input pulses is called a counter. The input pulses may be clock pulses, or they may originate from some
More informationSynthesizable Verilog
Synthesizable Verilog Courtesy of Dr. Edwards@Columbia, and Dr. Franzon@NCSU http://csce.uark.edu +1 (479) 575-6043 yrpeng@uark.edu Design Methodology Structure and Function (Behavior) of a Design HDL
More informationRecommended Design Techniques for ECE241 Project Franjo Plavec Department of Electrical and Computer Engineering University of Toronto
Recommed Design Techniques for ECE241 Project Franjo Plavec Department of Electrical and Computer Engineering University of Toronto DISCLAIMER: The information contained in this document does NOT contain
More informationL5: Simple Sequential Circuits and Verilog
L5: Simple Sequential Circuits and Verilog Courtesy of Rex Min. Used with permission. 1 Key Points from L4 (Sequential Blocks) Classification: Latch: level sensitive (positive latch passes input to output
More informationVHDL for Synthesis. Course Description. Course Duration. Goals
VHDL for Synthesis Course Description This course provides all necessary theoretical and practical know how to write an efficient synthesizable HDL code through VHDL standard language. The course goes
More informationBulletproofing FSM Verification Automated Approach to Detect Corner Case Issues in an FSM Design
Bulletproofing FSM Verification Automated Approach to Detect Corner Case Issues in an FSM Design Lisa Piper Technical Marketing Real Intent Inc., Sunnyvale, CA Comprehensive verification of Finite State
More informationTopics. Midterm Finish Chapter 7
Lecture 9 Topics Midterm Finish Chapter 7 Xilinx FPGAs Chapter 7 Spartan 3E Architecture Source: Spartan-3E FPGA Family Datasheet CLB Configurable Logic Blocks Each CLB contains four slices Each slice
More informationFPGA Design Challenge :Techkriti 14 Digital Design using Verilog Part 1
FPGA Design Challenge :Techkriti 14 Digital Design using Verilog Part 1 Anurag Dwivedi Digital Design : Bottom Up Approach Basic Block - Gates Digital Design : Bottom Up Approach Gates -> Flip Flops Digital
More informationGraduate Institute of Electronics Engineering, NTU Design of Datapath Controllers
Design of Datapath Controllers Lecturer: Wein-Tsung Shen Date: 2005.04.01 ACCESS IC LAB Outline Sequential Circuit Model Finite State Machines Useful Modeling Techniques pp. 2 Model of Sequential Circuits
More information5.14 Algorithmic State Machine (ASM) Charts
5.4 Algorithmic State Machine (ASM) Charts An ASM chart is an alternative method for describing a state machine More directly shows the sequential steps of a state machine. Easier to understand input priority
More informationFederal Urdu University of Arts, Science and Technology, Islamabad VLSI SYSTEM DESIGN. Prepared By: Engr. Yousaf Hameed.
VLSI SYSTEM DESIGN Prepared By: Engr. Yousaf Hameed Lab Engineer BASIC ELECTRICAL & DIGITAL SYSTEMS LAB DEPARTMENT OF ELECTRICAL ENGINEERING VLSI System Design 1 LAB 01 Schematic Introduction to DSCH and
More informationELCT 501: Digital System Design
ELCT 501: Digital System Lecture 4: CAD tools (Continued) Dr. Mohamed Abd El Ghany, Basic VHDL Concept Via an Example Problem: write VHDL code for 1-bit adder 4-bit adder 2 1-bit adder Inputs: A (1 bit)
More informationGraphics: Alexandra Nolte, Gesine Marwedel, Universität Dortmund. RTL Synthesis
Graphics: Alexandra Nolte, Gesine Marwedel, 2003 Universität Dortmund RTL Synthesis Purpose of HDLs Purpose of Hardware Description Languages: Capture design in Register Transfer Language form i.e. All
More informationParallel versus serial execution
Parallel versus serial execution F assign statements are implicitly parallel Ì = means continuous assignment Ì Example assign E = A & D; assign A = B & C; Ì A and E change if B changes F always blocks
More informationSpeaker: Kayting Adviser: Prof. An-Yeu Wu Date: 2009/11/23
98-1 Under-Graduate Project Synthesis of Combinational Logic Speaker: Kayting Adviser: Prof. An-Yeu Wu Date: 2009/11/23 What is synthesis? Outline Behavior Description for Synthesis Write Efficient HDL
More informationSynthesis of Language Constructs. 5/10/04 & 5/13/04 Hardware Description Languages and Synthesis
Synthesis of Language Constructs 1 Nets Nets declared to be input or output ports are retained Internal nets may be eliminated due to logic optimization User may force a net to exist trireg, tri0, tri1
More informationSt.MARTIN S ENGINEERING COLLEGE Dhulapally, Secunderabad
St.MARTIN S ENGINEERING COLLEGE Dhulapally, Secunderabad-500 014 Subject: Digital Design Using Verilog Hdl Class : ECE-II Group A (Short Answer Questions) UNIT-I 1 Define verilog HDL? 2 List levels of
More informationECE 4514 Digital Design II. Spring Lecture 2: Hierarchical Design
ECE 4514 Digital Design II Spring 2007 Abstraction in Hardware Design Remember from last lecture that HDLs offer a textual description of a netlist. Through abstraction in the HDL, we can capture more
More informationRegisters and finite state machines
Registers and finite state machines DAPA E.T.S.I. Informática Universidad de Sevilla /22 Jorge Juan 2, 2, 22 You are free to copy, distribute and communicate this work publicly and
More informationFinite State Machines (FSM) Description in VHDL. Review and Synthesis
Finite State Machines (FSM) Description in VHDL Review and Synthesis FSM Review A sequential circuit that is implemented in a fixed number of possible states is called a Finite State Machine (FSM). Finite
More informationOUTLINE Introduction Power Components Dynamic Power Optimization Conclusions
OUTLINE Introduction Power Components Dynamic Power Optimization Conclusions 04/15/14 1 Introduction: Low Power Technology Process Hardware Architecture Software Multi VTH Low-power circuits Parallelism
More informationComputer Architecture: Part III. First Semester 2013 Department of Computer Science Faculty of Science Chiang Mai University
Computer Architecture: Part III First Semester 2013 Department of Computer Science Faculty of Science Chiang Mai University Outline Decoders Multiplexers Registers Shift Registers Binary Counters Memory
More informationEPC6055 Digital Integrated Circuits EXAM 1 Fall Semester 2013
EPC6055 Digital Integrated Circuits EXAM 1 Fall Semester 2013 Print Here Student ID Signature This is a closed book exam. The exam is to be completed in one-hundred ten (110) minutes. Don t use scratch
More informationDigital Design with FPGAs. By Neeraj Kulkarni
Digital Design with FPGAs By Neeraj Kulkarni Some Basic Electronics Basic Elements: Gates: And, Or, Nor, Nand, Xor.. Memory elements: Flip Flops, Registers.. Techniques to design a circuit using basic
More informationCSE140L: Components and Design Techniques for Digital Systems Lab. FSMs. Instructor: Mohsen Imani. Slides from Tajana Simunic Rosing
CSE4L: Components and Design Techniques for Digital Systems La FSMs Instructor: Mohsen Imani Slides from Tajana Simunic Rosing Source: Vahid, Katz Flip-flops Hardware Description Languages and Sequential
More informationECE 2300 Digital Logic & Computer Organization. More Sequential Logic Verilog
ECE 2300 Digital Logic & Computer Organization Spring 2018 More Sequential Logic Verilog Lecture 7: 1 Announcements HW3 will be posted tonight Prelim 1 Thursday March 1, in class Coverage: Lectures 1~7
More informationDigital Integrated Circuits
Digital Integrated Circuits Lecture 5 Jaeyong Chung System-on-Chips (SoC) Laboratory Incheon National University MULTIPLE initial/always In C (single-threaded), a single statement is being executed at
More information