Digital Logic Design. Final Examination

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1 The University of Toleo s8fs_il7.fm - EEC: igital Logic esign r. Anthony. Johnson tuent name igital Logic esign Final Examination Problems Points... 4 Total 6 Was the exam fair? yes no

2 The University of Toleo s8fs_il7.fm - EEC: igital Logic esign r. Anthony. Johnson tuent name Problem points Given is a logic (switching) function F in the ecimal list sum-of-minterms representation (-). F (A,B,C,) = Σ(, 4, 5, 8, ) + (A,B,C,) = Σ(, 7,, 5) (-) Problem statement On the example of the given logic function F emonstrate an ability to:. erive a Karnaugh map representation of the function F,. use the Karnaugh map metho to erive a minimal number of literals expression of F,. esign the two-level NAN-NAN implementation of the OP form of function F, an the two-level NOR-NOR implementation of the PO form of function F, as specifie uner.4 an.5 below. Hint # For full creit: all equations, all answers to questions, all circuit moels an other graphical representations are expecte to be entere into the space esignate for them; all shown numerical results must be precee by the symbolic an numeric expressions whose evaluation prouces these numerical results. Problem olution An explicit emonstration of unerstaning the following solution steps is expecte.. Prepare the Karnaugh map representation of the function F, an place a copy of it into each of the spaces reserve for Figures - an -. AB C AB C F = C (B + ) (A + B + ) (c) { A C F = B + B + A B C () Figure - Representation forms of the function F. an Karnaugh map of F.(c)Minimum number of literals PO representation of F.()Minimum number of literals OP representation of F.

3 The University of Toleo s8fs_il7.fm - EEC: igital Logic esign r. Anthony. Johnson tuent name. Apply the Karnaugh map minimization metho to erive the Minimum number of literals prouctof-sums (PO) representation of the function F. Enter the erive algebraic representation of F in the space reserve for Figure -(c).. Apply the Karnaugh map minimization metho to erive the Minimum number of literals sum-ofproucts (OP) representation of the function F. Enter the erive algebraic representation of F in the space reserve for Figure -()..4 In the space reserve for Figure -, prepare a logical circuit moel of the two-level NOR-NOR form of implementation of the erive minimum number of literals PO expression of the expression of the function F..5 In the space reserve for Figure -, prepare a logical circuit moel of the two-level NAN- NAN form of implementation of the erive minimum number of literals OP expression of the function F. C B B A B F A C B F Figure - Two-level implementation of the minimum number of literals expressions of the functions F. NOR-NOR implementation.nan-nan implementation.

4 The University of Toleo s8fs_il7.fm - 4 EEC: igital Logic esign r. Anthony. Johnson tuent name Problem points Figure. contains the following parts of the escription of a universal (biirectional) shift-register: a partial (incomplete) rawing of a logic circuit moel of a universal shift-register is shown in Figure., where positions of input terminals are not shown; one specific Function Table of a universal shift-register is shown in Figure.. O O O O RE RE RE RE CLK CLR s MUX 4: s MUX 4: s MUX 4: s MUX 4: s s s s I R I L I I I I Operation coe Register operation shift right no change parallel loa shift left ignal esignation O O o ignal escription erial output for shift left operation erial output for shift right operation (c) Figure. MUX-base implementation of a Universal shift register. Partial logic circuit moel of a universal shift register. Function table of the shift register, showing the operation coes to be implemente by the esign. (c)pace for writing in the answer to part.. Problem tatement Base on the given escription from parts an emonstrate an ability to:. complete the missing connections to the signal inputs of the multiplexers in the logical circuit moel of the universal shift-register in such a way that the complete circuit implements the functions specifie in the Function Table of Figure.;. recognize the serial output terminals for shift-left an shift-right operations.

5 The University of Toleo s8fs_il7.fm - 5 EEC: igital Logic esign r. Anthony. Johnson tuent name Hint # For full creit: all equations, all answers to questions, all circuit moels an other graphical representations are expecte to be entere into the space esignate for them; all shown numerical results must be precee by the symbolic an numeric expressions whose evaluation prouces the shown results. Problem olution For full creit, explicit emonstration of unerstaning the following solution steps is expecte. 8. Using the following esignations for the input signals to the shift register: - shift right operation: I R, - shift left operation: I L, - parallel loa operation: I o through I esign an enter in Figure. the necessary connections to make the complete logical circuit moel of Figure. an implementation of the universal shift register specifie by the function table shown in Figure... In the space reserve for Figure -(c), write the signal esignations from Figure. which represent the serial outputs of the register for shift left an shift right operations.

6 The University of Toleo s8fs_il7.fm - 6 EEC: igital Logic esign r. Anthony. Johnson tuent name Problem 4 points Given is the specification of a tate Machine (M): AM chart of the M is shown in Figure., M has one input signal, (c) M has one output signal: Z, () M s internal state memory ought to be built using ege-triggere JK-type flip-flops. Z= External Inputs I i / Next state logic I N s / Internal state memory + s / I Output logic O o / Outputs Z= Z= Clock Z= Figure. Mealy type tate Machine escription. The Mealy type M architecture. AM chart of a specific M for which the esign process is to be emonstrate. Problem tatement Base on the given verbal specification of the M, emonstrate an ability to:. compose the tate Transition Table implie by the given AM chart;. combine the information from the tate Transition Table an the JK-type Flip-Fop Excitation Table to prepare the tate Transition Excitation Table of the specifie M;. apply the Karnaugh Map simplification metho to erive the minimum number of literals flip-flop excitation functions of the internal state memory; 4. compose the next-state combinational circuit moel which implements the erive internalstate flip-flop transition excitation function(s). Hint # For full creit: all equations, all answers to questions, all circuit moels an other graphical representations are expecte to be entere into the space esignate for them; all shown numerical results must be precee by the symbolic an numeric expressions whose evaluation prouces the shown results.

7 The University of Toleo s8fs_il7.fm - 7 EEC: igital Logic esign r. Anthony. Johnson tuent name Problem olution For full creit, explicit emonstration of unerstaning the following solution steps is expecte.. Compose the state transition table of the M using the information from the AM chart of Figure.. how the compose state transition table in the space reserve for Figure. Z= Z= Z= Z= y y? / / / / / / / / Y Y /Z y Y J K y y Y J Z Y (c) K J K y y y y y y y y y y J = y K = J = y K = Z = y y () J - Kmap K - Kmap J - Kmap K - Kmap Z- Kmap Figure. esign process of the tate Machine. tate transition table of the M. JK-type flip-flop excitation table. (c)transition excitation table of the M. ()Karnaugh maps of the functions J, K, J, K an Z. (e)implifie expressions of logic functions J, K, J, K an Z. (e). In the space reserve for Figure. fill in the contents of the excitation table of JK-type flipflop.. Combining the information from the state transition table an the flip-flop excitation table compose the state transition excitation table of the M. how the compose table in the space reserve for Figure.(c).4 In the space reserve for Figure.() prepare the Karnaugh map representations of the flip-flop excitation functions foun in the state transition excitation table of the M..5 Using the constructe Karnaugh maps, erive the minimum number of literals expressions of flipflop excitation function(s), an enter the erive expressions in the space reserve for Figure.(e).

8 The University of Toleo s8fs_il7.fm - 8 EEC: igital Logic esign r. Anthony. Johnson tuent name.6 In the space reserve for Figure. prepare the logical circuit moel of the esigne implementation of tate Machine whose AM chart is shown in Figure.. y y J K J FF K C y y Z=y y J K J FF K C y y CLK Figure. Logical circuit moel of the tate Machine whose AM chart is shown in Figure..

Digital Logic Design. Final Examination

Digital Logic Design. Final Examination The University of Toleo Section s5fs_il7.fm - EECS: igital Logic esign r. nthony. Johnson Stuent name igital Logic esign Final Examination Problems Points... Total 5 Was the exam fair? yes no The University