COMPUTER ORGANIZATION AND DESIGN
|
|
- Horace Flynn
- 5 years ago
- Views:
Transcription
1 COMPUTER ORGANIZATION AND DESIGN The Hardware/Software Interface 5 th Edition Chapter 3 Arithmetic for Computers
2 Arithmetic for Computers Operations on integers Addition and subtraction Multiplication and division Dealing with overflow Floating-point real numbers Representation and operations 3.1 Introduction Chapter 3 Arithmetic for Computers 2
3 Integer Addition Example: Addition and Subtraction Overflow if result out of range Adding +ve and ve operands, no overflow Adding two +ve operands Overflow if result sign is 1 Adding two ve operands Overflow if result sign is 0 Chapter 3 Arithmetic for Computers 3
4 Integer Subtraction Add negation of second operand Example: 7 6 = 7 + ( 6) +7: : : Overflow if result out of range Subtracting two +ve or two ve operands, no overflow Subtracting +ve from ve operand Overflow if result sign is 0 Subtracting ve from +ve operand Overflow if result sign is 1 Chapter 3 Arithmetic for Computers 4
5 Dealing with Overflow Overflow occurs when the result of an operation cannot be represented in 32-bits, i.e., when the sign bit contains a value bit of the result and not the proper sign bit When adding operands with different signs or when subtracting operands with the same sign, overflow can never occur Operation Operand A Operand B Result indicating overflow A + B 0 0 < 0 A + B < 0 < 0 0 A - B 0 < 0 < 0 A - B < 0 0 0
6 Dealing with Overflow Overflow occurs when the result of an operation cannot be represented in 32-bits, i.e., when the sign bit contains a value bit of the result and not the proper sign bit When adding operands with different signs or when subtracting operands with the same sign, overflow can never occur Operation Operand A Operand B Result indicating overflow A + B 0 0 < 0 A + B < 0 < 0 0 A - B 0 < 0 < 0 A - B < MIPS signals overflow with an exception (aka interrupt) an unscheduled procedure call where the EPC contains the address of the instruction that caused the exception
7 2 s Comp - Detecting Overflow When adding two's complement numbers, overflow will only occur if the numbers being added have the same sign the sign of the result is different If we perform the addition a n-1 a n-2... a 1 a 0 +b n-1 b n-2 b 1 b s n-1 s n-2 s 1 s 0 Overflow can be detected as V an bn 1 sn 1 + an 1 bn 1 Overflow can also be detected as V = 1 sn 1 = c n cn 1 where c n-1 and c n are the carry in and carry out of the most significant bit
8 Unsigned - Detecting Overflow For unsigned numbers, overflow occurs if there is carry out of the most significant bit. V = c n For example, 1001 = = = 1 With the MIPS architecture Overflow exceptions occur for two s complement arithmetic add, sub, addi Overflow exceptions do not occur for unsigned arithmetic addu, subu, addiu
9 Dealing with Overflow Some languages (e.g., C) ignore overflow Use MIPS addu, addui, subu instructions Other languages (e.g., Ada, Fortran) require raising an exception Use MIPS add, addi, sub instructions On overflow, invoke exception handler Save PC in exception program counter (EPC) register Jump to predefined handler address mfc0 (move from coprocessor reg) instruction can retrieve EPC value, to return after corrective action Chapter 3 Arithmetic for Computers 8
10 MIPS Arithmetic Logic Unit (ALU) Must support the Arithmetic/Logic operations of the ISA add, addi, addiu, addu sub, subu mult, multu, div, divu sqrt and, andi, nor, or, ori, xor, xori beq, bne, slt, slti, sltiu, sltu A B zero ovf 1 ALU m (operation) result
11 MIPS Arithmetic Logic Unit (ALU) Must support the Arithmetic/Logic operations of the ISA add, addi, addiu, addu sub, subu mult, multu, div, divu sqrt and, andi, nor, or, ori, xor, xori beq, bne, slt, slti, sltiu, sltu With special handling for sign extend addi, addiu, slti, sltiu zero extend andi, ori, xori overflow detection add, addi, sub A B zero ovf 1 ALU m (operation) result
12 Arithmetic for Multimedia Graphics and media processing operates on vectors of 8-bit and 16-bit data Use 64-bit adder, with partitioned carry chain Operate on 8 8-bit, 4 16-bit, or 2 32-bit vectors SIMD (single-instruction, multiple-data) Saturating operations On overflow, result is largest representable value eg., clipping in audio, saturation in video Chapter 3 Arithmetic for Computers 10
13 Multiply Binary multiplication is just a bunch of right shifts and adds n multiplicand multiplier n partial product array double precision product 2n
14 Multiply Binary multiplication is just a bunch of right shifts and adds n multiplicand multiplier n partial product array can be formed in parallel and added in parallel for faster multiplication double precision product 2n
15 Multiplication Start with long-multiplication approach 3.3 Multiplication multiplicand multiplier product Length of product is the sum of operand lengths Chapter 3 Arithmetic for Computers 12
16 Multiplication Hardware Multiplicand is zero extended (unsigned mul) Initially 0 Chapter 3 Arithmetic for Computers 13
17 Multiplication Example (Version 1) Consider: , Product = bit multiplicand and multiplier are used in this example Multiplicand is zero extended because it is unsigned Iteration Multiplicand Multiplier Product 0 Initialize
18 Multiplication Example (Version 1) Consider: , Product = bit multiplicand and multiplier are used in this example Multiplicand is zero extended because it is unsigned Iteration Multiplicand Multiplier Product 0 Initialize Multiplier[0] = 1 => ADD
19 Multiplication Example (Version 1) Consider: , Product = bit multiplicand and multiplier are used in this example Multiplicand is zero extended because it is unsigned Iteration Multiplicand Multiplier Product 0 Initialize Multiplier[0] = 1 => ADD + SLL Multiplicand and SRL Multiplier
20 Multiplication Example (Version 1) Consider: , Product = bit multiplicand and multiplier are used in this example Multiplicand is zero extended because it is unsigned Iteration Multiplicand Multiplier Product 0 Initialize Multiplier[0] = 1 => ADD + SLL Multiplicand and SRL Multiplier Multiplier[0] = 0 => Do Nothing
21 Multiplication Example (Version 1) Consider: , Product = bit multiplicand and multiplier are used in this example Multiplicand is zero extended because it is unsigned Iteration Multiplicand Multiplier Product 0 Initialize Multiplier[0] = 1 => ADD + SLL Multiplicand and SRL Multiplier Multiplier[0] = 0 => Do Nothing SLL Multiplicand and SRL Multiplier
22 Multiplication Example (Version 1) Consider: , Product = bit multiplicand and multiplier are used in this example Multiplicand is zero extended because it is unsigned Iteration Multiplicand Multiplier Product 0 Initialize Multiplier[0] = 1 => ADD + SLL Multiplicand and SRL Multiplier Multiplier[0] = 0 => Do Nothing SLL Multiplicand and SRL Multiplier Multiplier[0] = 1 => ADD
23 Multiplication Example (Version 1) Consider: , Product = bit multiplicand and multiplier are used in this example Multiplicand is zero extended because it is unsigned Iteration Multiplicand Multiplier Product 0 Initialize Multiplier[0] = 1 => ADD + SLL Multiplicand and SRL Multiplier Multiplier[0] = 0 => Do Nothing SLL Multiplicand and SRL Multiplier Multiplier[0] = 1 => ADD + SLL Multiplicand and SRL Multiplier
24 Multiplication Example (Version 1) Consider: , Product = bit multiplicand and multiplier are used in this example Multiplicand is zero extended because it is unsigned Iteration Multiplicand Multiplier Product 0 Initialize Multiplier[0] = 1 => ADD + SLL Multiplicand and SRL Multiplier Multiplier[0] = 0 => Do Nothing SLL Multiplicand and SRL Multiplier Multiplier[0] = 1 => ADD + SLL Multiplicand and SRL Multiplier Multiplier[0] = 1 => ADD
25 Multiplication Example (Version 1) Consider: , Product = bit multiplicand and multiplier are used in this example Multiplicand is zero extended because it is unsigned Iteration Multiplicand Multiplier Product 0 Initialize Multiplier[0] = 1 => ADD + SLL Multiplicand and SRL Multiplier Multiplier[0] = 0 => Do Nothing SLL Multiplicand and SRL Multiplier Multiplier[0] = 1 => ADD + SLL Multiplicand and SRL Multiplier Multiplier[0] = 1 => ADD + SLL Multiplicand and SRL Multiplier
26 Observation on Version 1 of Multiply Hardware in version 1 can be optimized Rather than shifting the multiplicand to the left Instead, shift the product to the right Has same net effect and produces same results Reduce Hardware Multiplicand register can be reduced to 32 bits We can also reduce the adder size to 32 bits One cycle per iteration Shifting and addition can be done simultaneously
27 Version 2 of Multiplication Hardware Product = HI and LO registers, HI=0 Product is shifted right Reduced 32-bit Multiplicand & Adder Start Multiplicand = 1 Multiplier[0]? = 0 32 bits 32 bits 32-bit ALU add HI = HI + Multiplicand 33 bits carry 32 bits HI 64 bits LO shift right write shift right Control Shift Product = (HI,LO) Right 1 bit Shift Multiplier Right 1 bit 32 nd Repetition? No Multiplier 32 bits Multiplier[0] Done Yes
28 Refined Version of Multiply Hardware Eliminate Multiplier Register Initialize LO = Multiplier, HI=0 Product = HI and LO registers Start LO=Multiplier, HI=0 = 1 LO[0]? = 0 32 bits Multiplicand 32 bits HI = HI + Multiplicand 32-bit ALU 33 bits add Shift Product = (HI,LO) Right 1 bit carry 32 bits HI 64 bits LO shift right write LO[0] Control 32 nd Repetition? Done Yes No
29 Multiply Example (Refined Version) Consider: , Product = bit multiplicand and multiplier are used in this example 4-bit adder produces a 5-bit sum (with carry) Iteration Multiplicand Carry Product = HI, LO 0 Initialize (LO = Multiplier, HI=0)
30 Multiply Example (Refined Version) Consider: , Product = bit multiplicand and multiplier are used in this example 4-bit adder produces a 5-bit sum (with carry) Iteration Multiplicand Carry Product = HI, LO 0 Initialize (LO = Multiplier, HI=0) LO[0] = 1 => ADD
31 Multiply Example (Refined Version) Consider: , Product = bit multiplicand and multiplier are used in this example 4-bit adder produces a 5-bit sum (with carry) Iteration Multiplicand Carry Product = HI, LO 0 Initialize (LO = Multiplier, HI=0) LO[0] = 1 => ADD Shift Right Product = (HI, LO)
32 Multiply Example (Refined Version) Consider: , Product = bit multiplicand and multiplier are used in this example 4-bit adder produces a 5-bit sum (with carry) Iteration Multiplicand Carry Product = HI, LO 0 Initialize (LO = Multiplier, HI=0) LO[0] = 1 => ADD + Shift Right Product = (HI, LO) LO[0] = 0 => Do Nothing
33 Multiply Example (Refined Version) Consider: , Product = bit multiplicand and multiplier are used in this example 4-bit adder produces a 5-bit sum (with carry) Iteration Multiplicand Carry Product = HI, LO 0 Initialize (LO = Multiplier, HI=0) LO[0] = 1 => ADD + Shift Right Product = (HI, LO) LO[0] = 0 => Do Nothing Shift Right Product = (HI, LO)
34 Multiply Example (Refined Version) Consider: , Product = bit multiplicand and multiplier are used in this example 4-bit adder produces a 5-bit sum (with carry) Iteration Multiplicand Carry Product = HI, LO 0 Initialize (LO = Multiplier, HI=0) LO[0] = 1 => ADD + Shift Right Product = (HI, LO) LO[0] = 0 => Do Nothing Shift Right Product = (HI, LO) LO[0] = 1 => ADD
35 Multiply Example (Refined Version) Consider: , Product = bit multiplicand and multiplier are used in this example 4-bit adder produces a 5-bit sum (with carry) Iteration Multiplicand Carry Product = HI, LO 0 Initialize (LO = Multiplier, HI=0) LO[0] = 1 => ADD + Shift Right Product = (HI, LO) LO[0] = 0 => Do Nothing Shift Right Product = (HI, LO) LO[0] = 1 => ADD Shift Right Product = (HI, LO)
36 Multiply Example (Refined Version) Consider: , Product = bit multiplicand and multiplier are used in this example 4-bit adder produces a 5-bit sum (with carry) Iteration Multiplicand Carry Product = HI, LO 0 Initialize (LO = Multiplier, HI=0) LO[0] = 1 => ADD + Shift Right Product = (HI, LO) LO[0] = 0 => Do Nothing Shift Right Product = (HI, LO) LO[0] = 1 => ADD Shift Right Product = (HI, LO) LO[0] = 1 => ADD
37 Multiply Example (Refined Version) Consider: , Product = bit multiplicand and multiplier are used in this example 4-bit adder produces a 5-bit sum (with carry) Iteration Multiplicand Carry Product = HI, LO 0 Initialize (LO = Multiplier, HI=0) LO[0] = 1 => ADD + Shift Right Product = (HI, LO) LO[0] = 0 => Do Nothing Shift Right Product = (HI, LO) LO[0] = 1 => ADD Shift Right Product = (HI, LO) LO[0] = 1 => ADD Shift Right Product = (HI, LO)
38 Faster Multiplier Uses multiple adders Cost/performance tradeoff Can be pipelined Several multiplication performed in parallel Chapter 3 Arithmetic for Computers 20
39 MIPS Multiplication Two 32-bit registers for product HI: most-significant 32 bits LO: least-significant 32-bits Instructions mult rs, rt / multu rs, rt 64-bit product in HI/LO mfhi rd / mflo rd Move from HI/LO to rd Can test HI value to see if product overflows 32 bits mul rd, rs, rt Least-significant 32 bits of product > rd Chapter 3 Arithmetic for Computers 21
40 Unsigned Division (Paper & Pencil) 11 =
41 Division divisor quotient dividend remainder n-bit operands yield n-bit quotient and remainder Check for 0 divisor Long division approach If divisor dividend bits 1 bit in quotient, subtract Otherwise 0 bit in quotient, bring down next dividend bit Restoring division Do the subtract, and if remainder goes < 0, add divisor back Signed division Divide using absolute values Adjust sign of quotient and remainder as required 3.4 Division Chapter 3 Arithmetic for Computers 23
42 Division Hardware Initially divisor in left half Initially dividend Chapter 3 Arithmetic for Computers 24
43 Division Example Dividend = 0111 Divisor = 0010
44 Optimized Divider Uses two registers: HI and LO Initialize: HI = Remainder = 0 and LO = Dividend Shift (HI, LO) LEFT by 1 bit (also Shift Quotient LEFT) Shift the remainder and dividend registers together LEFT Compute: Difference = Remainder Divisor If (Difference 0) then Remainder = Difference Set Least significant Bit of Quotient Observation to Reduce Hardware: LO register can be also used to store the computed Quotient
45 Optimized Divider Initialize: HI = 0, LO = Dividend Results: HI = Remainder LO = Quotient Chapter 3 Arithmetic for Computers 27
46 Unsigned Integer Division Example Example: / (4-bit dividend & divisor) Result Quotient = and Remainder = bit registers for Remainder and Divisor (4-bit ALU) Iteration HI LO Divisor Difference 0 Initialize
47 Unsigned Integer Division Example Example: / (4-bit dividend & divisor) Result Quotient = and Remainder = bit registers for Remainder and Divisor (4-bit ALU) Iteration HI LO Divisor 0 Initialize : Shift Left, Diff = HI - Divisor Difference
48 Unsigned Integer Division Example Example: / (4-bit dividend & divisor) Result Quotient = and Remainder = bit registers for Remainder and Divisor (4-bit ALU) Iteration HI LO Divisor 0 Initialize : Shift Left, Diff = HI - Divisor : Diff < 0 => Do Nothing Difference
49 Unsigned Integer Division Example Example: / (4-bit dividend & divisor) Result Quotient = and Remainder = bit registers for Remainder and Divisor (4-bit ALU) Iteration HI LO Divisor 0 Initialize : Shift Left, Diff = HI - Divisor : Diff < 0 => Do Nothing 1: Shift Left, Diff = HI - Divisor Difference
50 Unsigned Integer Division Example Example: / (4-bit dividend & divisor) Result Quotient = and Remainder = bit registers for Remainder and Divisor (4-bit ALU) Iteration Initialize 2: Diff < 0 => Do Nothing : Rem = Diff, set lsb of LO HI LO Divisor : Shift Left, Diff = HI - Divisor : Shift Left, Diff = HI - Divisor Difference
51 Unsigned Integer Division Example Example: / (4-bit dividend & divisor) Result Quotient = and Remainder = bit registers for Remainder and Divisor (4-bit ALU) Iteration Initialize 2: Diff < 0 => Do Nothing : Rem = Diff, set lsb of LO HI LO Divisor : Shift Left, Diff = HI - Divisor : Shift Left, Diff = HI - Divisor : Shift Left, Diff = HI - Divisor Difference
52 Unsigned Integer Division Example Example: / (4-bit dividend & divisor) Result Quotient = and Remainder = bit registers for Remainder and Divisor (4-bit ALU) Iteration Initialize 2: Diff < 0 => Do Nothing 2: Rem = Diff, set lsb of LO : Diff < 0 => Do Nothing HI LO Divisor : Shift Left, Diff = HI - Divisor : Shift Left, Diff = HI - Divisor : Shift Left, Diff = HI - Divisor Difference
53 Unsigned Integer Division Example Example: / (4-bit dividend & divisor) Result Quotient = and Remainder = bit registers for Remainder and Divisor (4-bit ALU) Iteration Initialize 2: Diff < 0 => Do Nothing 2: Rem = Diff, set lsb of LO : Diff < 0 => Do Nothing HI LO Divisor : Shift Left, Diff = HI - Divisor : Shift Left, Diff = HI - Divisor : Shift Left, Diff = HI - Divisor : Shift Left, Diff = HI - Divisor Difference
54 Unsigned Integer Division Example Example: / (4-bit dividend & divisor) Result Quotient = and Remainder = bit registers for Remainder and Divisor (4-bit ALU) Iteration Initialize 2: Diff < 0 => Do Nothing 2: Rem = Diff, set lsb of LO : Diff < 0 => Do Nothing 2: Diff < 0 => Do Nothing HI LO Divisor : Shift Left, Diff = HI - Divisor : Shift Left, Diff = HI - Divisor : Shift Left, Diff = HI - Divisor : Shift Left, Diff = HI - Divisor Difference
55 Combined Multiplier and Divider One cycle per partial-remainder subtraction Looks a lot like a multiplier! Same hardware can be used for both Chapter 3 Arithmetic for Computers 29
56 Faster Division Can t use parallel hardware as in multiplier Subtraction is conditional on sign of remainder Faster dividers (e.g. SRT devision) generate multiple quotient bits per step Still require multiple steps Chapter 3 Arithmetic for Computers 30
57 MIPS Division Use HI/LO registers for result HI: 32-bit remainder LO: 32-bit quotient Instructions div rs, rt / divu rs, rt No overflow or divide-by-0 checking Software must perform checks if required Use mfhi, mflo to access result Chapter 3 Arithmetic for Computers 31
58 Representing Big (and Small) Numbers What if we want to encode approx. age of the earth? 4,600,000,000 or 4.6 x 10 9 weight in kg of one a.m.u. (atomic mass unit) or 1.6 x There is no way we can encode either of them in a 32-bit integer Floating point representation (-1) sign x F x 2 E Still have to fit everything in 32 bits (single precision)
59 Floating Point Representation for non-integral numbers Including very small and very large numbers Like scientific notation 3.5 Floating Point In binary normalized not normalized ±1.xxxxxxx 2 2 yyyy Types float and double in C Chapter 3 Arithmetic for Computers 33
60 Floating Point Standard Defined by IEEE Std Developed in response to divergence of representations Portability issues for scientific code Now almost universally adopted Two representations Single precision (32-bit) Double precision (64-bit) Chapter 3 Arithmetic for Computers 34
61 IEEE Floating-Point Format single: 8 bits double: 11 bits S Exponent single: 23 bits double: 52 bits Fraction x = ( 1) S (1+ Fraction) 2 (Exponent Bias) S: sign bit (0 non-negative, 1 negative) Normalized significand: 1.0 significand < 2.0 Always has a leading pre-binary-point 1 bit, so no need to represent it explicitly (hidden bit) Significand is Fraction with the 1. restored Exponent: excess representation: actual exponent + Bias Ensures exponent is unsigned Single: Bias = 127; Double: Bias = 1023 Chapter 3 Arithmetic for Computers 35
62 IEEE Floating-Point Format All 0 All 0 All 0 All 0 All 1 All 1 All 1 All 1 Chapter 3 Arithmetic for Computers 36
63 Single-Precision Range Exponents and reserved Smallest value Exponent: actual exponent = = 126 Fraction: significand = 1.0 ± ± Largest value exponent: actual exponent = = +127 Fraction: significand 2.0 ± ± Chapter 3 Arithmetic for Computers 37
64 Double-Precision Range Exponents and reserved Smallest value Exponent: actual exponent = = 1022 Fraction: significand = 1.0 ± ± Largest value Exponent: actual exponent = = Fraction: significand 2.0 ± ± Chapter 3 Arithmetic for Computers 38
65 Floating-Point Precision Relative precision all fraction bits are significant Single: approx 2 23 Equivalent to 23 log decimal digits of precision Double: approx 2 52 Equivalent to 52 log decimal digits of precision Chapter 3 Arithmetic for Computers 39
66 Floating-Point Example Represent = ( 1) S = 1 Fraction = Exponent = 1 + Bias Single: = 126 = Double: = 1022 = Single: Double: Chapter 3 Arithmetic for Computers 40
67 Floating-Point Example What number is represented by the singleprecision float S = 1 Fraction = Exponent = = 129 x = ( 1) 1 ( ) 2 ( ) = ( 1) = 5.0 Chapter 3 Arithmetic for Computers 41
68 Representable FP Numbers Negative numbers Positive numbers max FLP min min + FLP max ± Sparser Denser Denser Sparser O verflow region Underflow regions O verflow region Midway example Underflow example Typical example O verflow example Chapter 3 Arithmetic for Computers 42
69 Zero Biased exponent=0 Fraction = 0 Hidden bit = 0. Two representations for 0 (single precision) x = ( 1) 0x x S (0 + 0) 2 Bias = ± 0.0 Chapter 3 Arithmetic for Computers 43
70 Denormal Numbers Exponent = hidden bit is 0 x = ( 1) S (0 + Fraction) 2 ( Bias 1) Smaller than normal numbers allow for gradual underflow, with diminishing precision Chapter 3 Arithmetic for Computers 44
71 Denormalized Example Find the decimal equivalent of IEEE 754 number Determine the sign: 0, the number is positive Calculate the exponent exponent of all 0s means the number is denormalized exponent is therefore -126 Convert the significand to decimal remember to add the implicit bit (this is 0. because the number is denormalized) ( ) 2 = ( ) = x Chapter 3 Arithmetic for Computers 45
72 Infinities and NaNs Exponent = , Fraction = ±Infinity Can be used in subsequent calculations, avoiding need for overflow check Exponent = , Fraction Not-a-Number (NaN) Indicates illegal or undefined result e.g., 0.0 / 0.0 Can be used in subsequent calculations Chapter 3 Arithmetic for Computers 46
73 NaNs 1. Operations with at least one NaN operand 2. Indeterminate forms divisions 0/0 and ± /± multiplications 0 ± and ± 0 additions + ( ), ( ) + and equivalent subtractions 3. Real operations with complex results square root of a negative number. logarithm of a negative number inverse sine or cosine of a number that is less than 1 or greater than +1. Chapter 3 Arithmetic for Computers 47
74 Floating-Point Addition Consider a 4-digit decimal example Align decimal points Shift number with smaller exponent Add significands = Normalize result & check for over/underflow Round and renormalize if necessary Chapter 3 Arithmetic for Computers 48
75 Floating-Point Addition Now consider a 4-digit binary example ( ) 1. Align binary points Shift number with smaller exponent Add significands = Normalize result & check for over/underflow , with no over/underflow 4. Round and renormalize if necessary (no change) = Chapter 3 Arithmetic for Computers 49
76 Floating Point Addition Example Consider adding: (1.111) (1.011) For simplicity, we assume 4 bits of precision (or 3 bits of fraction)
77 Floating Point Addition Example Consider adding: (1.111) (1.011) For simplicity, we assume 4 bits of precision (or 3 bits of fraction) Exponents are not equal
78 Floating Point Addition Example Consider adding: (1.111) (1.011) For simplicity, we assume 4 bits of precision (or 3 bits of fraction) Exponents are not equal Shift the significand of the lesser exponent right until its exponent matches the larger number
79 Floating Point Addition Example Consider adding: (1.111) (1.011) For simplicity, we assume 4 bits of precision (or 3 bits of fraction) Exponents are not equal Shift the significand of the lesser exponent right until its exponent matches the larger number (1.011) = (0.1011) = ( ) 2 2 1
80 Floating Point Addition Example Consider adding: (1.111) (1.011) For simplicity, we assume 4 bits of precision (or 3 bits of fraction) Exponents are not equal Shift the significand of the lesser exponent right until its exponent matches the larger number (1.011) = (0.1011) = ( ) Difference between the two exponents = 1 ( 3) = 2
81 Floating Point Addition Example Consider adding: (1.111) (1.011) For simplicity, we assume 4 bits of precision (or 3 bits of fraction) Exponents are not equal Shift the significand of the lesser exponent right until its exponent matches the larger number (1.011) = (0.1011) = ( ) Difference between the two exponents = 1 ( 3) = 2 So, shift right by 2 bits
82 Floating Point Addition Example Consider adding: (1.111) (1.011) For simplicity, we assume 4 bits of precision (or 3 bits of fraction) Exponents are not equal Shift the significand of the lesser exponent right until its exponent matches the larger number (1.011) = (0.1011) = ( ) Difference between the two exponents = 1 ( 3) = 2 So, shift right by 2 bits Now, add the significands: Carry
83 Addition Example cont d So, (1.111) (1.011) = ( ) 2 2 1
84 Addition Example cont d So, (1.111) (1.011) = ( ) However, result ( ) is NOT normalized
85 Addition Example cont d So, (1.111) (1.011) = ( ) However, result ( ) is NOT normalized Normalize result: ( ) = ( ) 2 2 0
86 Addition Example cont d So, (1.111) (1.011) = ( ) However, result ( ) is NOT normalized Normalize result: ( ) = ( ) In this example, we have a carry So, shift right by 1 bit and increment the exponent
87 Addition Example cont d So, (1.111) (1.011) = ( ) However, result ( ) is NOT normalized Normalize result: ( ) = ( ) In this example, we have a carry So, shift right by 1 bit and increment the exponent Round the significand to fit in appropriate number of bits We assumed 4 bits of precision or 3 bits of fraction
88 Addition Example cont d So, (1.111) (1.011) = ( ) However, result ( ) is NOT normalized Normalize result: ( ) = ( ) In this example, we have a carry So, shift right by 1 bit and increment the exponent Round the significand to fit in appropriate number of bits We assumed 4 bits of precision or 3 bits of fraction Round to nearest: ( ) 2 (1.001)
89 Addition Example cont d So, (1.111) (1.011) = ( ) However, result ( ) is NOT normalized Normalize result: ( ) = ( ) In this example, we have a carry So, shift right by 1 bit and increment the exponent Round the significand to fit in appropriate number of bits We assumed 4 bits of precision or 3 bits of fraction Round to nearest: ( ) 2 (1.001) 2 Renormalize if rounding generates a carry
90 Addition Example cont d So, (1.111) (1.011) = ( ) However, result ( ) is NOT normalized Normalize result: ( ) = ( ) In this example, we have a carry So, shift right by 1 bit and increment the exponent Round the significand to fit in appropriate number of bits We assumed 4 bits of precision or 3 bits of fraction Round to nearest: ( ) 2 (1.001) 2 Renormalize if rounding generates a carry Detect overflow / underflow If exponent becomes too large (overflow) or too small (underflow) Represent overflow/underflow accordingly
91 Floating Point Subtraction Example Consider: (1.000) (1.000) We assume again: 4 bits of precision (or 3 bits of fraction)
92 Floating Point Subtraction Example Consider: (1.000) (1.000) We assume again: 4 bits of precision (or 3 bits of fraction) Shift right significand of the lesser exponent
93 Floating Point Subtraction Example Consider: (1.000) (1.000) We assume again: 4 bits of precision (or 3 bits of fraction) Shift right significand of the lesser exponent Difference between the two exponents = 2 ( 3) = 5
94 Floating Point Subtraction Example Consider: (1.000) (1.000) We assume again: 4 bits of precision (or 3 bits of fraction) Shift right significand of the lesser exponent Difference between the two exponents = 2 ( 3) = 5 Shift right by 5 bits: (1.000) = ( ) 2 2 2
95 Floating Point Subtraction Example Consider: (1.000) (1.000) We assume again: 4 bits of precision (or 3 bits of fraction) Shift right significand of the lesser exponent Difference between the two exponents = 2 ( 3) = 5 Shift right by 5 bits: (1.000) = ( ) Convert subtraction into addition to 2's complement
96 Floating Point Subtraction Example Consider: (1.000) (1.000) We assume again: 4 bits of precision (or 3 bits of fraction) Shift right significand of the lesser exponent Difference between the two exponents = 2 ( 3) = 5 Shift right by 5 bits: (1.000) = ( ) Convert subtraction into addition to 2's complement Sign
97 Floating Point Subtraction Example Consider: (1.000) (1.000) We assume again: 4 bits of precision (or 3 bits of fraction) Shift right significand of the lesser exponent Difference between the two exponents = 2 ( 3) = 5 Shift right by 5 bits: (1.000) = ( ) Convert subtraction into addition to 2's complement Sign 2 s Complement
98 Floating Point Subtraction Example Consider: (1.000) (1.000) We assume again: 4 bits of precision (or 3 bits of fraction) Shift right significand of the lesser exponent Difference between the two exponents = 2 ( 3) = 5 Shift right by 5 bits: (1.000) = ( ) Convert subtraction into addition to 2's complement Sign 2 s Complement
99 Floating Point Subtraction Example Consider: (1.000) (1.000) We assume again: 4 bits of precision (or 3 bits of fraction) Shift right significand of the lesser exponent Difference between the two exponents = 2 ( 3) = 5 Shift right by 5 bits: (1.000) = ( ) Convert subtraction into addition to 2's complement Sign 2 s Complement Since result is negative, convert result from 2's complement to sign-magnitude
100 Floating Point Subtraction Example Consider: (1.000) (1.000) We assume again: 4 bits of precision (or 3 bits of fraction) Shift right significand of the lesser exponent Difference between the two exponents = 2 ( 3) = 5 Shift right by 5 bits: (1.000) = ( ) Convert subtraction into addition to 2's complement Sign 2 s Complement Since result is negative, convert result from 2's complement to sign-magnitude 2 s Complement
101 Subtraction Example cont d So, (1.000) (1.000) =
102 Subtraction Example cont d So, (1.000) (1.000) = Normalize result: =
103 Subtraction Example cont d So, (1.000) (1.000) = Normalize result: = Round the significand to fit in appropriate number of bits We assumed 4 bits of precision or 3 bits of fraction
104 Subtraction Example cont d So, (1.000) (1.000) = Normalize result: = Round the significand to fit in appropriate number of bits We assumed 4 bits of precision or 3 bits of fraction Round to nearest: (1.1111) 2 (10.000)
105 Subtraction Example cont d So, (1.000) (1.000) = Normalize result: = Round the significand to fit in appropriate number of bits We assumed 4 bits of precision or 3 bits of fraction Round to nearest: (1.1111) 2 (10.000) 2 Renormalize: rounding generated a carry =
106 Subtraction Example cont d So, (1.000) (1.000) = Normalize result: = Round the significand to fit in appropriate number of bits We assumed 4 bits of precision or 3 bits of fraction Round to nearest: (1.1111) 2 (10.000) 2 Renormalize: rounding generated a carry = Result would have been accurate if more fraction bits are used
107 Floating Point Subtraction Example Consider: (1.000) (1.100) We assume again: 4 bits of precision (or 3 bits of fraction)
108 Floating Point Subtraction Example Consider: (1.000) (1.100) We assume again: 4 bits of precision (or 3 bits of fraction) Shift right significand of the lesser exponent
109 Floating Point Subtraction Example Consider: (1.000) (1.100) We assume again: 4 bits of precision (or 3 bits of fraction) Shift right significand of the lesser exponent Difference between the two exponents = -3 ( 4) = 1
110 Floating Point Subtraction Example Consider: (1.000) (1.100) We assume again: 4 bits of precision (or 3 bits of fraction) Shift right significand of the lesser exponent Difference between the two exponents = -3 ( 4) = 1 Shift right by 1 bits: (1.100) = (0.1100) 2 2-3
111 Floating Point Subtraction Example Consider: (1.000) (1.100) We assume again: 4 bits of precision (or 3 bits of fraction) Shift right significand of the lesser exponent Difference between the two exponents = -3 ( 4) = 1 Shift right by 1 bits: (1.100) = (0.1100) Convert subtraction into addition to 2's complement
112 Floating Point Subtraction Example Consider: (1.000) (1.100) We assume again: 4 bits of precision (or 3 bits of fraction) Shift right significand of the lesser exponent Difference between the two exponents = -3 ( 4) = 1 Shift right by 1 bits: (1.100) = (0.1100) Convert subtraction into addition to 2's complement Sign
113 Floating Point Subtraction Example Consider: (1.000) (1.100) We assume again: 4 bits of precision (or 3 bits of fraction) Shift right significand of the lesser exponent Difference between the two exponents = -3 ( 4) = 1 Shift right by 1 bits: (1.100) = (0.1100) Convert subtraction into addition to 2's complement Sign 2 s Complement
114 Floating Point Subtraction Example Consider: (1.000) (1.100) We assume again: 4 bits of precision (or 3 bits of fraction) Shift right significand of the lesser exponent Difference between the two exponents = -3 ( 4) = 1 Shift right by 1 bits: (1.100) = (0.1100) Convert subtraction into addition to 2's complement Sign 2 s Complement
115 Subtraction Example cont d So, (1.000) (1.100) =
116 Subtraction Example cont d So, (1.000) (1.100) = Normalize result: =
117 Subtraction Example cont d So, (1.000) (1.100) = Normalize result: = For subtraction, we can have leading zeros
118 Subtraction Example cont d So, (1.000) (1.100) = Normalize result: = For subtraction, we can have leading zeros Round the significand to fit in appropriate number of bits We assumed 4 bits of precision or 3 bits of fraction Answer:
119 FP Adder Hardware Much more complex than integer adder Doing it in one clock cycle would take too long Much longer than integer operations Slower clock would penalize all instructions FP adder usually takes several cycles Can be pipelined Chapter 3 Arithmetic for Computers 57
120 FP Adder Hardware Step 1 Step 2 Step 3 Step 4 Chapter 3 Arithmetic for Computers 58
121 FP Adder Hardware Chapter 3 Arithmetic for Computers 59
122 Floating-Point Multiplication Consider a 4-digit decimal example Add exponents For biased exponents, subtract bias from sum New exponent = = 5 2. Multiply significands = Normalize result & check for over/underflow Round and renormalize if necessary Determine sign of result from signs of operands Chapter 3 Arithmetic for Computers 61
123 Floating-Point Multiplication Now consider a 4-digit binary example ( ) 1. Add exponents Unbiased: = 3 Biased: ( ) + ( ) = = Multiply significands = Normalize result & check for over/underflow (no change) with no over/underflow 4. Round and renormalize if necessary (no change) 5. Determine sign: +ve ve ve = Chapter 3 Arithmetic for Computers 62
124 FP Arithmetic Hardware FP multiplier is of similar complexity to FP adder But uses a multiplier for significands instead of an adder FP arithmetic hardware usually does Addition, subtraction, multiplication, division, reciprocal, square-root FP integer conversion Operations usually takes several cycles Can be pipelined Chapter 3 Arithmetic for Computers 63
125 FP Instructions in MIPS FP hardware is coprocessor 1 Adjunct processor that extends the ISA Separate FP registers 32 single-precision: $f0, $f1, $f31 Paired for double-precision: $f0/$f1, $f2/$f3, Release 2 of MIPs ISA supports bit FP reg s FP instructions operate only on FP registers Programs generally don t do integer ops on FP data, or vice versa More registers with minimal code-size impact FP load and store instructions lwc1, ldc1, swc1, sdc1 e.g., ldc1 $f8, 32($sp) Chapter 3 Arithmetic for Computers 65
126 FP Instructions in MIPS Single-precision arithmetic add.s, sub.s, mul.s, div.s add.s $f0, $f1, $f6 #$f0 = $f1 + $f6 Double-precision arithmetic add.d, sub.d, mul.d, div.d add.d $f0, $f2, $f6 #$f0:$f1 = $f2:$f3 + $f6:$f7 mul.d $f4, $f4, $f6 Single- and double-precision comparison c.xx.s, c.xx.d (xx is eq, lt, le, ) Sets or clears FP condition-code bit (0 to 7) c.lt.s $f3, $f4 #if($f3 < $f4) cond=1; else cond=0 Branch on FP condition code true or false bc1t, bc1f bc1t TargetLabel #if(cond==1) go to TargetLabel Chapter 3 Arithmetic for Computers 66
127 FP Example: F to C C code: float f2c (float fahr) { return ((5.0/9.0)*(fahr )); } fahr in $f12, result in $f0, literals in global memory space Compiled MIPS code: f2c: lwc1 $f16, const5($gp) lwc1 $f18, const9($gp) div.s $f16, $f16, $f18 lwc1 $f18, const32($gp) sub.s $f18, $f12, $f18 mul.s $f0, $f16, $f18 jr $ra Chapter 3 Arithmetic for Computers 67
128 Accurate Arithmetic IEEE Std 754 specifies additional rounding control Extra bits of precision (guard, round, sticky) Choice of rounding modes Allows programmer to fine-tune numerical behavior of a computation Not all FP units implement all options Most programming languages and FP libraries just use defaults Trade-off between hardware complexity, performance, and market requirements Chapter 3 Arithmetic for Computers 71
129 Support for Accurate Arithmetic IEEE 754 FP rounding modes Always round up (toward + ) Always round down (toward - ) Truncate (toward zero) Round to nearest even (RTNE)
130 Support for Accurate Arithmetic IEEE 754 FP rounding modes Always round up (toward + ) Always round down (toward - ) Truncate (toward zero) Round to nearest even (RTNE) Rounding (except for truncation) requires the hardware to include extra F bits during calculations Guard bit used to provide one F bit when shifting left to normalize a result (e.g., when normalizing F after division or subtraction) Round bit used to improve rounding accuracy Sticky bit used to support Round to nearest even; is set to a 1 whenever a 1 bit shifts (right) through it (e.g., when aligning F during addition/subtraction) sticky F = 1. xxxxxxxxxxxxxxxxxxxxxxx G R S OR of the discarded bits
131 Rounding Examples Number To + To To Zero Chapter 3 Arithmetic for Computers 73
132 RTNE Examples GRS - Action (after first normalization if required) 0xx - round down = do nothing (x means any bit value, 0 or 1) this is a tie: round up if the bit just before G is 1, else round down = do nothing round up (increment by 1) round up (increment by 1) round up (increment by 1) Sig GRS Increment? Rounded N N N Y Y Y Chapter 3 Arithmetic for Computers 74
133 Guard Bit Guard bit: guards against loss of a significant bit Only one guard bit is needed to maintain accuracy of result Shifted left (if needed) during normalization as last fraction bit
134 Guard Bit Guard bit: guards against loss of a significant bit Only one guard bit is needed to maintain accuracy of result Shifted left (if needed) during normalization as last fraction bit Example on the need of a guard bit:
135 Guard Bit Guard bit: guards against loss of a significant bit Only one guard bit is needed to maintain accuracy of result Shifted left (if needed) during normalization as last fraction bit Example on the need of a guard bit: (subtraction)
136 Guard Bit Guard bit: guards against loss of a significant bit Only one guard bit is needed to maintain accuracy of result Shifted left (if needed) during normalization as last fraction bit Example on the need of a guard bit: (subtraction) (shift right 7 bits)
137 Guard Bit Guard bit: guards against loss of a significant bit Only one guard bit is needed to maintain accuracy of result Shifted left (if needed) during normalization as last fraction bit Example on the need of a guard bit: (subtraction) (shift right 7 bits) (2's complement)
138 Guard Bit Guard bit: guards against loss of a significant bit Only one guard bit is needed to maintain accuracy of result Shifted left (if needed) during normalization as last fraction bit Example on the need of a guard bit: (subtraction) (shift right 7 bits) Guard bit do not discard (2's complement)
139 Guard Bit Guard bit: guards against loss of a significant bit Only one guard bit is needed to maintain accuracy of result Shifted left (if needed) during normalization as last fraction bit Example on the need of a guard bit: (subtraction) (shift right 7 bits) Guard bit do not discard (2's complement) (add significands)
140 Guard Bit Guard bit: guards against loss of a significant bit Only one guard bit is needed to maintain accuracy of result Shifted left (if needed) during normalization as last fraction bit Example on the need of a guard bit: (subtraction) (shift right 7 bits) Guard bit do not discard (2's complement) (add significands) (normalized)
141 Guard Bit Guard bit: guards against loss of a significant bit Only one guard bit is needed to maintain accuracy of result Shifted left (if needed) during normalization as last fraction bit Example on the need of a guard bit: (subtraction) (shift right 7 bits) Guard bit do not discard (2's complement) (add significands) (normalized)
142 Round and Sticky Bits Two extra bits are needed for rounding Rounding performed after normalizing a result significand Round bit: appears after the guard bit Sticky bit: appears after the round bit (OR of all additional bits)
143 Round and Sticky Bits Two extra bits are needed for rounding Rounding performed after normalizing a result significand Round bit: appears after the guard bit Sticky bit: appears after the round bit (OR of all additional bits) Consider the same example of previous slide:
144 Round and Sticky Bits Two extra bits are needed for rounding Rounding performed after normalizing a result significand Round bit: appears after the guard bit Sticky bit: appears after the round bit (OR of all additional bits) Consider the same example of previous slide: (2's complement)
145 Round and Sticky Bits Two extra bits are needed for rounding Rounding performed after normalizing a result significand Round bit: appears after the guard bit Sticky bit: appears after the round bit (OR of all additional bits) Consider the same example of previous slide: (2's complement) (sum)
Chapter 3. Arithmetic Text: P&H rev
Chapter 3 Arithmetic Text: P&H rev3.29.16 Arithmetic for Computers Operations on integers Addition and subtraction Multiplication and division Dealing with overflow Floating-point real numbers Representation
More informationThomas Polzer Institut für Technische Informatik
Thomas Polzer tpolzer@ecs.tuwien.ac.at Institut für Technische Informatik Operations on integers Addition and subtraction Multiplication and division Dealing with overflow Floating-point real numbers VO
More informationArithmetic for Computers. Hwansoo Han
Arithmetic for Computers Hwansoo Han Arithmetic for Computers Operations on integers Addition and subtraction Multiplication and division Dealing with overflow Floating-point real numbers Representation
More informationFloating Point Arithmetic
Floating Point Arithmetic Jinkyu Jeong (jinkyu@skku.edu) Computer Systems Laboratory Sungkyunkwan University http://csl.skku.edu EEE3050: Theory on Computer Architectures, Spring 2017, Jinkyu Jeong (jinkyu@skku.edu)
More informationFloating Point Arithmetic. Jin-Soo Kim Computer Systems Laboratory Sungkyunkwan University
Floating Point Arithmetic Jin-Soo Kim (jinsookim@skku.edu) Computer Systems Laboratory Sungkyunkwan University http://csl.skku.edu Floating Point (1) Representation for non-integral numbers Including very
More informationTDT4255 Computer Design. Lecture 4. Magnus Jahre
1 TDT4255 Computer Design Lecture 4 Magnus Jahre 2 Chapter 3 Computer Arithmetic ti Acknowledgement: Slides are adapted from Morgan Kaufmann companion material 3 Arithmetic for Computers Operations on
More informationComputer Organization and Structure. Bing-Yu Chen National Taiwan University
Computer Organization and Structure Bing-Yu Chen National Taiwan University Arithmetic for Computers Addition and Subtraction Gate Logic and K-Map Method Constructing a Basic ALU Arithmetic Logic Unit
More informationChapter 3. Arithmetic for Computers
Chapter 3 Arithmetic for Computers Arithmetic for Computers Operations on integers Addition and subtraction Multiplication and division Dealing with overflow Floating-point real numbers Representation
More informationComputer Architecture and IC Design Lab. Chapter 3 Part 2 Arithmetic for Computers Floating Point
Chapter 3 Part 2 Arithmetic for Computers Floating Point Floating Point Representation for non integral numbers Including very small and very large numbers 4,600,000,000 or 4.6 x 10 9 0.0000000000000000000000000166
More informationChapter 3. Arithmetic for Computers
Chapter 3 Arithmetic for Computers Arithmetic for Computers Operations on integers Addition and subtraction Multiplication and division Dealing with overflow Floating-point real numbers Representation
More informationChapter 3. Arithmetic for Computers
Chapter 3 Arithmetic for Computers Arithmetic for Computers Operations on integers Addition and subtraction Multiplication and division Dealing with overflow Floating-point real numbers Representation
More informationComputer Architecture. Chapter 3: Arithmetic for Computers
182.092 Computer Architecture Chapter 3: Arithmetic for Computers Adapted from Computer Organization and Design, 4 th Edition, Patterson & Hennessy, 2008, Morgan Kaufmann Publishers and Mary Jane Irwin
More information5DV118 Computer Organization and Architecture Umeå University Department of Computing Science Stephen J. Hegner. Topic 3: Arithmetic
5DV118 Computer Organization and Architecture Umeå University Department of Computing Science Stephen J. Hegner Topic 3: Arithmetic These slides are mostly taken verbatim, or with minor changes, from those
More informationReview: MIPS Organization
1 MIPS Arithmetic Review: MIPS Organization Processor Memory src1 addr 5 src2 addr 5 dst addr 5 write data Register File registers ($zero - $ra) bits src1 data src2 data read/write addr 1 1100 2 30 words
More informationWritten Homework 3. Floating-Point Example (1/2)
Written Homework 3 Assigned on Tuesday, Feb 19 Due Time: 11:59pm, Feb 26 on Tuesday Problems: 3.22, 3.23, 3.24, 3.41, 3.43 Note: You have 1 week to work on homework 3. 3 Floating-Point Example (1/2) Q:
More informationChapter 3 Arithmetic for Computers (Part 2)
Department of Electr rical Eng ineering, Chapter 3 Arithmetic for Computers (Part 2) 王振傑 (Chen-Chieh Wang) ccwang@mail.ee.ncku.edu.tw ncku edu Depar rtment of Electr rical Eng ineering, Feng-Chia Unive
More informationMIPS Integer ALU Requirements
MIPS Integer ALU Requirements Add, AddU, Sub, SubU, AddI, AddIU: 2 s complement adder/sub with overflow detection. And, Or, Andi, Ori, Xor, Xori, Nor: Logical AND, logical OR, XOR, nor. SLTI, SLTIU (set
More informationCSCI 402: Computer Architectures. Arithmetic for Computers (4) Fengguang Song Department of Computer & Information Science IUPUI.
CSCI 402: Computer Architectures Arithmetic for Computers (4) Fengguang Song Department of Computer & Information Science IUPUI Homework 4 Assigned on Feb 22, Thursday Due Time: 11:59pm, March 5 on Monday
More informationCOMPUTER ORGANIZATION AND DESIGN. 5 th Edition. The Hardware/Software Interface. Chapter 3. Arithmetic for Computers
COMPUTER ORGANIZATION AND DESIGN The Hardware/Software Interface 5 th Edition Chapter 3 Arithmetic for Computers Boolean Algebra Boolean algebra is the basic math used in digital circuits and computers.
More informationBoolean Algebra. Chapter 3. Boolean Algebra. Chapter 3 Arithmetic for Computers 1. Fundamental Boolean Operations. Arithmetic for Computers
COMPUTER ORGANIZATION AND DESIGN The Hardware/Software Interface 5 th Edition COMPUTER ORGANIZATION AND DESIGN The Hardware/Software Interface 5 th Edition Chapter 3 Arithmetic for Computers Arithmetic
More informationInteger Arithmetic. Jinkyu Jeong Computer Systems Laboratory Sungkyunkwan University
Integer Arithmetic Jinkyu Jeong (jinkyu@skku.edu) Computer Systems Laboratory Sungkyunkwan University http://csl.skku.edu EEE3050: Theory on Computer Architectures, Spring 2017, Jinkyu Jeong (jinkyu@skku.edu)
More informationArithmetic for Computers
MIPS Arithmetic Instructions Cptr280 Dr Curtis Nelson Arithmetic for Computers Operations on integers Addition and subtraction; Multiplication and division; Dealing with overflow; Signed vs. unsigned numbers.
More informationDivide: Paper & Pencil
Divide: Paper & Pencil 1001 Quotient Divisor 1000 1001010 Dividend -1000 10 101 1010 1000 10 Remainder See how big a number can be subtracted, creating quotient bit on each step Binary => 1 * divisor or
More informationChapter 3 Arithmetic for Computers
Chapter 3 Arithmetic for Computers 1 Outline Signed and unsigned numbers (Sec. 3.2) Addition and subtraction (Sec. 3.3) Multiplication (Sec. 3.4) Division (Sec. 3.5) Floating point (Sec. 3.6) 2 Representation
More informationNumber Systems and Their Representations
Number Representations Cptr280 Dr Curtis Nelson Number Systems and Their Representations In this presentation you will learn about: Representation of numbers in computers; Signed vs. unsigned numbers;
More informationArithmetic. Chapter 3 Computer Organization and Design
Arithmetic Chapter 3 Computer Organization and Design Addition Addition is similar to decimals 0000 0111 + 0000 0101 = 0000 1100 Subtraction (negate) 0000 0111 + 1111 1011 = 0000 0010 Over(under)flow For
More information3.5 Floating Point: Overview
3.5 Floating Point: Overview Floating point (FP) numbers Scientific notation Decimal scientific notation Binary scientific notation IEEE 754 FP Standard Floating point representation inside a computer
More informationComputer Architecture Chapter 3. Fall 2005 Department of Computer Science Kent State University
Computer Architecture Chapter 3 Fall 2005 Department of Computer Science Kent State University Objectives Signed and Unsigned Numbers Addition and Subtraction Multiplication and Division Floating Point
More informationChapter 3 Arithmetic for Computers. ELEC 5200/ From P-H slides
Chapter 3 Arithmetic for Computers 1 Arithmetic for Computers Operations on integers Addition and subtraction Multiplication and division Dealing with overflow Floating-point real numbers Representation
More informationFloating Point COE 308. Computer Architecture Prof. Muhamed Mudawar. Computer Engineering Department King Fahd University of Petroleum and Minerals
Floating Point COE 38 Computer Architecture Prof. Muhamed Mudawar Computer Engineering Department King Fahd University of Petroleum and Minerals Presentation Outline Floating-Point Numbers IEEE 754 Floating-Point
More informationOutline. EEL-4713 Computer Architecture Multipliers and shifters. Deriving requirements of ALU. MIPS arithmetic instructions
Outline EEL-4713 Computer Architecture Multipliers and shifters Multiplication and shift registers Chapter 3, section 3.4 Next lecture Division, floating-point 3.5 3.6 EEL-4713 Ann Gordon-Ross.1 EEL-4713
More informationECE331: Hardware Organization and Design
ECE331: Hardware Organization and Design Lecture 10: Multiplication & Floating Point Representation Adapted from Computer Organization and Design, Patterson & Hennessy, UCB MIPS Division Two 32-bit registers
More informationChapter 3. Arithmetic for Computers
Chapter 3 Arithmetic for Computers Arithmetic for Computers Unsigned vs. Signed Integers Operations on integers Addition and subtraction Multiplication and division Dealing with overflow Floating-point
More informationSigned Multiplication Multiply the positives Negate result if signs of operand are different
Another Improvement Save on space: Put multiplier in product saves on speed: only single shift needed Figure: Improved hardware for multiplication Signed Multiplication Multiply the positives Negate result
More informationArithmetic for Computers. Integer Addition. Chapter 3
COMPUTER ORGANIZATION AND DESIGN The Hardware/Software Interface 5 th Edition Chapter 3 Arithmetic for Computers Arithmetic for Computers Operations on integers Addition and subtraction Multiplication
More informationNumber Systems and Computer Arithmetic
Number Systems and Computer Arithmetic Counting to four billion two fingers at a time What do all those bits mean now? bits (011011011100010...01) instruction R-format I-format... integer data number text
More informationInteger Subtraction. Chapter 3. Overflow conditions. Arithmetic for Computers. Signed Addition. Integer Addition. Arithmetic for Computers
COMPUTER ORGANIZATION AND DESIGN The Hardware/Software Interface 5 th Edition Integer Subtraction Chapter 3 Arithmetic for Computers Add negation of second operand Example: 7 6 = 7 + ( 6) +7: 0000 0000
More informationCOMPUTER ORGANIZATION AND DESIGN. 5 th Edition. The Hardware/Software Interface. Chapter 3. Arithmetic for Computers
COMPUTER ORGANIZATION AND DESIGN The Hardware/Software Interface 5 th Edition Chapter 3 Arithmetic for Computers Arithmetic for Computers Operations on integers Addition and subtraction Multiplication
More informationTailoring the 32-Bit ALU to MIPS
Tailoring the 32-Bit ALU to MIPS MIPS ALU extensions Overflow detection: Carry into MSB XOR Carry out of MSB Branch instructions Shift instructions Slt instruction Immediate instructions ALU performance
More informationCENG3420 L05: Arithmetic and Logic Unit
CENG3420 L05: Arithmetic and Logic Unit Bei Yu byu@cse.cuhk.edu.hk (Latest update: January 25, 2018) Spring 2018 1 / 53 Overview Overview Addition Multiplication & Division Shift Floating Point Number
More informationCOMPUTER ORGANIZATION AND DESIGN. 5 th Edition. The Hardware/Software Interface. Chapter 3. Arithmetic for Computers
COMPUTER ORGANIZATION AND DESIGN The Hardware/Software Interface 5 th Edition Chapter 3 Arithmetic for Computers Arithmetic for Computers Operations on integers Addition and subtraction Multiplication
More informationCOMPUTER ORGANIZATION AND DESIGN. 5 th Edition. The Hardware/Software Interface. Chapter 3. Arithmetic for Computers
COMPUTER ORGANIZATION AND DESIGN The Hardware/Software Interface 5 th Edition Chapter 3 Arithmetic for Computers Arithmetic for Computers Operations on integers Addition and subtraction Multiplication
More informationHomework 3. Assigned on 02/15 Due time: midnight on 02/21 (1 WEEK only!) B.2 B.11 B.14 (hint: use multiplexors) CSCI 402: Computer Architectures
Homework 3 Assigned on 02/15 Due time: midnight on 02/21 (1 WEEK only!) B.2 B.11 B.14 (hint: use multiplexors) 1 CSCI 402: Computer Architectures Arithmetic for Computers (2) Fengguang Song Department
More informationModule 2: Computer Arithmetic
Module 2: Computer Arithmetic 1 B O O K : C O M P U T E R O R G A N I Z A T I O N A N D D E S I G N, 3 E D, D A V I D L. P A T T E R S O N A N D J O H N L. H A N N E S S Y, M O R G A N K A U F M A N N
More informationInstruction Set Architecture of. MIPS Processor. MIPS Processor. MIPS Registers (continued) MIPS Registers
CSE 675.02: Introduction to Computer Architecture MIPS Processor Memory Instruction Set Architecture of MIPS Processor CPU Arithmetic Logic unit Registers $0 $31 Multiply divide Coprocessor 1 (FPU) Registers
More informationInteger Multiplication and Division
Integer Multiplication and Division COE 301 Computer Organization Prof. Muhamed Mudawar College of Computer Sciences and Engineering King Fahd University of Petroleum and Minerals Presentation Outline
More informationLecture 13: (Integer Multiplication and Division) FLOATING POINT NUMBERS
Lecture 13: (Integer Multiplication and Division) FLOATING POINT NUMBERS Lecture 13 Floating Point I (1) Fall 2005 Integer Multiplication (1/3) Paper and pencil example (unsigned): Multiplicand 1000 8
More informationFloating Point Arithmetic
Floating Point Arithmetic ICS 233 Computer Architecture and Assembly Language Dr. Aiman El-Maleh College of Computer Sciences and Engineering King Fahd University of Petroleum and Minerals [Adapted from
More informationFloating Point. The World is Not Just Integers. Programming languages support numbers with fraction
1 Floating Point The World is Not Just Integers Programming languages support numbers with fraction Called floating-point numbers Examples: 3.14159265 (π) 2.71828 (e) 0.000000001 or 1.0 10 9 (seconds in
More informationEE260: Logic Design, Spring n Integer multiplication. n Booth s algorithm. n Integer division. n Restoring, non-restoring
EE 260: Introduction to Digital Design Arithmetic II Yao Zheng Department of Electrical Engineering University of Hawaiʻi at Mānoa Overview n Integer multiplication n Booth s algorithm n Integer division
More informationECE260: Fundamentals of Computer Engineering
Arithmetic for Computers James Moscola Dept. of Engineering & Computer Science York College of Pennsylvania Based on Computer Organization and Design, 5th Edition by Patterson & Hennessy Arithmetic for
More informationCENG 3420 Lecture 05: Arithmetic and Logic Unit
CENG 3420 Lecture 05: Arithmetic and Logic Unit Bei Yu byu@cse.cuhk.edu.hk CENG3420 L05.1 Spring 2017 Outline q 1. Overview q 2. Addition q 3. Multiplication & Division q 4. Shift q 5. Floating Point Number
More informationMIPS ISA. 1. Data and Address Size 8-, 16-, 32-, 64-bit 2. Which instructions does the processor support
Components of an ISA EE 357 Unit 11 MIPS ISA 1. Data and Address Size 8-, 16-, 32-, 64-bit 2. Which instructions does the processor support SUBtract instruc. vs. NEGate + ADD instrucs. 3. Registers accessible
More informationECE331: Hardware Organization and Design
ECE331: Hardware Organization and Design Lecture 15: Midterm 1 Review Adapted from Computer Organization and Design, Patterson & Hennessy, UCB Basics Midterm to cover Book Sections (inclusive) 1.1 1.5
More informationLecture 8: Addition, Multiplication & Division
Lecture 8: Addition, Multiplication & Division Today s topics: Signed/Unsigned Addition Multiplication Division 1 Signed / Unsigned The hardware recognizes two formats: unsigned (corresponding to the C
More informationCOMPUTER ORGANIZATION AND. Edition. The Hardware/Software Interface. Chapter 3. Arithmetic for Computers
ARM D COMPUTER ORGANIZATION AND Edition The Hardware/Software Interface Chapter 3 Arithmetic for Computers Modified and extended by R.J. Leduc - 2016 In this chapter, we will investigate: How integer arithmetic
More informationComputer Architecture Set Four. Arithmetic
Computer Architecture Set Four Arithmetic Arithmetic Where we ve been: Performance (seconds, cycles, instructions) Abstractions: Instruction Set Architecture Assembly Language and Machine Language What
More informationEEM 486: Computer Architecture. Lecture 2. MIPS Instruction Set Architecture
EEM 486: Computer Architecture Lecture 2 MIPS Instruction Set Architecture EEM 486 Overview Instruction Representation Big idea: stored program consequences of stored program Instructions as numbers Instruction
More informationUNIVERSITY OF MASSACHUSETTS Dept. of Electrical & Computer Engineering. Digital Computer Arithmetic ECE 666
UNIVERSITY OF MASSACHUSETTS Dept. of Electrical & Computer Engineering Digital Computer Arithmetic ECE 666 Part 4-A Floating-Point Arithmetic Israel Koren ECE666/Koren Part.4a.1 Preliminaries - Representation
More informationLecture 10: Floating Point, Digital Design
Lecture 10: Floating Point, Digital Design Today s topics: FP arithmetic Intro to Boolean functions 1 Examples Final representation: (-1) S x (1 + Fraction) x 2 (Exponent Bias) Represent -0.75 ten in single
More informationOverview. Introduction to the MIPS ISA. MIPS ISA Overview. Overview (2)
Introduction to the MIPS ISA Overview Remember that the machine only understands very basic instructions (machine instructions) It is the compiler s job to translate your high-level (e.g. C program) into
More informationxx.yyyy Lecture #11 Floating Point II Summary (single precision): Precision and Accuracy Fractional Powers of 2 Representation of Fractions
CS61C L11 Floating Point II (1) inst.eecs.berkeley.edu/~cs61c CS61C : Machine Structures Lecture #11 Floating Point II 2007-7-12 Scott Beamer, Instructor Sony & Nintendo make E3 News www.nytimes.com Review
More informationComputer Architecture. The Language of the Machine
Computer Architecture The Language of the Machine Instruction Sets Basic ISA Classes, Addressing, Format Administrative Matters Operations, Branching, Calling conventions Break Organization All computers
More informationFloating-Point Data Representation and Manipulation 198:231 Introduction to Computer Organization Lecture 3
Floating-Point Data Representation and Manipulation 198:231 Introduction to Computer Organization Instructor: Nicole Hynes nicole.hynes@rutgers.edu 1 Fixed Point Numbers Fixed point number: integer part
More informationChapter 3 Arithmetic for Computers
Chapter 3 Arithmetic for Computers 1 Arithmetic for Computers Operations on integers Addition and subtraction Multiplication and division Dealing with overflow Floating-point real numbers Representation
More informationReduced Instruction Set Computer (RISC)
Reduced Instruction Set Computer (RISC) Focuses on reducing the number and complexity of instructions of the ISA. RISC Goals RISC: Simplify ISA Simplify CPU Design Better CPU Performance Motivated by simplifying
More informationCS222: Processor Design
CS222: Processor Design Dr. A. Sahu Dept of Comp. Sc. & Engg. Indian Institute of Technology Guwahati 1 Outline Previous Class: Floating points: Add, Sub, Mul,Div, Rounding Processor Design: Introduction
More informationIEEE Standard 754 for Binary Floating-Point Arithmetic.
CS61C L11 Floating Point II (1) inst.eecs.berkeley.edu/~cs61c CS61C : Machine Structures Lecture #11 Floating Point II 2005-10-05 There is one handout today at the front and back of the room! Lecturer
More informationECE 2035 Programming HW/SW Systems Fall problems, 7 pages Exam Two 23 October 2013
Instructions: This is a closed book, closed note exam. Calculators are not permitted. If you have a question, raise your hand and I will come to you. Please work the exam in pencil and do not separate
More informationCOMP 303 Computer Architecture Lecture 6
COMP 303 Computer Architecture Lecture 6 MULTIPLY (unsigned) Paper and pencil example (unsigned): Multiplicand 1000 = 8 Multiplier x 1001 = 9 1000 0000 0000 1000 Product 01001000 = 72 n bits x n bits =
More informationMIPS Instruction Set
MIPS Instruction Set Prof. James L. Frankel Harvard University Version of 7:12 PM 3-Apr-2018 Copyright 2018, 2017, 2016, 201 James L. Frankel. All rights reserved. CPU Overview CPU is an acronym for Central
More informationCO Computer Architecture and Programming Languages CAPL. Lecture 13 & 14
CO20-320241 Computer Architecture and Programming Languages CAPL Lecture 13 & 14 Dr. Kinga Lipskoch Fall 2017 Frame Pointer (1) The stack is also used to store variables that are local to function, but
More informationCS61C : Machine Structures
inst.eecs.berkeley.edu/~cs61c CS61C : Machine Structures Lecture #11 Floating Point II Scott Beamer, Instructor Sony & Nintendo make E3 News 2007-7-12 CS61C L11 Floating Point II (1) www.nytimes.com Review
More informationCPE300: Digital System Architecture and Design
CPE300: Digital System Architecture and Design Fall 2011 MW 17:30-18:45 CBC C316 Arithmetic Unit 10122011 http://www.egr.unlv.edu/~b1morris/cpe300/ 2 Outline Recap Fixed Point Arithmetic Addition/Subtraction
More informationMark Redekopp, All rights reserved. EE 357 Unit 11 MIPS ISA
EE 357 Unit 11 MIPS ISA Components of an ISA 1. Data and Address Size 8-, 16-, 32-, 64-bit 2. Which instructions does the processor support SUBtract instruc. vs. NEGate + ADD instrucs. 3. Registers accessible
More informationChapter Three. Arithmetic
Chapter Three 1 Arithmetic Where we've been: Performance (seconds, cycles, instructions) Abstractions: Instruction Set Architecture Assembly Language and Machine Language What's up ahead: Implementing
More informationReduced Instruction Set Computer (RISC)
Reduced Instruction Set Computer (RISC) Reduced Instruction Set Computer (RISC) Focuses on reducing the number and complexity of instructions of the machine. Reduced number of cycles needed per instruction.
More informationChapter 3: Arithmetic for Computers
Chapter 3: Arithmetic for Computers Objectives Signed and Unsigned Numbers Addition and Subtraction Multiplication and Division Floating Point Computer Architecture CS 35101-002 2 The Binary Numbering
More informationNUMBER OPERATIONS. Mahdi Nazm Bojnordi. CS/ECE 3810: Computer Organization. Assistant Professor School of Computing University of Utah
NUMBER OPERATIONS Mahdi Nazm Bojnordi Assistant Professor School of Computing University of Utah CS/ECE 3810: Computer Organization Overview Homework 4 is due tonight Verify your uploaded file before the
More informationCO Computer Architecture and Programming Languages CAPL. Lecture 15
CO20-320241 Computer Architecture and Programming Languages CAPL Lecture 15 Dr. Kinga Lipskoch Fall 2017 How to Compute a Binary Float Decimal fraction: 8.703125 Integral part: 8 1000 Fraction part: 0.703125
More informationECE232: Hardware Organization and Design. Computer Organization - Previously covered
ECE232: Hardware Organization and Design Part 6: MIPS Instructions II http://www.ecs.umass.edu/ece/ece232/ Adapted from Computer Organization and Design, Patterson & Hennessy, UCB Computer Organization
More informationFloating Point Numbers
Floating Point Numbers Summer 8 Fractional numbers Fractional numbers fixed point Floating point numbers the IEEE 7 floating point standard Floating point operations Rounding modes CMPE Summer 8 Slides
More informationCSCI 402: Computer Architectures. Arithmetic for Computers (3) Fengguang Song Department of Computer & Information Science IUPUI.
CSCI 402: Computer Architectures Arithmetic for Computers (3) Fengguang Song Department of Computer & Information Science IUPUI 3.5 Today s Contents Floating point numbers: 2.5, 10.1, 100.2, etc.. How
More informationFloating-point representations
Lecture 10 Floating-point representations Methods of representing real numbers (1) 1. Fixed-point number system limited range and/or limited precision results must be scaled 100101010 1111010 100101010.1111010
More informationFloating-point representations
Lecture 10 Floating-point representations Methods of representing real numbers (1) 1. Fixed-point number system limited range and/or limited precision results must be scaled 100101010 1111010 100101010.1111010
More informationComputer Architecture. MIPS Instruction Set Architecture
Computer Architecture MIPS Instruction Set Architecture Instruction Set Architecture An Abstract Data Type Objects Registers & Memory Operations Instructions Goal of Instruction Set Architecture Design
More informationMath in MIPS. Subtracting a binary number from another binary number also bears an uncanny resemblance to the way it s done in decimal.
Page < 1 > Math in MIPS Adding and Subtracting Numbers Adding two binary numbers together is very similar to the method used with decimal numbers, except simpler. When you add two binary numbers together,
More informationCSE 141 Computer Architecture Summer Session Lecture 3 ALU Part 2 Single Cycle CPU Part 1. Pramod V. Argade
CSE 141 Computer Architecture Summer Session 1 2004 Lecture 3 ALU Part 2 Single Cycle CPU Part 1 Pramod V. Argade Reading Assignment Announcements Chapter 5: The Processor: Datapath and Control, Sec. 5.3-5.4
More information361 div.1. Computer Architecture EECS 361 Lecture 7: ALU Design : Division
361 div.1 Computer Architecture EECS 361 Lecture 7: ALU Design : Division Outline of Today s Lecture Introduction to Today s Lecture Divide Questions and Administrative Matters Introduction to Single cycle
More informationAssembly Programming
Designing Computer Systems Assembly Programming 08:34:48 PM 23 August 2016 AP-1 Scott & Linda Wills Designing Computer Systems Assembly Programming In the early days of computers, assembly programming
More informationFlow of Control -- Conditional branch instructions
Flow of Control -- Conditional branch instructions You can compare directly Equality or inequality of two registers One register with 0 (>,
More informationEEC 483 Computer Organization
EEC 483 Computer Organization Chapter 3. Arithmetic for Computers Chansu Yu Table of Contents Ch.1 Introduction Ch. 2 Instruction: Machine Language Ch. 3-4 CPU Implementation Ch. 5 Cache and VM Ch. 6-7
More informationThe MIPS Instruction Set Architecture
The MIPS Set Architecture CPS 14 Lecture 5 Today s Lecture Admin HW #1 is due HW #2 assigned Outline Review A specific ISA, we ll use it throughout semester, very similar to the NiosII ISA (we will use
More informationCOMP2611: Computer Organization. Data Representation
COMP2611: Computer Organization Comp2611 Fall 2015 2 1. Binary numbers and 2 s Complement Numbers 3 Bits: are the basis for binary number representation in digital computers What you will learn here: How
More informationCISC 662 Graduate Computer Architecture. Lecture 4 - ISA
CISC 662 Graduate Computer Architecture Lecture 4 - ISA Michela Taufer http://www.cis.udel.edu/~taufer/courses Powerpoint Lecture Notes from John Hennessy and David Patterson s: Computer Architecture,
More informationLecture 10: Floating Point, Digital Design
Lecture 10: Floating Point, Digital Design Today s topics: FP arithmetic Intro to Boolean functions 1 Examples Final representation: (-1) S x (1 + Fraction) x 2 (Exponent Bias) Represent -0.75 ten in single
More informationReview of Last lecture. Review ALU Design. Designing a Multiplier Shifter Design Review. Booth s algorithm. Today s Outline
Today s Outline San Jose State University EE176-SJSU Computer Architecture and Organization Lecture 5 HDL, ALU, Shifter, Booth Algorithm Multiplier & Divider Instructor: Christopher H. Pham Review of Last
More informationCISC 662 Graduate Computer Architecture. Lecture 4 - ISA MIPS ISA. In a CPU. (vonneumann) Processor Organization
CISC 662 Graduate Computer Architecture Lecture 4 - ISA MIPS ISA Michela Taufer http://www.cis.udel.edu/~taufer/courses Powerpoint Lecture Notes from John Hennessy and David Patterson s: Computer Architecture,
More informationCO212 Lecture 10: Arithmetic & Logical Unit
CO212 Lecture 10: Arithmetic & Logical Unit Shobhanjana Kalita, Dept. of CSE, Tezpur University Slides courtesy: Computer Architecture and Organization, 9 th Ed, W. Stallings Integer Representation For
More informationWeek 10: Assembly Programming
Week 10: Assembly Programming Arithmetic instructions Instruction Opcode/Function Syntax Operation add 100000 $d, $s, $t $d = $s + $t addu 100001 $d, $s, $t $d = $s + $t addi 001000 $t, $s, i $t = $s +
More information