Writing LLVM Backends Construindo Backends para o LLVM. Bruno Cardoso Lopes

Transcription

1 Writing LLVM Backends Construindo Backends para o LLVM Bruno Cardoso Lopes

2 Agenda What s LLVM? Why LLVM? Who is using? Infrastructure. Internals. The Backend. Writing LLVM backends. Work.

3 What's LLVM? Low Level Virtual Machine A compiler infrastructure suite. Compiler frontend (llvm-gcc, clang) + IR + LLVM Backends. A virtual instruction set. RISC based, language independent with SSA information. Frontend IR Backend

4 What's LLVM? A optimization oriented compiler. Provides compile time, link-time and offline optimizations. LLVM Bitcode Backend Frontend disk optimizer

5 Why LLVM? Doesn't have a very steep learning curve compared to other known compilers. Good for compiler students. Lots of interesting compiler optimizations. Learning difficulty GCC LLVM

6 Who is using? Apple (OpenGL JIT compiler, Xcode, IPhone) Pypy, Lunar, Mesa, Gallium3D, Adobe, Qemu

7 The Compiler Infrastructure. LLVM Frontend GCC based front-end : llvm-gcc Very mature and supports Java, Ada, FORTRAN, C, C++ and ObjC. $ llvm-gcc -O2 -c bozo.c --emit-llvm $ llvm-dis < bozo.o LLVM assembly... define %lhs, i32 %rhs, float %w) nounwind { entry: %tmp3 = sdiv i32 %lhs, %rhs ; <i32> [#uses=1] %tmp34 = sitofp i32 %tmp3 to float ; <float> [#uses=1] %tmp6 = mul float %tmp34, %w ; <float> [#uses=1] ret float %tmp6 }

8 The Compiler Infrastructure. LLVM Frontend Clang: C, C++, Objective C and Objective C++ front-end. Not yet stable but provide better diagnostics, integration with IDEs and easier to develop and maintain. $ clang -fsyntax-only ~/t.c -pedantic /tmp/blah.c:2:17: warning: extension used typedef float V attribute ((vector_size(16))); ^ 1 diagnostic generated.

9 The Compiler Infrastructure. LLVM Backend Target many architectures : Alpha, ARM, C, CellSPU, IA64, Mips, MSIL, Emit C Code, MSIL and JIT for X86, X86-64, PowerPC 32/64 PowerPC, Sparc, X86/X86_64 x86 $ lli hello.o JIT Engine PowerPC

10 The Compiler Infrastructure. LLVM Driver llvmc, a llvm based compiler driver under development. The objective is to have a compiler driver like gcc. llvmc -O2 x.c y.c z.c -o xyz llvmc -O2 x.c -o x.o llvmc -O2 y.c -o y.o llvmc -O2 z.c -o z.o llvmc -O2 x.o y.o z.o -o xyz

11 The Compiler Infrastructure. Optimizations Compile-time optimizations Driven with -O{1,2,3,s} in llvm-gcc. Link-time (cross-file, interprocedural) optimizations. raiseallocs simplifycfg domtree domfrontier mem2reg globalopt globaldce ipconstprop deadargelim instcombine simplifycfg basiccg pruneeh inline simplifylibcalls basiccg argpromotion tailduplicate instcombine simplifycfg domtree domfrontier scalarrepl instcombine breakcritedges condprop tailcallelim simplifycfg reassociate domtree loops loopsimplify domfrontier scalarevolution lcssa looprotate licm lcssa loopunswitch scalarevolution lcssa loopindexsplit instcombine scalarevolution domfrontier lcssa indvars domfrontier scalarevolution lcssa loopunroll instcombine domtree memdep gvn sccp instcombine breakcritedges condprop memdep dse mergereturn postdomtree postdomfrontier adce simplifycfg constmerge stripdeadprototypes

12 What's LLVM? Putting it all together Frontend float bozo(int lhs, int rhs, float w) { float c = (lhs/rhs)*w; return c; } llvm-gcc --emit-llvm -c bozo.c Optimizations llvm-extract -func=bozo bozo.o opt -std-compile-opts...

13 Putting it all together What's LLVM? Optimizations define %lhs, i32 %rhs, float %w) { entry: %tmp3 = sdiv i32 %lhs, %rhs %tmp34 = sitofp i32 %tmp3 to float %tmp6 = mul float %tmp34, %w ret float %tmp6 }... llc -march=arm Backend bozo: stmfd sp!, {r4, lr} sub sp, sp, #8 mov r4, r2 bl divsi3 bl floatsisf mov r1, r4 bl mulsf3 add sp, sp, #8 ldmfd sp!, {r4, pc}.size bozo,.-bozo

14 LLVM Internals Well written C++ Pluggable register allocators Modular and Pluggable optimization framework and register allocator. $ clang vect.c -emit-llvm llvm-as opt -std-compile-opts llvm-dis define <4 x x float> %a, <4 x float> %b) { entry: %mul = mul <4 x float> %b, %a %add = add <4 x float> %mul, %a ret <4 x float> %add }

15 LLVM Internals Library approach (Runtime, Target, Code Generation, Transformation, Core and Analysis libraries) Did i hear Python bindings? ;) Easy to write and plug a new optimization. $ clang vect.c -emit-llvm llvm-as opt -std-compile-opts llc -march=x86 -mcpu=yonah... _foo: mulps %xmm0, %xmm1 addps %xmm0, %xmm1 movaps %xmm1, %xmm0 ret

16 The Backend What's the backend job? Support the target ABI (calling conventions, PIC,...). Translate the IR to real instructions and registers. Do code generation issues (Instruction selection,scheduling,...).

17 The Backend How's that done? LLVM has a target independent code generator. Inheritance and overloading are used to define target specific details. Node Lowering (CALL, FORMAL_ARGUMENTS, RET, TLS).

18 How's that done? The Backend Describe target specific ABI information def CC_Mips : CallingConv<[ // Promote i8/i16 arguments to i32. CCIfType<[i8, i16], CCPromoteToType<i32>>, // The first 4 integer arguments are passed in // integer registers. CCIfType<[i32], CCAssignToReg<[A0, A1, A2, A3]>>, // Integer values get stored in stack slots // that are 4 bytes in size and 4-byte aligned. CCIfType<[i32], CCAssignToStack<4, 4>> ]>;

19 How's that done? The Backend Node Lowering CALL, FORMAL_ARGUMENTS, Ret, GlobalAdress, JumpTable LowerOperation(SDOperand Op, SelectionDAG &DAG) { switch (Op.getOpcode()) { case ISD::CALL: return LowerCALL(Op, DAG);... case ISD::JumpTable: return LowerJumpTable(Op, DAG);...

20 Supported Archs The Backend X86/X86_64 and PowerPC 32/64 are very stable backends. Each backend is a standalone library. Very clean directory hierarchy X86AsmPrinter.cpp X86ISelLowering.cpp X86FloatingPoint.cpp X86InstrInfo.td X86JITInfo.cpp X86ATTAsmPrinter.cpp X86InstrMMX.td X86CallingConv.td X86ELFWriterInfo.cpp

21 The Backend TableGen TableGen to describe the architecture Calling Convention, Instruction, Registers, Itinerary...) Can describe high and low level representations at the same time, e.g. bit fields and DAGs could be represented def RET { // Instruction MipsInst FR field bits<32> Inst = {..., rd{4}, rd{3}, rd{2}, rd{1}, rd{0},...}; string Namespace = "Mips"; dag OutOperandList = (outs); dag InOperandList = (ins CPURegs:$target); string AsmString = "jr $target"; list<dag> Pattern = [(MipsRet CPURegs:$target)]; InstrItinClass Itinerary = IIBranch;... bits<5> shamt = { 0, 0, 0, 0, 0 }; bits<6> funct = { 0, 0, 0, 0, 1, 0 }; }

22 The Backend Instructions defined with TableGen are matched with the llvm virtual instruction set. Easy to define Peephole optimizations. The target can easily define custom Nodes (operations not llvm native). Direct instruction matching def ADDu {... list<dag> Pattern = [(set CPURegs:$dst, (add CPURegs:$b, CPURegs:$c))]; }

23 The Backend def MipsJmpLink : SDNode<"MipsISD::JmpLink", SDT_MipsJmpLink, [SDNPHasChain, SDNPOutFlag]>; New node handling case MipsISD::JmpLink: { if (TM.getRelocationModel() == Reloc::PIC_) {... Peephole Optimizations def : Pat<(not CPURegs:$in), (NOR CPURegs:$in, ZERO)>;

24 The Backend Asm and Binary emission Target independent Asm Printer. Asm emission as default (followed by calls to the GNU assembler and linker) with flavors. Experimental ELF emission.

25 Writing LLVM Backends Want to develop a new Backend for LLVM? Start with Mips and Sparc backends as references. Implement ABI and Lowering. Peephole and other target specific optimizations. Compile the llvm test suite. Describe target specific information with TableGen.

26 Writing LLVM Backends How should i test and debug? Real hardware really helps! Don't have money? GDB is our friend. Find some emulator (thanks QEMU!) Ask for hardware donation

27 Writing LLVM Backends Open projects Improve ELF support. Implement new optimizations. Use llvm in your compiler course at college. Add support for features and target specific optimizations. Ask questions to llvmdev mailing list or at #llvm (irc.oftc.net)

28 Work and LLVM Implemented the Mips backend as a Google Summer Of Code project. Mips is still fairly used nowadays (PSP, PS2, broadcom, linksys routers, TVs,...) PS2 Emotion Engine Broadcom

29 Future Work The Backend is still experimental. Improve the backend supporting code generation for PSP. PSP

30 End... Thanks!!! Questions!?