# SIR C.R.REDDY COLLEGE OF ENGINEERING, ELURU DEPARTMENT OF INFORMATION TECHNOLOGY LESSON PLAN

Size: px
Start display at page:

Download "SIR C.R.REDDY COLLEGE OF ENGINEERING, ELURU DEPARTMENT OF INFORMATION TECHNOLOGY LESSON PLAN"

Transcription

1 SIR C.R.REDDY COLLEGE OF ENGINEERING, ELURU DEPARTMENT OF INFORMATION TECHNOLOGY LESSON PLAN SUBJECT: CSE DIGITAL LOGIC DESIGN CLASS: 2/4 B.Tech., I SEMESTER, A.Y INSTRUCTOR: Sri A.M.K.KANNA BABU

2 SIR C R REDDY COLLEGE OF ENGINEERING DEPT. OF INFORMATION TECHNOLOGY PROGRAMME : B.Tech SEMESTER : II/IV I Semester A.YEAR : COURSE : CSE DIGITAL LOGIC DESIGN INSTRUCTOR : Sri A.M.K.KANNA BABU Course Contents Category of Course Course Title Course Code Credits- 4 Theory Paper Departmental Core - CSE DIGITAL LOGIC DESIGN CSE L-3 T-1 Max.Marks-70 Duration-3hrs. Course objectives: 1. To introduce number systems and Binary codes. 2. To introduce basic postulates of Boolean algebra and shows the correlation between Boolean expressions and Boolean functions. 3. To introduce the methods for simplifying Boolean expressions. 4. To outline the formal procedures for the analysis and design of combinational circuits and sequential circuits. 5. To introduce the concept of memories, programmable logic devices. Students who have successfully completed this course will have full understanding of the following concepts

3 Course Outcomes for Digital Logic Design: Able to understand Binary Systems, Boolean Functions, Logic Gates, Combinational Circuits, Sequential Circuits and different types of memories. Able to apply number systems, Boolean functions and logic gates for the design of digital circuits. Able to analyze different logic circuits (like combinational and sequential circuits). Able to design different digital circuits. Online References: Prerequisite: Students are expected to know mathematical fundamental and logical skills. Internal Assessment Details: Attendance : 5 Marks Internal Test 1& 2 : 15 Marks Assignment-1 : 5 Marks Assignment-2 : 5 Marks Total : 30 Marks

4 DIGITAL LOGIC DESIGN CSE2.1.6 Credits : 4 Instruction : 3 Periods & 1 Tut /week Sessional Marks : 30 University-Exam : 3 Hours Univ-Exam Marks: Binary Systems: Digital Systems. Binary Numbers. Number Base Conversions. Octal and Hexadecimal Numbers. Complements. Signed Binary Numbers. Binary Codes. Binary Storage and Registers. Binary Logic. 2. Boolean algebra and Logic Gates. Basic Definitions. Axiomatic Definition of Boolean Algebra. Basic Theorems and Properties of Boolean Algebra. Boolean Functions. Canonical and Standard Forms. Other Logic Operations. Digital Logic Gates. Integrated Circuits. 3. Combinational Logic Design, Gate-Level Minimization. The Map Method. Four-Variable Map. Five-Variable Map. Product of Sums Simplification. Don't-Care Conditions. NAND and NOR Implementation. Other Two- Level Implementations. Exclusive-OR Function. Hardware Description Language (HDL). 4. Combinational Logic Combinational Circuits. Analysis Procedure. Design Procedure. Binary Adder- Subtractor. Decimal Adder. Binary Multiplier. Magnitude Comparator. Decoders. Encoders. Multiplexers. HDL For Combinational Circuits. 5. Sequential Logic Design, Synchronous Sequential Logic Sequential Circuits. Latches. Flip-Flops. Analysis of Clocked Sequential Circuits. HDL For Sequential Circuits. State Reduction and Assignment. Design Procedure. 6. Registers ad Counters. Registers. Shift Registers. Ripple Counters. Synchronous Counters. Other Counters. HDL for Registers and Counters. 7. Memory and Programmable Logic Introduction. Random-Access Memory. Memory Decoding. Error Detection and Correction. Read-Only Memory. Programmable Logic Array. Programmable Array Logic. Sequential Programmable Devices. Text Books: 1. Digital Design, 3rd Edition, M. Morris Mano, Pearson Education, Inc., 2002

5 SIR C R REDDY COLLEGE OF ENGINEERING: ELURU DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING The schedule for the whole course/subject is: COURSE SCHEDULE Unit No Description of the Chapter Description of the Topics Total no of periods (L+T) 1 Binary Systems Digital Systems. Binary Numbers. Number Base Conversions. Octal and Hexadecimal Numbers. Complements. Signed Binary Numbers. Binary Codes. Binary Storage and Registers. Binary Logic Boolean algebra and Logic Gates Basic Definitions. Axiomatic Definition of Boolean Algebra. Basic Theorems and Properties of Boolean Algebra. Boolean Functions. Canonical and Standard Forms. Other Logic Operations. Digital Logic Gates. Integrated Circuits Combinational Logic Design, Gate-Level Minimization The Map Method. Four-Variable Map. Five-Variable Map. Product of Sums Simplification. Don't- Care Conditions. NAND and NOR Implementation. Other Two- Level Implementations. Exclusive-OR Function. Hardware Description Language (HDL) Combinational Logic Combinational Circuits. Analysis Procedure. Design Procedure. Binary Adder- Subtractor. Decimal Adder. Binary Multiplier. Magnitude Comparator. Decoders. Encoders. 9+1

6 Multiplexers. HDL For Combinational Circuits. 5 Sequential Logic Design, Synchronous Sequential Logic Sequential Circuits. Latches. Flip- Flops. Analysis of Clocked Sequential Circuits. HDL For Sequential Circuits. State Reduction and Assignment. Design Procedure Registers and Counters. Registers. Shift Registers. Ripple Counters. Synchronous Counters. Other Counters. HDL for Registers and Counters Memory and Programmable Logic Introduction. Random-Access Memory. Memory Decoding. Error Detection and Correction. Read-Only Memory. Programmable Logic Array. Programmable Array Logic. Sequential Programmable Devices. 4+1 Total number of estimated periods : 65 periods Signature of the H.O.D Signature of the Faculty Date:

7 LECTURE PLAN DEPARTMET NAME OF LECTURER INFORMATION TECHNOLOGY Sri A.M.K.KANNA BABU Sl. No Topics to be covered No. of Lecture Teaching method 1 Introduction to Digital Systems 2 Binary numbers 3 Number system conversion 2 BB 4 Octal and Hexadecimal Numbers 5 Complements 2 BB 6 Signed Binary Numbers 2 BB 7 Binary Codes 2 BB 8 Binary Storage and Registers 2 PPT with LCD 9 Binary Logic 2 BB 10 Basic Definitions 11 Axiomatic Definition of Boolean Algebra 12 Basic Theorems and Properties of Boolean Algebra 13 Boolean Functions 1 14 Canonical and Standard Forms 2 BB

8 15 Other Logic Operations 2 BB 16 Digital Logic Gates 17 Integrated Circuits 18 The Map Method 1 PPT with LCD 19 Four-Variable Map 20 Five-Variable Map 2 BB 21 Product of Sums Simplification 22 Don't-Care Conditions 23 NAND and NOR Implementation 24 Other Two- Level Implementations 1 25 Exclusive-OR Function 26 Hardware Description Language (HDL) 27 Combinational Circuits Analysis Procedure 28 Design Procedure 29 Binary Adder- Subtractor 1 PPT with LCD 30 Decimal Adder 1 31 Binary Multiplier 32 Magnitude Comparator 33 Decoders

9 34 Encoders 35 Multiplexers 1 36 HDL For Combinational Circuits 37 Sequential Circuits 38 Latches 39 Flip-Flops 2 BB 40 Analysis of Clocked Sequential Circuits 2 BB 41 HDL For Sequential Circuits 42 State Reduction and Assignment 43 Design Procedure 2 BB 44 Registers 2 BB 45 Counters 3 BB 46 Introduction Memory RAM and ROM 47 Error Detection and Correction 48 Programmable Logic Array 49 Programmable Array Logic 1 PPT with LCD 50 Sequential Programmable Devices Total number of estimated periods : 65 periods

10 Unit wise questions (short and essay) DIGITAL LOGIC DESIGN Unit Wise Question Bank UNIT-I 1. Find the two s complements of following numbers: a) (1230) 4 and (23) 4 b) (135.4) 6 and (43.2) 6 2. Convert the following numbers from the given base to the base indicated. a) decimal to binary, octal and hexadecimal. b) Binary ( ) to decimal, octal and hexadecimal; 3. Convert the following numbers from the given base to the base indicated. a) octal to decimal, binary and hexadecimal b) hexadecimal 2ACD.5 to decimal, binary and octal. 4. Convert the following number to decimal a) (0.342) 6 b) (8.3) 9 c) (198) 12 d) (50) 7 5. Obtain the 9 s and 10 s complement of the following decimal numbers a) b) c) d) e) Obtain the 1 s and 2 s complement of the following binary numbers a) b) c) d) e) Perform the subtraction with the following numbers using 2 s and 1 s complement a) b)

11 8. Explain a) self-complementary codes with examples. b) Error-detection codes and Reflected Code 9. Explain a) BCD codes b) Register transfer with a neat diagram. 10. a) Explain basic logic gates with a truth tables and gates UNIT-II b) Define Boolean algebra and prove the following theorems (i) X + X = X (ii) X.0 = 0 (iii) X + XY = X (iv) (XY) 1 = X 1 + Y 1 1. Implement 64 1 multiplexer with four 16 1 and one 4 1 multiplexer. (Use only block diagram). 2. A combinational logic circuit is defined by the following Boolean functions. F1 = ABC + AC F2 = ABC + AB F3 = ABC + AB Design the circuit with a decoder and external gates. xy + x (wz + wz ). 3. If F1 = Π 3,4,7,8,11,14,15 and F2 = Σ1,2,4,5,7,8,10,11,12,15 obtain minimal SOP expression for F1 F 2 and draw the circuit using NAND gates. 4. Draw the two -level NAND circuit for the following Boolean - expression: AB + CD E + BC (A + B) also obtain minimal SOP expression and draw the circuit using NAND gates.

12 5. If F1(A,B,C) = A _ B _ C F2 (A,B,C) = A_C _B Show that F1 = F2 6. Construct K-map for the following expression and obtain minimal SOP expression. Implement the function with 2-level NAND -NAND form. f (A,B,C,D) = (A + C + D) (A + B + D)(A + B + C 1 )(A + B + D)(A 1 + B + D) 7. Implement the following Boolean function F using the two - level form: i. NAND-AND ii. AND-NOR F (A,B,C,D) = _0, 1, 2, 3, 4, 8, 9, 12 UNIT-III 1. What is a flip-flop? 2. What is a latch? 3. What is a sequential circuit? 4. What is asynchronous sequential circuit? 5. Draw and explain the logic diagram of a master-slave D flip-flop using NAND gates. 6. a) Design a synchronous BCD counter with JK flip-flops. b) Design a shift register with parallel load that operates according to the following function table: Shift Load Register Operation 0 0 No Change 0 1 Load Parallel Data 1 X Shift Right

13 7. (a) Design a 4-bit ring counter using T- flip flops and draw the circuit diagram and timing diagrams. (b) Draw the block diagram and explain the operation of serial transfer between two shift registers and draw its timing diagram. 8. Reduce the number of states in the state table listed below. Use an implication table. Present state Next state Output x=0 x=1 x=0 x=1 a f b 0 0 b d c 0 0 c f e 0 0 d g a 0 0 e d c 0 0 f f b 1 1 g g h 0 1 h g a 1 0 UNIT-IV 1. What is a RAM? 2. Explain types of RAM? 3. What is a ROM? 4. Explain types of ROM?

14 5. What is a PAL? 6. What is a PLA? 7. (a) Explain the block diagram of a memory unit. Explain the read and write operation a RAM can perform. (b) i. How many 32K * 8 RAM chips are needed to provide a memory capacity of 256K bytes. ii. How many lines of the address must be used to access 256K bytes? How many of these lines are connected to the address inputs of all chips? iii.how many lines must be decoded for the chip select inputs? Specify the size of the decoder. 8. Explain RAM and ROM? 9. Explain PAL? 10.Explain PLA?

### Code No: R Set No. 1

Code No: R059210504 Set No. 1 II B.Tech I Semester Regular Examinations, November 2006 DIGITAL LOGIC DESIGN ( Common to Computer Science & Engineering, Information Technology and Computer Science & Systems

### Code No: R Set No. 1

Code No: R059210504 Set No. 1 II B.Tech I Semester Supplementary Examinations, February 2007 DIGITAL LOGIC DESIGN ( Common to Computer Science & Engineering, Information Technology and Computer Science

### Code No: R Set No. 1

Code No: R059210504 Set No. 1 II B.Tech I Semester Regular Examinations, November 2007 DIGITAL LOGIC DESIGN ( Common to Computer Science & Engineering, Information Technology and Computer Science & Systems

### Code No: 07A3EC03 Set No. 1

Code No: 07A3EC03 Set No. 1 II B.Tech I Semester Regular Examinations, November 2008 SWITCHING THEORY AND LOGIC DESIGN ( Common to Electrical & Electronic Engineering, Electronics & Instrumentation Engineering,

### B.Tech II Year I Semester (R13) Regular Examinations December 2014 DIGITAL LOGIC DESIGN

B.Tech II Year I Semester () Regular Examinations December 2014 (Common to IT and CSE) (a) If 1010 2 + 10 2 = X 10, then X is ----- Write the first 9 decimal digits in base 3. (c) What is meant by don

### R a) Simplify the logic functions from binary to seven segment display code converter (8M) b) Simplify the following using Tabular method

SET - 1 1. a) Convert the decimal number 250.5 to base 3, base 4 b) Write and prove de-morgan laws c) Implement two input EX-OR gate from 2 to 1 multiplexer (3M) d) Write the demerits of PROM (3M) e) What

### HANSABA COLLEGE OF ENGINEERING & TECHNOLOGY (098) SUBJECT: DIGITAL ELECTRONICS ( ) Assignment

Assignment 1. What is multiplexer? With logic circuit and function table explain the working of 4 to 1 line multiplexer. 2. Implement following Boolean function using 8: 1 multiplexer. F(A,B,C,D) = (2,3,5,7,8,9,12,13,14,15)

### R10. II B. Tech I Semester, Supplementary Examinations, May

SET - 1 1. a) Convert the following decimal numbers into an equivalent binary numbers. i) 53.625 ii) 4097.188 iii) 167 iv) 0.4475 b) Add the following numbers using 2 s complement method. i) -48 and +31

### II/IV B.Tech (Regular/Supplementary) DEGREE EXAMINATION. Answer ONE question from each unit.

Hall Ticket Number: 14CS IT303 November, 2017 Third Semester Time: Three Hours Answer Question No.1 compulsorily. II/IV B.Tech (Regular/Supplementary) DEGREE EXAMINATION Common for CSE & IT Digital Logic

www.vidyarthiplus.com Question Paper Code : 31298 B.E./B.Tech. DEGREE EXAMINATION, NOVEMBER/DECEMBER 2013. Third Semester Computer Science and Engineering CS 2202/CS 34/EC 1206 A/10144 CS 303/080230012--DIGITAL

### Philadelphia University Student Name: Student Number:

Philadelphia University Student Name: Student Number: Faculty of Engineering Serial Number: Final Exam, First Semester: 2018/2019 Dept. of Computer Engineering Course Title: Logic Circuits Date: 03/01/2019

### Digital logic fundamentals. Question Bank. Unit I

Digital logic fundamentals Question Bank Subject Name : Digital Logic Fundamentals Subject code: CA102T Staff Name: R.Roseline Unit I 1. What is Number system? 2. Define binary logic. 3. Show how negative

### VALLIAMMAI ENGINEERING COLLEGE

VALLIAMMAI ENGINEERING COLLEGE SRM Nagar, Kattankulathur 603 203 DEPARTMENT OF INFORMATION TECHNOLOGY & COMPUTER SCIENCE AND ENGINEERING QUESTION BANK II SEMESTER CS6201- DIGITAL PRINCIPLE AND SYSTEM DESIGN

### SRM ARTS AND SCIENCE COLLEGE SRM NAGAR, KATTANKULATHUR

SRM ARTS AND SCIENCE COLLEGE SRM NAGAR, KATTANKULATHUR 603203 DEPARTMENT OF COMPUTER SCIENCE & APPLICATIONS LESSON PLAN (207-208) Course / Branch : B.Sc CS Total Hours : 50 Subject Name : Digital Electronics

### Injntu.com Injntu.com Injntu.com R16

1. a) What are the three methods of obtaining the 2 s complement of a given binary (3M) number? b) What do you mean by K-map? Name it advantages and disadvantages. (3M) c) Distinguish between a half-adder

### VALLIAMMAI ENGINEERING COLLEGE

VALLIAMMAI ENGINEERING COLLEGE SRM Nagar, Kattankulathur 603 203 DEPARTMENT OF INFORMATION TECHNOLOGY QUESTION BANK Academic Year 2018 19 III SEMESTER CS8351-DIGITAL PRINCIPLES AND SYSTEM DESIGN Regulation

### VALLIAMMAI ENGINEERING COLLEGE. SRM Nagar, Kattankulathur DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING EC6302 DIGITAL ELECTRONICS

VALLIAMMAI ENGINEERING COLLEGE SRM Nagar, Kattankulathur-603 203 DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING EC6302 DIGITAL ELECTRONICS YEAR / SEMESTER: II / III ACADEMIC YEAR: 2015-2016 (ODD

### COLLEGE OF ENGINEERING DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING QUESTION BANK SUBJECT CODE & NAME: EC 1312 DIGITAL LOGIC CIRCUITS UNIT I

KINGS COLLEGE OF ENGINEERING DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING QUESTION BANK SUBJECT CODE & NAME: EC 1312 DIGITAL LOGIC CIRCUITS YEAR / SEM: III / V UNIT I NUMBER SYSTEM & BOOLEAN ALGEBRA

### Scheme G. Sample Test Paper-I

Sample Test Paper-I Marks : 25 Times:1 Hour 1. All questions are compulsory. 2. Illustrate your answers with neat sketches wherever necessary. 3. Figures to the right indicate full marks. 4. Assume suitable

### END-TERM EXAMINATION

(Please Write your Exam Roll No. immediately) END-TERM EXAMINATION DECEMBER 2006 Exam. Roll No... Exam Series code: 100919DEC06200963 Paper Code: MCA-103 Subject: Digital Electronics Time: 3 Hours Maximum

### SIDDHARTH GROUP OF INSTITUTIONS :: PUTTUR Siddharth Nagar, Narayanavanam Road QUESTION BANK (DESCRIPTIVE)

SIDDHARTH GROUP OF INSTITUTIONS :: PUTTUR Siddharth Nagar, Narayanavanam Road 517583 QUESTION BANK (DESCRIPTIVE) Subject with Code : STLD(16EC402) Year & Sem: II-B.Tech & I-Sem Course & Branch: B.Tech

### R07. Code No: V0423. II B. Tech II Semester, Supplementary Examinations, April

SET - 1 II B. Tech II Semester, Supplementary Examinations, April - 2012 SWITCHING THEORY AND LOGIC DESIGN (Electronics and Communications Engineering) Time: 3 hours Max Marks: 80 Answer any FIVE Questions

### SUBJECT CODE: IT T35 DIGITAL SYSTEM DESIGN YEAR / SEM : 2 / 3

UNIT - I PART A (2 Marks) 1. Using Demorgan s theorem convert the following Boolean expression to an equivalent expression that has only OR and complement operations. Show the function can be implemented

### KING FAHD UNIVERSITY OF PETROLEUM & MINERALS COMPUTER ENGINEERING DEPARTMENT

KING FAHD UNIVERSITY OF PETROLEUM & MINERALS COMPUTER ENGINEERING DEPARTMENT COE 202: Digital Logic Design Term 162 (Spring 2017) Instructor: Dr. Abdulaziz Barnawi Class time: U.T.R.: 11:00-11:50AM Class

### SIR C.R.REDDY COLLEGE OF ENGINEERING, ELURU DEPARTMENT OF INFORMATION TECHNOLOGY LESSON PLAN

SIR C.R.REDDY COLLEGE OF ENGINEERING, ELURU DEPARTMENT OF INFORMATION TECHNOLOGY LESSON PLAN SUBJECT: IT 2.1.5 SYSTEM PROGRAMMING CLASS: 2/4 B.Tech., I SEMESTER, A.Y.2017-18 INSTRUCTOR: J.MALATHI SIR C

### INSTITUTE OF AERONAUTICAL ENGINEERING (Autonomous) Dundigal, Hyderabad

INSTITUTE OF AERONAUTICAL ENGINEERING (Autonomous) Dundigal, Hyderabad - 500 043 COMPUTER SCIENCE AND ENGINEERING TUTORIAL QUESTION BANK Name : DIGITAL LOGIC DESISN Code : AEC020 Class : B Tech III Semester

### INSTITUTE OF AERONAUTICAL ENGINEERING (Autonomous) Dundigal, Hyderabad

INSTITUTE OF AERONAUTICAL ENGINEERING (Autonomous) Dundigal, Hyderabad - 500043 Course Name : DIGITAL LOGIC DESISN Course Code : AEC020 Class : B Tech III Semester Branch : CSE Academic Year : 2018 2019

### Principles of Digital Techniques PDT (17320) Assignment No State advantages of digital system over analog system.

Assignment No. 1 1. State advantages of digital system over analog system. 2. Convert following numbers a. (138.56) 10 = (?) 2 = (?) 8 = (?) 16 b. (1110011.011) 2 = (?) 10 = (?) 8 = (?) 16 c. (3004.06)

### UPY14602-DIGITAL ELECTRONICS AND MICROPROCESSORS Lesson Plan

UPY14602-DIGITAL ELECTRONICS AND MICROPROCESSORS Lesson Plan UNIT I - NUMBER SYSTEMS AND LOGIC GATES Introduction to decimal- Binary- Octal- Hexadecimal number systems-inter conversions-bcd code- Excess

### SIR C.R.REDDY COLLEGE OF ENGINEERING, ELURU DEPARTMENT OF INFORMATION TECHNOLOGY LESSON PLAN

SIR C.R.REDDY COLLEGE OF ENGINEERING, ELURU DEPARTMENT OF INFORMATION TECHNOLOGY LESSON PLAN SUBJECT: (IT 4.1.3) ADVANCED OPERATING SYSTEM CLASS: 4/4 B.Tech. I SEMESTER, A.Y.2017-18 INSTRUCTOR: CHALLA

### R07

www..com www..com SET - 1 II B. Tech I Semester Supplementary Examinations May 2013 SWITCHING THEORY AND LOGIC DESIGN (Com. to EEE, EIE, BME, ECC) Time: 3 hours Max. Marks: 80 Answer any FIVE Questions

### DHANALAKSHMI SRINIVASAN COLLEGE OF ENGINEERING AND TECHNOLOGY

DHANALAKSHMI SRINIVASAN COLLEGE OF ENGINEERING AND TECHNOLOGY Dept/Sem: II CSE/03 DEPARTMENT OF ECE CS8351 DIGITAL PRINCIPLES AND SYSTEM DESIGN UNIT I BOOLEAN ALGEBRA AND LOGIC GATES PART A 1. How many

### CONTENTS CHAPTER 1: NUMBER SYSTEM. Foreword...(vii) Preface... (ix) Acknowledgement... (xi) About the Author...(xxiii)

CONTENTS Foreword...(vii) Preface... (ix) Acknowledgement... (xi) About the Author...(xxiii) CHAPTER 1: NUMBER SYSTEM 1.1 Digital Electronics... 1 1.1.1 Introduction... 1 1.1.2 Advantages of Digital Systems...

### QUESTION BANK FOR TEST

CSCI 2121 Computer Organization and Assembly Language PRACTICE QUESTION BANK FOR TEST 1 Note: This represents a sample set. Please study all the topics from the lecture notes. Question 1. Multiple Choice

### (ii) Simplify and implement the following SOP function using NOR gates:

DHANALAKSHMI COLLEGE OF ENGINEERING DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING EE6301 DIGITAL LOGIC CIRCUITS UNIT I NUMBER SYSTEMS AND DIGITAL LOGIC FAMILIES PART A 1. How can an OR gate be

### SIR C.R.REDDY COLLEGE OF ENGINEERING, ELURU DEPARTMENT OF INFORMATION TECHNOLOGY LESSON PLAN

SIR C.R.REDDY COLLEGE OF ENGINEERING, ELURU DEPARTMENT OF INFORMATION TECHNOLOGY LESSON PLAN SUBJECT: CSE 3.1.1 COMPUTER NETWORKS CLASS: 3/4 B.Tech., I SEMESTER, A.Y.2017-18 INSTRUCTOR: V.GOPINATH Sir

### UNIT I BOOLEAN ALGEBRA AND COMBINATIONAL CIRCUITS PART-A (2 MARKS)

SUBJECT NAME: DIGITAL LOGIC CIRCUITS YEAR / SEM : II / III DEPARTMENT : EEE UNIT I BOOLEAN ALGEBRA AND COMBINATIONAL CIRCUITS 1. What is variable mapping? 2. Name the two canonical forms for Boolean algebra.

### DIRECTORATE OF TECHNICAL EDUCATION DIPLOMA IN ELECTRICAL AND ELECTRONICS ENGINEERING II YEAR M SCHEME IV SEMESTER.

DIRECTORATE OF TECHNICAL EDUCATION DIPLOMA IN ELECTRICAL AND ELECTRONICS ENGINEERING II YEAR M SCHEME IV SEMESTER 2015 2016 onwards DIGITAL ELECTRONICS CURRICULUM DEVELOPMENT CENTRE Curriculum Development

### PART B. 3. Minimize the following function using K-map and also verify through tabulation method. F (A, B, C, D) = +d (0, 3, 6, 10).

II B. Tech II Semester Regular Examinations, May/June 2015 SWITCHING THEORY AND LOGIC DESIGN (Com. to EEE, ECE, ECC, EIE.) Time: 3 hours Max. Marks: 70 Note: 1. Question Paper consists of two parts (Part-A

### SHRI ANGALAMMAN COLLEGE OF ENGINEERING. (An ISO 9001:2008 Certified Institution) SIRUGANOOR, TIRUCHIRAPPALLI

SHRI ANGALAMMAN COLLEGE OF ENGINEERING AND TECHNOLOGY (An ISO 9001:2008 Certified Institution) SIRUGANOOR, TIRUCHIRAPPALLI 621 105 DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING EC1201 DIGITAL

NADAR SARASWATHI COLLEGE OF ENGINEERING AND TECHNOLOGY Vadapudupatti, Theni-625531 Question Bank for the Units I to V SEMESTER BRANCH SUB CODE 3rd Semester B.E. / B.Tech. Electrical and Electronics Engineering

### Question Total Possible Test Score Total 100

Computer Engineering 2210 Final Name 11 problems, 100 points. Closed books, closed notes, no calculators. You would be wise to read all problems before beginning, note point values and difficulty of problems,

### CS6201-DIGITAL PRINCIPLE AND SYSTEM DESIGN I YEAR/II SEM PART-B UNIT-I BOOLEAN ALGEBRA AND LOGIC GATES.

CS6201-DIGITAL PRINCIPLE AND SYSTEM DESIGN I YEAR/II SEM PART-B UNIT-I BOOLEAN ALGEBRA AND LOGIC GATES. 1) Simplify the boolean function using tabulation method. F = (0, 1, 2, 8, 10, 11, 14, 15) List all

### MULTIMEDIA COLLEGE JALAN GURNEY KIRI KUALA LUMPUR

STUDENT IDENTIFICATION NO MULTIMEDIA COLLEGE JALAN GURNEY KIRI 54100 KUALA LUMPUR SECOND SEMESTER FINAL EXAMINATION, 2013/2014 SESSION ITC2223 COMPUTER ORGANIZATION & ARCHITECTURE DSEW-E-F 1/13 18 FEBRUARY

### SIR C.R.REDDY COLLEGE OF ENGINEERING, ELURU DEPARTMENT OF INFORMATION TECHNOLOGY LESSON PLAN

SIR C.R.REDDY COLLEGE OF ENGINEERING, ELURU DEPARTMENT OF INFORMATION TECHNOLOGY LESSON PLAN SUBJECT: IT 3.1.3 WEB TECHNOLOGY CLASS: III/IVB.Tech., I st SEMESTER, A.Y.2017-18 INSTRUCTOR: SATYANARAYANA

### 10EC33: DIGITAL ELECTRONICS QUESTION BANK

10EC33: DIGITAL ELECTRONICS Faculty: Dr.Bajarangbali E Examination QuestionS QUESTION BANK 1. Discuss canonical & standard forms of Boolean functions with an example. 2. Convert the following Boolean function

### SIR C.R.REDDY COLLEGE OF ENGINEERING, ELURU DEPARTMENT OF INFORMATION TECHNOLOGY LESSON PLAN

SIR C.R.REDDY COLLEGE OF ENGINEERING, ELURU DEPARTMENT OF INFORMATION TECHNOLOGY LESSON PLAN SUBJECT: IT 4.1.2 NETWORK PROTOCOLS CLASS: 4/4 B.Tech., I - SEMESTER, A.Y.2017-18 INSTRUCTOR: Sri N. Prasad

### DE Solution Set QP Code : 00904

DE Solution Set QP Code : 00904 1. Attempt any three of the following: 15 a. Define digital signal. (1M) With respect to digital signal explain the terms digits and bits.(2m) Also discuss active high and

### R.M.D. ENGINEERING COLLEGE R.S.M. Nagar, Kavaraipettai

L T P C R.M.D. ENGINEERING COLLEGE R.S.M. Nagar, Kavaraipettai- 601206 DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING EC8392 UNIT - I 3 0 0 3 OBJECTIVES: To present the Digital fundamentals, Boolean

### Switching Theory & Logic Design/Digital Logic Design Question Bank

Switching Theory & Logic Design/Digital Logic Design Question Bank UNIT I NUMBER SYSTEMS AND CODES 1. A 12-bit Hamming code word containing 8-bits of data and 4 parity bits is read from memory. What was

### Hours / 100 Marks Seat No.

17333 13141 3 Hours / 100 Seat No. Instructions (1) All Questions are Compulsory. (2) Answer each next main Question on a new page. (3) Illustrate your answers with neat sketches wherever necessary. (4)

### KINGS COLLEGE OF ENGINEERING DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING QUESTION BANK NAME OF THE SUBJECT: EE 2255 DIGITAL LOGIC CIRCUITS

KINGS COLLEGE OF ENGINEERING DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING QUESTION BANK NAME OF THE SUBJECT: EE 2255 DIGITAL LOGIC CIRCUITS YEAR / SEM: II / IV UNIT I BOOLEAN ALGEBRA AND COMBINATIONAL

### BHARATHIDASAN ENGINEERING COLLEGE Degree / Branch : B.E./ECE Year / Sem : II/ III Sub.Code / Name : EC6302/DIGITAL ELECTRONICS

BHARATHIDASAN ENGINEERING COLLEGE Degree / Branch : B.E./ECE Year / Sem : II/ III Sub.Code / Name : EC6302/DIGITAL ELECTRONICS FREQUENTLY ASKED QUESTIONS UNIT I MINIMIZATION TECHNIQUES AND LOGIC GATES

### Combinational Circuits

Combinational Circuits Combinational circuit consists of an interconnection of logic gates They react to their inputs and produce their outputs by transforming binary information n input binary variables

### Assignment (3-6) Boolean Algebra and Logic Simplification - General Questions

Assignment (3-6) Boolean Algebra and Logic Simplification - General Questions 1. Convert the following SOP expression to an equivalent POS expression. 2. Determine the values of A, B, C, and D that make

### Computer Architecture: Part III. First Semester 2013 Department of Computer Science Faculty of Science Chiang Mai University

Computer Architecture: Part III First Semester 2013 Department of Computer Science Faculty of Science Chiang Mai University Outline Decoders Multiplexers Registers Shift Registers Binary Counters Memory

### CS/IT DIGITAL LOGIC DESIGN

CS/IT 214 (CR) Total No. of Questions :09] [Total No. of Pages : 02 II/IV B.Tech. DEGREE EXAMINATIONS, DECEMBER- 2016 First Semester CS/IT DIGITAL LOGIC DESIGN Time: Three Hours 1. a) Flip-Flop Answer

### Digital Logic Design Exercises. Assignment 1

Assignment 1 For Exercises 1-5, match the following numbers with their definition A Number Natural number C Integer number D Negative number E Rational number 1 A unit of an abstract mathematical system

### TEACHING & EXAMINATION SCHEME For the Examination COMPUTER SCIENCE. B.Sc. Part-I

TEACHING & EXAMINATION SCHEME For the Examination -2015 COMPUTER SCIENCE THEORY B.Sc. Part-I CS.101 Paper I Computer Oriented Numerical Methods and FORTRAN Pd/W Exam. Max. (45mts.) Hours Marks 150 2 3

### Specifying logic functions

CSE4: Components and Design Techniques for Digital Systems Specifying logic functions Instructor: Mohsen Imani Slides from: Prof.Tajana Simunic and Dr.Pietro Mercati We have seen various concepts: Last

INDEX Absorption law, 31, 38 Acyclic graph, 35 tree, 36 Addition operators, in VHDL (VHSIC hardware description language), 192 Algebraic division, 105 AND gate, 48 49 Antisymmetric, 34 Applicable input

### 3. The high voltage level of a digital signal in positive logic is : a) 1 b) 0 c) either 1 or 0

1. The number of level in a digital signal is: a) one b) two c) four d) ten 2. A pure sine wave is : a) a digital signal b) analog signal c) can be digital or analog signal d) neither digital nor analog

### DIGITAL ELECTRONICS. Vayu Education of India

DIGITAL ELECTRONICS ARUN RANA Assistant Professor Department of Electronics & Communication Engineering Doon Valley Institute of Engineering & Technology Karnal, Haryana (An ISO 9001:2008 ) Vayu Education

### ELCT 501: Digital System Design

ELCT 501: Digital System Lecture 4: CAD tools (Continued) Dr. Mohamed Abd El Ghany, Basic VHDL Concept Via an Example Problem: write VHDL code for 1-bit adder 4-bit adder 2 1-bit adder Inputs: A (1 bit)

### DKT 122/3 DIGITAL SYSTEM 1

Company LOGO DKT 122/3 DIGITAL SYSTEM 1 BOOLEAN ALGEBRA (PART 2) Boolean Algebra Contents Boolean Operations & Expression Laws & Rules of Boolean algebra DeMorgan s Theorems Boolean analysis of logic circuits

### SWITCHING THEORY AND LOGIC CIRCUITS

SWITCHING THEORY AND LOGIC CIRCUITS COURSE OBJECTIVES. To understand the concepts and techniques associated with the number systems and codes 2. To understand the simplification methods (Boolean algebra

### ii) Do the following conversions: output is. (a) (101.10) 10 = (?) 2 i) Define X-NOR gate. (b) (10101) 2 = (?) Gray (2) /030832/31034

No. of Printed Pages : 4 Roll No.... rd 3 Sem. / ECE Subject : Digital Electronics - I SECTION-A Note: Very Short Answer type questions. Attempt any 15 parts. (15x2=30) Q.1 a) Define analog signal. b)

### Course Batch Semester Subject Code Subject Name. B.E-Marine Engineering B.E- ME-16 III UBEE307 Integrated Circuits

Course Batch Semester Subject Code Subject Name B.E-Marine Engineering B.E- ME-16 III UBEE307 Integrated Circuits Part-A 1 Define De-Morgan's theorem. 2 Convert the following hexadecimal number to decimal

### 1. Mark the correct statement(s)

1. Mark the correct statement(s) 1.1 A theorem in Boolean algebra: a) Can easily be proved by e.g. logic induction b) Is a logical statement that is assumed to be true, c) Can be contradicted by another

### Hours / 100 Marks Seat No.

17320 21718 3 Hours / 100 Seat No. Instructions (1) All Questions are Compulsory. (2) Answer each next main Question on a new page. (3) Figures to the right indicate full marks. (4) Assume suitable data,

### Recitation Session 6

Recitation Session 6 CSE341 Computer Organization University at Buffalo radhakri@buffalo.edu March 11, 2016 CSE341 Computer Organization Recitation Session 6 1/26 Recitation Session Outline 1 Overview

### LSN 4 Boolean Algebra & Logic Simplification. ECT 224 Digital Computer Fundamentals. Department of Engineering Technology

LSN 4 Boolean Algebra & Logic Simplification Department of Engineering Technology LSN 4 Key Terms Variable: a symbol used to represent a logic quantity Compliment: the inverse of a variable Literal: a

### EE292: Fundamentals of ECE

EE292: Fundamentals of ECE Fall 2012 TTh 10:00-11:15 SEB 1242 Lecture 22 121115 http://www.ee.unlv.edu/~b1morris/ee292/ 2 Outline Review Binary Number Representation Binary Arithmetic Combinatorial Logic

### DIGITAL ELECTRONICS. P41l 3 HOURS

UNIVERSITY OF SWAZILAND FACUL TY OF SCIENCE AND ENGINEERING DEPARTMENT OF PHYSICS MAIN EXAMINATION 2015/16 TITLE OF PAPER: COURSE NUMBER: TIME ALLOWED: INSTRUCTIONS: DIGITAL ELECTRONICS P41l 3 HOURS ANSWER

### LOGIC DESIGN. Dr. Mahmoud Abo_elfetouh

LOGIC DESIGN Dr. Mahmoud Abo_elfetouh Course objectives This course provides you with a basic understanding of what digital devices are, how they operate, and how they can be designed to perform useful

### Midterm Exam Review. CS 2420 :: Fall 2016 Molly O'Neil

Midterm Exam Review CS 2420 :: Fall 2016 Molly O'Neil Midterm Exam Thursday, October 20 In class, pencil & paper exam Closed book, closed notes, no cell phones or calculators, clean desk 20% of your final

### GATE CSE. GATE CSE Book. November 2016 GATE CSE

GATE CSE GATE CSE Book November 2016 GATE CSE Preface This book is made thanks to the effort of GATE CSE members and Praneeth who made most of the latex notes for GATE CSE. Remaining work of completing

### Combinational Logic Circuits

Combinational Logic Circuits By Dr. M. Hebaishy Digital Logic Design Ch- Rem.!) Types of Logic Circuits Combinational Logic Memoryless Outputs determined by current values of inputs Sequential Logic Has

### Department of Computer Science University of Peshawar UNDERGTRADUATE CURRICULUM BCS

Department of Computer Science University of Peshawar UNDERGTRADUATE CURRICULUM BCS Code: BCS231 Credit Hours: 3 Digital Logic Design Numbering Systems a) Number Representation, Conversion, and Arithmetic

### EE 8351 Digital Logic Circuits Ms.J.Jayaudhaya, ASP/EEE

EE 8351 Digital Logic Circuits Ms.J.Jayaudhaya, ASP/EEE 1 Logic circuits for digital systems may be combinational or sequential. A combinational circuit consists of input variables, logic gates, and output

### 2.6 BOOLEAN FUNCTIONS

2.6 BOOLEAN FUNCTIONS Binary variables have two values, either 0 or 1. A Boolean function is an expression formed with binary variables, the two binary operators AND and OR, one unary operator NOT, parentheses

### MGU-BCA-205- Second Sem- Core VI- Fundamentals of Digital Systems- MCQ s. 2. Why the decimal number system is also called as positional number system?

MGU-BCA-205- Second Sem- Core VI- Fundamentals of Digital Systems- MCQ s Unit-1 Number Systems 1. What does a decimal number represents? A. Quality B. Quantity C. Position D. None of the above 2. Why the

### 1. Draw general diagram of computer showing different logical components (3)

Tutorial 1 1. Draw general diagram of computer showing different logical components (3) 2. List at least three input devices (1.5) 3. List any three output devices (1.5) 4. Fill the blank cells of the

### Chap.3 3. Chap reduces the complexity required to represent the schematic diagram of a circuit Library

3.1 Combinational Circuits 2 Chap 3. logic circuits for digital systems: combinational vs sequential Combinational Logic Design Combinational Circuit (Chap 3) outputs are determined by the present applied

### II/IV B.Tech (Regular/Supplementary) DEGREE EXAMINATION. Discrete Mathematical Structures. Answer ONE question from each unit.

14CS IT302 November,2016 II/IV B.Tech (Regular/Supplementary) DEGREE EXAMINATION Common for CSE & IT Discrete Mathematical Structures (4X12=48 Marks) 1. Answer all questions (1X12=12 Marks) a (Pv~P) is

### SCHEME OF EXAMINATION FOR B.Sc.(COMPUTER SCIENCE) SEMESTER SYSTEM (Regular Course) w.e.f Scheme for B.Sc.-I. Semester-I. Internal Assessment

SCHEME OF EXAMINATION FOR B.Sc.(COMPUTER SCIENCE) SEMESTER SYSTEM (Regular Course) w.e.f. 2013-14 Scheme for B.Sc.-I Sr. No. Paper 1 Paper-I Computer And Programming Fundamentals Semester-I Internal Assessment

### Systems Programming. Lecture 2 Review of Computer Architecture I

Systems Programming www.atomicrhubarb.com/systems Lecture 2 Review of Computer Architecture I In The Book Patt & Patel Chapter 1,2,3 (review) Outline Binary Bit Numbering Logical operations 2's complement

### ECE 2030B 1:00pm Computer Engineering Spring problems, 5 pages Exam Two 10 March 2010

Instructions: This is a closed book, closed note exam. Calculators are not permitted. If you have a question, raise your hand and I will come to you. Please work the exam in pencil and do not separate

### 2. (a) Compare the characteristics of a floppy disk and a hard disk. (b) Discuss in detail memory interleaving. [8+7]

Code No: A109211202 R09 Set No. 2 1. (a) Explain the purpose of the following registers: i. IR ii. PC iii. MDR iv. MAR. (b) Explain with an example the steps in subtraction of two n-digit unsigned numbers.

### ENEL 353: Digital Circuits Midterm Examination

NAME: SECTION: L01: Norm Bartley, ST 143 L02: Steve Norman, ST 145 When you start the test, please repeat your name and section, and add your U of C ID number at the bottom of the last page. Instructions:

### ELCT201: DIGITAL LOGIC DESIGN

ELCT201: DIGITAL LOGIC DESIGN Dr. Eng. Haitham Omran, haitham.omran@guc.edu.eg Dr. Eng. Wassim Alexan, wassim.joseph@guc.edu.eg Lecture 3 Following the slides of Dr. Ahmed H. Madian ذو الحجة 1438 ه Winter

### CS8803: Advanced Digital Design for Embedded Hardware

CS883: Advanced Digital Design for Embedded Hardware Lecture 2: Boolean Algebra, Gate Network, and Combinational Blocks Instructor: Sung Kyu Lim (limsk@ece.gatech.edu) Website: http://users.ece.gatech.edu/limsk/course/cs883

### Gate Level Minimization Map Method

Gate Level Minimization Map Method Complexity of hardware implementation is directly related to the complexity of the algebraic expression Truth table representation of a function is unique Algebraically

### EEE130 Digital Electronics I Lecture #4_1

EEE130 Digital Electronics I Lecture #4_1 - Boolean Algebra and Logic Simplification - By Dr. Shahrel A. Suandi 4-6 Standard Forms of Boolean Expressions There are two standard forms: Sum-of-products form

### St.MARTIN S ENGINEERING COLLEGE Dhulapally, Secunderabad

St.MARTIN S ENGINEERING COLLEGE Dhulapally, Secunderabad-500 014 Subject: Digital Design Using Verilog Hdl Class : ECE-II Group A (Short Answer Questions) UNIT-I 1 Define verilog HDL? 2 List levels of

### MLR Institute of Technology

MLR Institute of Technology Laxma Reddy Avenue, Dundigal, Quthbullapur (M), Hyderabad 500 043 Course Name Course Code Class Branch ELECTRONICS AND COMMUNICATIONS ENGINEERING QUESTION BANK : DIGITAL DESIGN

### Digital Design Using Digilent FPGA Boards -- Verilog / Active-HDL Edition

Digital Design Using Digilent FPGA Boards -- Verilog / Active-HDL Edition Table of Contents 1. Introduction to Digital Logic 1 1.1 Background 1 1.2 Digital Logic 5 1.3 Verilog 8 2. Basic Logic Gates 9

### CHAPTER 9 MULTIPLEXERS, DECODERS, AND PROGRAMMABLE LOGIC DEVICES

CHAPTER 9 MULTIPLEXERS, DECODERS, AND PROGRAMMABLE LOGIC DEVICES This chapter in the book includes: Objectives Study Guide 9.1 Introduction 9.2 Multiplexers 9.3 Three-State Buffers 9.4 Decoders and Encoders