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1 Serial : LS2_EE_S_Microprocessors_2688 Delhi Noida Bhopal Hyderabad Jaipur Lucknow Indore Pune Bhubaneswar Kolkata Patna Web: info@madeeasy.in Ph: CLASS TEST 28-9 ELECTRICAL ENGINEERING Subject : Microprocessor Date of test : 26/8/28 Answer Key. (c) 7. (d) 3. (d) 9. (d) 25. (d) 2. (d) 8. (d) 4. (b) 2. (d) 26. (a) 3. (b) 9. (b) 5. (a) 2. (d) 27. (c) 4. (a). (d) 6. (b) 22. (c) 28. (a) 5. (a). (a) 7. (b) 23. (d) 29. (b) 6. (b) 2. (c) 8. (a) 24. (d) 3. (d)

2 CT-28 EE Microprocessor 7 Detailed Explanations. (c) TRAP is also called as RST 4.5 Vector address = (4.5 8) = (36) = (24) H = (24) H. TRAP is a positive edge triggered and level triggered interrupt. RST 6.5 is a level triggered interrupt with third highest priority. INTR is a level triggered interrupt. 2. (d) 3. (b) LDA 75 H// Load the contents in location 75 H to accumulator CMA//Complement accumulator ( A ) INR A// Increment A by one ( A + ) STA 75 H// Store contents of accumulator to memory locaton 75 H HLT// Halt the program Contents in location 75 H are two s complemented. [A] = [B] = ADD B INR A S Z AC P CY INR doesn t effect carry flag. 4. (a) Using tristate buffer, a number of devices can transmit information enabling one device at a time. 5. (a) If the register hold minus five in two s compliment from then in arithmetic shift left the contents of the register shall be Initial Register content = ( 5) in 2 s compliment form After shift left = ( ) in 2 s comliment form It is found that the register contents is multiplied by two after logical shift left, left operation. Hence, arithmetic shift left operation is same as logical shift operation. 6. (b) An instruction cycle consists of several machine cycles. Hence, option (b) is correct.

3 8 Electrical Engineering 8. (d) 8C + 7E A H H H CY = (A) =A H. (a) LXI SP, 9 ; SP 9 LXI H, 5D ; HL 5D PUSH H ; SP = SP 2 = 8FFE POP PSW ; Pop the contents 5D onto PSW register. PSW = accumulator + status register PSW = 5D Status Register = S Z AC P CY 2. (c) IO/M RD WR D D MEM RD D 2 MEM WR D 3 D 4 D 5 I/O RD D 6 I/O WR D 7 3. (d) CY A: x x x x After execution of RRC 4 time A: x x x x Which is equivalent to dividing by () 2 or (b) Pointers (HL pair) can t be used to access I/O mapped I/O. Indirect addressing is not possible. When ALE signal goes high multiplexed bus is used as address bus and when it goes low multiplexed bus is used as data bus. For I/O mapped I/O instructions are fewer e.g. IN, OUT. But for memory mapped I/O instructions are more e.g., ADD M, MOV M, A etc.

4 CT-28 EE Microprocessor 9 5. (a) The chip select lines A 4 to A 8 will be set to for chip select. A 5 is do not care since it is not connected to chip select so it can be either or. So, address range will be 6. (b) Initial address Final address A 5 A 4 A 3 A 2 A A A 9 A 8 A 7 or or A 6 A 5 A 4 A 3 A 2 A A So, address range can be (7F) H to (7FFF) H or (FF) H to (FFFF) H but checking from the option (7F) H to (7FFF) H. IO/M is high so its IO operation. WR goes low so its a write operation. Hence (b). 7. (b) Machine cycles of OUT 2 H are Opcode fetch, memory read (For stored address) and I/O write. 8. (a) Hence, RD = 2 ; WR = ; ALE = 3. CC : CFFF : A 5 A A A A A A A A A A A A A A A chip select For active low chip select signal, the output of NAND gate should be low. Now, the output of NAND gate becomes low only when all inputs are high. Hence, for the given address range all the inputs of NAND should be A A A2 A3 A4 A (d) LXI B, 27 H ; loads BC pair with 27 H with 2 H B; 7 H C MVI A, 8F H ; moves 8 FH to A MVI C, 68 H ; moves 68 H to C SUB C ; subtract contents of C from A and store result in A. 8 FH 68 H 27 H ANI OFH ; OFH is ANDed with contents of A(ie. 27 H) and result is stored in A. A(27 H) : OFH : A = 7H STAX B ; stores the contents of A (ie. 7H) at address stored in BC pair (ie. 27 H) HLT ; Halts the execution of program. So, content of memory location 27 H after execution of program are 7 H.

5 Electrical Engineering 2. (d) Handshaking is used in asynchronous data transfer between microprocessor and I/O devices and DMA is used for direct data transfer between memory and I/O device. Interrupting is used for giving restart instruction from I/O devices. 2. (d) XRA M : It is a byte instruction, uses indirect addressing mode and requires two machine cycles (OP + MR). 7T-states are required. : -byte instruction, one machine cycle and 4T-states are required. STC LHLD 6 bit address : It is a 3-byte instruction, require 5 machine cycles (OP + MR + MR + MR + MR) & 6 T-states DAD R P : It is a -byte instruction, require 3 machine cycles and T-states 22. (c) Program counter (PC) is a 6-bit special purpose register which stores the address of next instruction to be executed or next byte to be fetched from memory. It is incremented automatically after fetching each byte from the memory. 23. (d) starting address= H ending address = 26 H size of memory = (26 ) H + H =6 H = 48 bytes 25. (d) LDA 2C H [3T states] executes faster than LXI 2C H MOV A,M which has 7T states. 26. (a) Given, number of T-states in each machine cycle = 3 No. of T-states required in 4 machine cycles = 2 One T state is precisely equal to one time period of clock signal. So, time of one T-state is: T = 3 µ s Time of 2 T-state = 2 T = 2 = 4 µs (c) The instruction Push B store the contents of BC at stack. The POP PSW instruction copy the contents of BC in to PSW. The contents of register C will be copied into flag register. D = = carry flag, D 6 = = zero flag.

6 CT-28 EE Microprocessor 28. (a) This program multiply Bytel by. Hence content of A will be 46H. 7H = 7, 7 = 7, 7 = 46H. 29. (b) Instructions in the programe and 2 mask the lower order address and not the higher order address. ANI OFH; A AND OFH A ANA B; A AND B A 3. (d) For enabling the decoder, output of NAND should be low and output of NAND gate is low when the address lines A 3 to A 5 are high. And for generation of chip select signal the output line Y 5 of decoder should be selected. Line Y 5 is selected when address lines A =. A = and A 2 = So, for the selection of given RAM, A =, A =, A 2 =, A 3 =, A 4 =, A 5 = Hence, address range will be as follows. A 5 A4 A3 A2 A A A9 A8 A7 A6 A5 A4 A3 A2 A A = F4 = F7FF Decoder enable Chip Select

Delhi Noida Bhopal Hyderabad Jaipur Lucknow Indore Pune Bhubaneswar Kolkata Patna Web: Ph:

Serial : 01. ND_EE_NW_Microprocessors_150718 Delhi Noida Bhopal Hyderabad Jaipur Lucknow Indore Pune Bhubaneswar Kolkata Patna Web: E-mail: info@madeeasy.in Ph: 011-45124612 CLASS TEST 2018-19 ELECTRICAL