Chapter 4 Arithmetic
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1 Computer Eng 1 (ECE290) Chapter 4 Arithmetic Functions and Circuits HOANG Trang Reference: 2008 Pearson Education, Inc. Lecture note of Prof.Donna J.Brown
2 Overview Binary adders Half and full adders Ripple carry and carry lookahead adders Binary subtraction Binary adder-subtractors Signed binary numbers Signed binary addition and subtraction ti Overflow HOANG Trang Reference: Lecture note of Prof.D.J.Brown & Chapter 4 2
3 Half-Adder = = = 1 Simple Binary Addition Zero plus zero equals zero Zero plus one equals one One plus zero equals one 1+1= One plus one equals zero with a carry of one HOANG Trang Reference: Lecture note of Prof.D.J.Brown & Chapter 4 3
4 Half-Adder HOANG Trang Reference: Lecture note of Prof.D.J.Brown & Chapter 4 4
5 Five Implementations: Half-Adder We can derive following sets of equations for a half- adder: (a) S X Y X Y C X Y (b) S (X Y) (X Y) C X Y (c) S ( C X Y ) C X Y (d) S (X Y) C C (X Y) (e) S X Y C X Y (a), (b), and (e) are SOP, POS, and XOR implementations i for S. In (c), the C function is used as a term in the AND- NOR implementation of S, and in (d), the C function is used in a POS term for S. HOANG Trang Reference: Lecture note of Prof.D.J.Brown & Chapter 4 5
6 Implementations: Half-Adder The most common half adder implementation is: X (e) Y S S X Y C X Y C A NAND only implementation is: S (X Y) C C ( ( X Y) ))) X C S CMOS Y HOANG Trang Reference: Lecture note of Prof.D.J.Brown & Chapter 4 6
7 NAND gate: behaviorial, transistor, layout O <= NOT ( A1 AND B1); Boolean Equation Transistor Mask HOANG Trang Reference: Lecture note of Prof.D.J.Brown & Chapter 4 7
8 Full-Adder HOANG Trang Reference: Lecture note of Prof.D.J.Brown & Chapter 4 8
9 Full-Adder Full adder from two half-adder adder circuits HOANG Trang Reference: Lecture note of Prof.D.J.Brown & Chapter 4 9
10 Adder: behavior, netlist, transistor, layout Behavioral model Structural model 28 transitors for 1 Full Adder HOANG Trang Reference: Lecture note of Prof.D.J.Brown & Chapter 4 10
11 Parallel Binary Adders Two-bit parallel binary adder HOANG Trang Reference: Lecture note of Prof.D.J.Brown & Chapter 4 11
12 Parallel Binary Adders Four-bit parallel binary adder iteractive HOANG Trang Reference: Lecture note of Prof.D.J.Brown & Chapter 4 12
13 4-bit Ripple-Carry Binary Adder A four-bit Ripple Carry Adder made from four 1-bit Full Adders: B 3 A 3 B 2 A 2 B 1 A 1 B 0 A 0 FA C 3 C 2 C 1 FA FA FA C 0 C 4 S 3 S 2 S 1 S 0 HOANG Trang Reference: Lecture note of Prof.D.J.Brown & Chapter 4 13
14 Unsigned Subtraction Algorithm: M (minuend) N (subtrahend) (n-bit number) M N: no end borrow, and the result is a nonnegative number and correct. N > M: end borrow occurs and the difference M N + 2 n and a minus sign is appended to the result ( ) 0011 Examples: HOANG Trang Reference: Lecture note of Prof.D.J.Brown & Chapter 4 14
15 Unsigned Subtraction (continued) The subtraction (2 n N): is the 2 s complement of fn To do both unsigned addition and unsigned A subtraction requires: Quite complex! Goal: Shared simpler logic for both addition and subtraction => Introduce complements as an approach Binary adder Subtract/Add Borrow Complement 0 1 S Quadruple 2-to-1 multiplexer B Binary subtractor Selective 2's complementer HOANG Trang Reference: Lecture note of Prof.D.J.Brown & Chapter 4 15 Result
16 Sign-magnitude representation Leftmost bit is sign bit: 0 positive 1 negative Ex: 6-bit representation (n=6) Example: +13: : Disadvantages of sign-magnitude: 1. Hard to do arithmetic (addition is hard) 2. Two representation of 0: +0 and -0 Largest number: (+31) (2 n -1) Smallest number: (-31) -(2 n -1) HOANG Trang Reference: Lecture note of Prof.D.J.Brown & Chapter 4 16
17 4-bit sign-magnitude representation HOANG Trang Reference: Lecture note of Prof.D.J.Brown & Chapter 4 17
18 4-bit 2 s complement representation HOANG Trang Reference: Lecture note of Prof.D.J.Brown & Chapter 4 18
19 4-bit representation Problem: 0: 2 representations NICE HOANG Trang Reference: Lecture note of Prof.D.J.Brown & Chapter 4 19
20 3-bit representation n=3 Number Sign -Mag. 1's Comp. 2's Comp HOANG Trang Reference: Lecture note of Prof.D.J.Brown & Chapter 4 20
21 2 s Complement Representation: X-> -X? Given: an n-bit number X in 2 s complement form Goal: Representation X in 2 s complement form? Example: n=5; X=01101 (2 s complement form) Method 1: take the 1 s complement of X and ADD 1 X= HOANG Trang Reference: Lecture note of Prof.D.J.Brown & Chapter 4 21
22 2 s Complement Representation: X-> -X? Method 2: compute: 2 n -X Method 3: complement all bits to the left of the least significant ifi t1(l (leaving other bits unchanged) X=01101 (+13) => -X=10011 (-13) X=10100 (-12) => -X=01100 (+12) HOANG Trang Reference: Lecture note of Prof.D.J.Brown & Chapter 4 22
23 2 s Complement Representation: X-> -X? Method 4: The n-bit 2 s complement representation is i ht d d ith l ft tbit f i ht 2 n-1 a weighted code with leftmost bit of weight - 2 X=1010 => X=-8+2=-6 HOANG Trang Reference: Lecture note of Prof.D.J.Brown & Chapter 4 23
24 2 s Complement Addition/Subtraction Given numbers X and Y in 2 s complement form 1. To ADD : Y+X: do ordinary binary 2. To SUBSTRACT: Y-X: compute (-X) and ADD Y+ (-X) (-10) (-13) (3) HOANG Trang Reference: Lecture note of Prof.D.J.Brown & Chapter 4 24
25 2 s Complement Adder/Subtractor How to design? + before we design, the Adder/Subtractor -> check that: we can design each seperately Design Adder: How to design? Design Substractor Answer: black box: would be like a nice girl. Oh, NO! HOANG Trang Reference: Lecture note of Prof.D.J.Brown & Chapter 4 25
26 2 s Complement Adder/Subtractor Subtraction can be done by addition of the 2's Complement. 1. Complement each bit (1's Complement.) 2. Add 1 to the result. For k = 1, subtract, the 2 s complement of B is formed by using XORs to form the 1 s comp and adding the 1 applied to C 0. For k = 0, add, B is passed through unchanged C 4 B 3 A 3 B 2 A 2 B 1 A 1 B 0 A 0 C 3 C 2 C 1 C 0 FA FA FA FA S 3 S 2 S 1 S 0 k HOANG Trang Reference: Lecture note of Prof.D.J.Brown & Chapter 4 26
27 Overflow Detection Overflow occurs if n + 1 bits are required to contain the result from an n-bit addition or subtraction n=5 bit: -16 -> 15 HOANG Trang Reference: Lecture note of Prof.D.J.Brown & Chapter 4 27
28 Overflow Detection: when it occurs? Intuition (clearly) that: Overflow can occur for: Addition of two operands with the same sign Add 2 positive and get a negative Add 2 negative and get a positive Subtraction of operands with different signs Ideal: simple implementation C n XOR C n-1 = 1 HOANG Trang Reference: Lecture note of Prof.D.J.Brown & Chapter 4 28
29 Overflow Detection: when it occurs? Consider all possibility overflow C n XOR C n-1 HOANG Trang Reference: Lecture note of Prof.D.J.Brown & Chapter 4 29
30 Overflow Detection: when it occurs? HOANG Trang Reference: Lecture note of Prof.D.J.Brown & Chapter 4 30
31 An Arithmetic Unit (AU) HOANG Trang Reference: Lecture note of Prof.D.J.Brown & Chapter 4 31
32 A Logic Unit (LU) HOANG Trang Reference: Lecture note of Prof.D.J.Brown & Chapter 4 32
33 An Arithmetic/Logic Unit (ALU) (very popular in micro-controller, computer, processor) HOANG Trang Reference: Lecture note of Prof.D.J.Brown & Chapter 4 33
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