CSE140L: Components and Design Techniques for Digital Systems Lab. Verilog HDL. Instructor: Mohsen Imani UC San Diego. Source: Eric Crabill, Xilinx

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1 CSE4L: Components and Design Techniques for Digital Systems Lab Verilog HDL Instructor: Mohsen Imani UC San Diego Source: Eric Crabill, Xilinx

2 System Tasks The $ sign denotes Verilog system tasks, there are a large number of these, most useful being: $display( The value of a is %b, a); Used in procedural blocks for text output. The %b is the value format (binary, in this case ) $monitor Similar to display, but executes every time one of its parameter changes $finish; Used to finish the simulation. Use when your stimulus and response testing is done. $stop; Similar to $finish, but doesn t exit simulation.

3 Blocking/Non-Blocking Assignments Blocking assignments (X=A) completes the assignment before continuing on to next statement Non-blocking assignments (X<=A) completes in zero time and doesn t change the value of the target until a blocking point (delay/wait) is encountered Watch out for assignments with delay! Examples follow. 3

4 Blocking Delay Unintended Behavior 4

5 Assign Delay Correct Behavior 5

6 Nonblocking delay expected behavior 6 Source:

7 Driving a simulation through a testbench module testbench (x, y); output x, y; reg [:] cnt; 2-bit vector initial begin cnt = ; repeat (4) begin # cnt = cnt + ; $display ("@ time=%d, x=%b, y=%b, cnt=%b", $time, x, y, cnt); end # $finish; end initial block executed only once at start of simulation print to a console assign x = cnt[]; assign y = cnt[]; endmodule directive to stop simulation

8 Delay Control Generation of clock and resets in testbench: reg rst, clk; initial begin end always begin end rst = b; // this happens once at time zero // starts off as asserted at time zero #; // wait for time units rst = b; clk = b; // deassert the rst signal // this repeats forever // starts off as high at time zero #25; // wait for half period clk = b; // clock goes low #25; // wait for half period

9 case Statements in Verilog What does the following piece of code represent? always_comb begin case ( sel_i ) 2 d : z_o = a_i; 2 d : z_o = b_i; 2 d2 : z_o = c_i; 2 d3 : z_o = d_i; default : z_o = bx; endcase end endmodule always_comb implicitly assume a complete sensitivity list. It s the same as: Useful for homework 3 9

10 Synchronous design: specify a clock When writing a module with a clock signal, use behavioral description with the clock in the sensitivity list clk) begin Useful for homework 3 // do stuff end

11 Generate a clock in a testbench When testing a module with multiple inputs, make sure you start from a known condition How to generate a clock signal in a testbench? initial begin end always // initialize your module inputs here #5 clk =! clk; Useful for homework 3

12 CSE4L: Components and Design Techniques for Digital Systems 2

13 Circuit Delay Transistors have instrinsic resistance and capacitance Signals take time to propagate from the input to the output of a gate Sometimes delays are labeled in circuit drawings 3

14 -Bit & Multi-bit Adders Half Adder A C out + S B C out Full Adder A + S B C in Types of multi-bit adders Ripple-carry (slow) Carry-lookahead (faster) Two-level logic adder (even faster) A B C out S = A B C out = AB S C in A B C out S C out Symbol A B N N + S N C in S = A B C in C out = AB + AC in + BC in

15 Ripple-Carry Adder Chain -bit adders together Carry ripples through entire chain Disadvantage: slow A 3 B 3 A 3 B 3 A B A B C out + C + 3 C 29 C + C + C in S 3 S 3 S S Ripple-carry adder delay t ripple = Nt FA where t FA is the delay of a full adder

16 Two-level Logic Adder No matter how many inputs you have, look at the truth table, convert to Kmap, apply the algorithm for two-level logic minimization Very fast adder, but. Beyond 8 inputs, a shockingly large amount of gates! Number of gates increases exponentially Ripple carry adder Carry-lookahead adder (next slide) FAST Two-level logic adder COMPLEX

17 Carry-lookahead adders c4 c3 c2 c c a3 a2 a a b3 b2 b b s3 s2 s s Carries First operand Second operand

18 Carry-lookahead adders Adder with propagate (P) and generate (G) outputs: Ci+ = Ai Bi + Ci (Ai xor Bi) Generate Propagate Ci+ = Gi + Ci Pi The carry at some level is equal to if either the generate signal is equal to one or if the propagate and the previous carry are both

19 Full-Adder Two scenarios (actually three) When would we always generate a carry-out based on the A i and B i inputs alone When would we always propagate the carry? When would we actually kill the carry (meaning there is guaranteed to be no carry-out)? a i b i C out Full Adder C in s i 9

20 Carry-Lookahead Adder Applying these equations for a 4-bit adder we can solve for the multiple carry-in bits: C = G + P C C 2 = G + P C = G + P (G + P C ) = G + P G + P P C C 3 = G 2 + P 2 C 2 = G 2 + P 2 G + P 2 P G + P 2 P P C C 4 = G 3 + P 3 C 3 = G 3 + P 3 G 2 + P 3 P 2 G + P 3 P 2 P G + P 3 P 2 P P C

21 Ref: Dan Earnst Carry-Lookahead Adder

22 Carry-Lookahead Adder A[5-2]B[5-2] C2 4-bit Adder P G 4 A [-8] B[-8] C 4-bit Adder 8 P G 4 A[7-4] B[7-4] C 4-bit Adder 4 P G 4 A[3-] B[3-] C 4-bit Adder P G 4 S[5-2] S[-8] S[7-4] S[3-] P 3 G 3 C 3 P 2 G 2 C 2 P G C P G C C 6 C 4 Lookahead Carry Unit P3- G3- C 4 bit adders with internal carry look-ahead P and G logic Second level carry-lookahead unit creates the GROUP P and G signals

23 Carry-lookahead adders Example: 4-bit CLA adder c = G + P c c2 = G + P c c3 = G2 + P2 c2 c4 = G3 + P3 c3 Gi = ai bi Pi = ai xor bi generate propagate All G and P are immediately available, but c are not. So you need to make substitutions: c = G + P c c2 = G + P (G + P c) c3 = G2 + P2 c2 c4 = G3 + P3 c3 = G + PG + PPc = (derive at home) = (derive at home) 23

CSE140L: Components and Design Techniques for Digital Systems Lab. Verilog HDL. Instructor: Mohsen Imani UC San Diego. Source: Eric Crabill, Xilinx

CSE140L: Components and Design Techniques for Digital Systems Lab Verilog HDL Instructor: Mohsen Imani UC San Diego Source: Eric Crabill, Xilinx 1 Hardware description languages Used to describe & model