Luleå University of Technology Kurskod SMD152 Datum Skrivtid

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1 Luleå University of Technology Kurskod SMD152 Datum Skrivtid Manual synthesis (10 p, 2 p each) Here you are given five different VHDL models. Your task is to draw the schematics of the VHDL models. Your schematics may only contain: Antal uppgifter: 6 Max poäng: 44 Lärare: Jonas Thor Telefon: Tillåtna hjälpmedel: Enbart skrivmaterial. En VHDL syntax guide är bifogad med tentamen Allowed material Only writing material. A VHDL syntax guide is included in the exam. AND gates with n inputs ( n 2) OR gates with n inputs XOR gates with n inputs Inverters Multiplexers Tri-state buffers Positive edge triggered D-type flip-flops, with or without synchronous or asynchronous clear or set. The flip-flops may also have a clock enable input (CE). Transparent data latches You may write in English or in Swedish. Clearly mark the names of the inputs/outputs as indicated in the VHDL source. a) library ieee; entity One_a is Clk : in std_logic; A, B : in std_logic; Y1, Y2 : out std_logic); end One_a; architecture RTL of One_a is signal I : std_logic; process(clk) variable V : std_logic; if rising_edge(clk) then V := A or B; I <= not (A and B); Y1 <= V; Y2 <= I xor V; 2

2 b) library ieee; entity One_b is Clk : in std_logic; A, B : in std_logic; Y : out std_logic); end One_b; architecture RTL of One_b is signal I1, I2 : std_logic; Y <= A and not(i2); process(clk) if rising_edge(clk) then I2 <= I1 and B; I1 <= A; c) library ieee; entity One_c is Clk, Reset : in std_logic; A, B : in std_logic; Output : out std_logic); end One_c; architecture RTL of One_c is type State is (S0, S1); signal PState, NState : State; process(clk, Reset) if Reset = '1' then PState <= S0; elsif rising_edge(clk) then PState <= NState; process(pstate, A, B) case PState is when S0 => Output <= '0'; if A = '1' then NState <= S1; NState <= S0; when S1 => Output <= '1'; if B = '1' then NState <= S0; NState <= S1; end case; 3 4

3 d) library ieee; use ieee.numeric_std.all; entity One_d Clk, Reset : in std_logic; E : in std_logic; P : out std_logic); end One_d; architecture RTL of One_d is signal C : unsigned(1 downto 0); process(clk) if rising_edge(clk) then if Reset = '1' then -- Note! specify if this reset is C <= "00"; -- synchronous or asynchronous elsif E = '1' then C <= ('0' & C(0)) + 1; P <= C(1) and E; e) library ieee; entity One_e is port ( A, B : in std_logic; X, Y : out std_logic); end One_e; architecture Proc of One_e is signal I : std_logic; P1 : process (A, B) if A = B then I <= A; I <= B; end process P1; P2 : process (I) if I = '1' then Y <= A; Y <= B; end process P2; X <= I; end Proc; 5 6

4 2 Timing diagram (4 p) 3 Finite State Machine (8p) A finite state machine is specified by the ASM chart and VHDL entity shown below. When the FSM is asynchronously reset it enters the S0 state. library ieee; entity FSM is Clk, Reset : in std_logic; A : in std_logic; F, Y : out std_logic); end FSM; Given the data path above fill in the values of the R output in the timing diagram below. The data path consists of positive edge triggered flip-flops, an adder, a multiplier and a multiplexer. a) Write synthesizable VHDL code that implements the state machine described in the ASM chart. b) Derive a gate level implementation of the FSM. Clearly show your work in each step solving this problem. 7 8

5 5 FPGA design flow (6p) 4 Behavioural synthesis (10 points, 2 point each) You have an algorithmic description of a computational structure given by the source code listed below. library ieee; entity Exam is A, B, C, D : in integer; X, Y : out integer); end Exam; architecture Algorithm of Exam is X <= (A**2)*B + A*C; -- A*A*B + A*C Y <= B*C + B*D + D; end Algorithm; Notice the description is purely combinational. Your task is to perform behavioural synthesis and transfer the algorithm to a synchronous sequential computational structure. a) Derive a scheduled data flow graph with the constraint that only one adder and one multiplier is available. Minimize the latency. Explain the design flow for a programmable logic device from design entry to device configuration. Draw a flow chart of the design flow and give written explanation of each design step. You may assume that you use VHDL for design entry and that your target device is an FPGA just like in the labs. You should explain at least the following tasks/processes; placement, routing, synthesis, functional simulation, timing simulation, static timing analysis and bit stream generation. Note! One of the mentioned processes was not performed in the lab, which one was that? 6 D Flip-flop (6p) Explain the following timing parameters for a positive edge triggered D flip-flop: Setup time Hold time Clock to output delay Use a timing diagram to illustrate the timing parameters. Also explain the term metastability. When can metastability occur and why? What can be done to reduce the chance of a system failure when a metastability event occurs? b) Allocate functional units and registers for the scheduled data flow graph derived in a). Each input should be assigned a register. Name the registers RA, RB, RC and RD. This means that the in the first clock cycle input A should be assigned to RA (RAA) and so on. Minimize the number of registers. You should assume that the registers have a clock enable input signal. The outputs X and Y should be registered as well but these registers may be shared with other registers. c) Draw the data path of design based on your solution of b). Make sure to label registers and show all necessary control signals, such as multiplexer select signals and clock enable signals. d) Draw the ASM chart using register transfer notation. The first state is given by this state box RA A RB B RC C RD B e) Draw the detailed ASM chart showing when the control signals are activated. 9 10

6 1 a) A B i_1 D Q i D Q Y1 Y1 1 e) Optimized implementation. Not necessary for full score, solution only needs to be functional correct. Most have solved this problem with two muxes + one xor (or xnor) gate which is ok. Clk D Q Y2 v_1 y2_1 Y2 1 b) 2) B Clk A D i1 Q i2_1 D i2 Q Y Y 1 c) The thick wire is just one bit. Clk A B Reset 0 1 nstate[0] D Q R pstate[0] Output 1 d) A 1-bit counter with registered carry output + an AND gate 11 12

7 Problem 3. a) VHDL source library ieee; entity FSM is Clk, Reset : in std_logic; A : in std_logic; F, Y : out std_logic); end FSM; architecture RTL of FSM is type State_type is (S0, S1, S2); signal PState, NState : State_type; process(clk, Reset) if Reset = '1' then PState <= S0; elsif rising_edge(clk) then PState <= NState; process(a, PState) F <= '0'; Y <= '0'; case PState is when S0 => if A = '1' then NState <= S1; F <= '1'; NState <= S0; when S1 => NState <= S2; Y <= '1'; when S2 => if A = '1' then NState <= S1; NState <= S2; end case; 3 b) We will solve this problem using one-hot encoding. Other encodings are valid as well. One-hot encoding Lets name the state vector Q. The encoding is chosen so that S0 Q= 001, S1 Q= 010 and S2 Q = 100. The main advantage of one-hot encoding is that only one bit needs to be examined in order to check if we are in a particular state. The state transition and output table is shown below Q A Q+ Y F By inspection we can determine the next state and output equations Q 0 + = Q 0 A Q 1 + = Q 2 A + Q 0 A = A(Q 2 + Q 0 ) Q2+ = Q 1 + Q 2 A Y = Q 1 F = Q 0 A This is also simple to derive directly from the ASM chart. The above equations can in words be translated to Next state is S0 if current state is S0 and A=0 Next state is S1 if current state is S2 and A=1 or if current state is S0 and A=1 Next state is S2 if current state is S1 or if current state is S1 or if current state is S2 and A = 0 Output Y is set in state S1 Output F is set if current state is S0 and A=1 The schematics is not shown, should be trivial. Note! This is not a safe implementation. What happens if there is a bit error in the state vector? A safe FSM would detect non-valid states and perform appropriate actions

8 4 a) 4 c) 4 b) 4 d-e) 15 16