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1 M A S S A C H U S E T T S I N S T I T U T E O F T E C H N O L O G Y DEPARTMENT OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCE 6.S084 Computation Structures Spring 2018 Practice Quiz #1 1 /8_ 2 /12 3 /12 4 /25 5 /12 6 /15 7 /16 Name Athena login name Score Recitation section o WF 11, (Silvina) o WF 1, (Andy) o WF 12, (Silvina) o None (pick up quiz in 32-G846) Please enter your name, Athena login name, and recitation section above. Enter your answers in the spaces provided below. You can use the extra white space and the backs of the pages for scratch work. Problem 1. Two s Complement Arithmetic (8 points) (A) (4 points) Express both 37 and 11 in 8-bit two s complement as well as hexadecimal. 37 in 8-bit two s complement (0b): 37 in hexadecimal (0x): 11 in 8-bit two s complement (0b): 11 in hexadecimal (0x): (B) (2 points) Compute in 8-bit two s complement in 8-bit two s complement (0b): (C) (2 points) Compute in 8-bit two s complement in 8-bit two s complement (0b): 6.S084 Spring of 10 - Practice Quiz #1

2 Problem 2. Boolean Expressions (12 points) (A) (8 points) Simplify the following Boolean expressions by finding a minimal sum-of-products expression for each one. (Note: These expressions can be reduced into a minimal SOP by repeatedly applying the Boolean algebra properties we saw in lecture.) 1. a b c + a b c 2. a b + c d e f g (B) (4 points) There are some Boolean expressions for which no assignment of values to variables can produce True (e.g., a a). These Boolean expressions are said to be non-satisfiable. Is the following Boolean expression satisfiable? If the expression is satisfiable, give an assignment to variables that makes the expression evaluate to True. If the expression is nonsatisfiable, explain why. x + yz yx + z (zy + x) 6.S084 Spring of 10 - Practice Quiz #1

3 Problem 3. Organic Logic (12 points) A B Slime Gate C Organic Logic, Inc., is a Cambridge startup that has developed an interesting device built using unidentified organic sludge from the depths of the Charles river; they would like to use it to perform logic functions. Their device, termed a Slime Gate, has two inputs A and B, and one output C (in addition to power and ground connections): With a 3 volt power supply, they have noted that Slime Gates reliably behave as follows: The output C is always in the range 0 volts < C < 3 volts. When either (or both) A or B has been less than 1 volt for 2 nanoseconds or more, the voltage at C is greater than 2.5 volts. When A and B have both been more than 2 volts for at least a nanosecond, C carries a voltage of less than 0.5 volts. Aside from the above constraints, the voltage at C is generally unpredictable; it varies widely between individual Slime Gate devices. As an O.L.I. consultant, you have proposed the following circuit as an inverter: X Y (A) (6 points) Give logic representation parameters yielding 0.5-volt noise margins and for which the above diagram depicts a valid inverter. Inverter V OL : ; V IL : ; V IH : ; V OH : (B) (4 points) Find the propagation delay of this inverter. t PD : ns (C) (2 points) Suppose the Slime Gate is used as a 2-input logic gate in this same family, as shown to the right. What, if any, function of P and Q is represented by the output R? P Q 2-input gate R Boolean function of P and Q, or None : 6.S084 Spring of 10 - Practice Quiz #1

4 Problem 4. Combinational Logic in BSV (25 points) (A) (4 points) The following BSV function f performs a specific arithmetic operation on n-bit operands a and b. We want the function f2 to implement f in a single line of code. Fill in the blank with an expression of the form a operation b to make f2 equivalent to f. function Bit#(1) f(bit#(n) a, Bit#(n) b); Bit#(TAdd#(n,1)) x = 0; for (Integer i = 0; i < valueof(n); i = i+1) begin x[i+1] = x[i] (a[i] & ~b[i]) (~a[i] & b[i]); end return x[valueof(n)]; endfunction function Bit#(1) f2(bit#(n) a, Bit#(n) b); return ( )? 1 : 0; endfunction (B) (4 points) Write the truth table for the combinational device described by this function. function Bit#(2) f(bit#(1) a, Bit#(1) b, Bit#(1) c); return (case ({a, b}) 0: ((c==1)? {a, b} : 3); 1: {c, a}; 2: 1; 3: (2 b01 ^ {c, c}); endcase); endfunction a b c out[1] out[0] S084 Spring of 10 - Practice Quiz #1

5 (C) (6 points) The following BSV function f performs a specific arithmetic operation on n-bit operands a and b. We want the function f2 to implement f in a single line of code. Fill in the blank with an expression of the form a operation b to make f2 equivalent to f. function Bit#(1) f(bit#(n) a, Bit#(n) b); Bit#(TAdd#(n,1)) x = 0; for (Integer i = 0; i < valueof(n); i = i+1) begin x[i+1] = (case ({a[i], b[i]}) 2 b00: x[i]; 2 b01: 0; 2 b10: 1; 2 b11: x[i]; endcase); end return x[valueof(n)]; endfunction function Bit#(1) f2(bit#(n) a, Bit#(n) b); return ( )? 1 : 0; endfunction (D) (5 points) For n = 2, manually compile the BSV function f above into a combinational circuit. You can use inverters, AND, OR, XOR, NAND, and NOR gates, as well as multiplexers. Please label the inputs and outputs bit by bit (a[0], a[1], b[0], b[1], out[0], and out[1]). You do not need to optimize or simplify the circuit. 6.S084 Spring of 10 - Practice Quiz #1

6 (E) (6 points) Show that half-adder devices can be used to implement any combinational circuit by implementing an inverter, an AND gate, and an OR gate using only half-adder gates. Make sure to clearly label the output. You may tie inputs to 1 or 0 if necessary, and may use multiple half-adder gates. A C B HA S C = A & B; S = A ^ B; Logic diagram of inverter implementation using half-adders: Logic diagram of AND gate implementation using half-adders: Logic diagram of OR gate implementation using half-adders: 6.S084 Spring of 10 - Practice Quiz #1

7 Problem 5. Sequential Logic Timing (12 points) (A) (4 points) Find the propagation delay (t PD ) and contamination delay (t CD ) of the circuit shown below, using the t CD and t PD information for the gate components shown in the table below. Gate t CD t PD INV 0.1ns 1.0ns NAND2 0.2ns 1.5ns NAND3 0.3ns 1.8ns XOR2 0.6ns 2.5ns t CD = ns t PD = ns (B) (8 points) The circuit above implements a full subtractor (FS), which, similar to a full adder, computes X Y Bin in two s complement. You combine two FS circuits as shown below to implement a two-bit self-decrementing counter. The table below shows the timing specifications for the D registers and FS circuit (not the same implementation as above!). Find the maximum value for the D register s hold time, t HOLD, and the minimum clock cycle period, t CLK, for which the circuit operates correctly. D reg FS t CD 0.2ns 0.1ns t PD 0.3ns 4.1ns t SETUP 1.2ns t HOLD??? maximum value for t HOLD : ns minimum value for t CLK : ns 6.S084 Spring of 10 - Practice Quiz #1

8 Problem 6. Sequential Logic in BSV (15 points) The following code implements a simple sequential circuit as a module that computes a function over a series of steps. Read the code and answer the questions about it below. interface Diff; method Action start(bit#(32) a, Bit#(32) b); method Bit#(32) get1; method Bit#(32) get2; endinterface module mkdiff(diff); Reg#(Bit#(32)) x <- mkreg(0); Reg#(Bit#(32)) y <- mkreg(0); Reg#(Bit#(32)) i <- mkreg(0); rule step(y > 0); if (x > y-1) begin x <= x-y; i <= i+1; end else begin y <= 0; end endrule method Action start(bit#(32) a, Bit#(32) b) if (y==0); i <= 0; x <= a; y <= b; endmethod method Bit#(32) get1 if (y == 0); return i; endmethod method Bit#(32) get2 if (y == 0); return x; endmethod endmodule (A) (3 points) If at the beginning of step the values in the register are x = 21, y = 8, i = 4, what are the values after rule step runs once? 1. x = 2. y = 3. i = 6.S084 Spring of 10 - Practice Quiz #1

9 (B) (6 points) If start is called with values a = 14 and b = 3, what will the output of get1 and get2 be when it is ready? 1. Return value of get1() = 2. Return value of get2() = (C) (6 points) Describe in words what function this circuit computes when the module is started with start(a, b). 1. What does the return value of get1() correspond to when it is ready? 2. What does the return value of get2() correspond to when it is ready? 6.S084 Spring of 10 - Practice Quiz #1

10 Problem 7. CMOS Logic (16 points) You are trying to select pulldowns for several 3- and 4-input CMOS gate designs. You can choose from seven different pulldowns, given names PD1 through PD7, diagrammed below: You can choose which inputs or constants (GND, VDD) are connected to each nfet, allowing these pulldowns to be used in various ways to build gates with various numbers of inputs. For each of the following 3- and 4-input Boolean functions, choose the appropriate pulldown design, i.e., the one which, properly connected, implements that gate s pulldown network. If multiple pulldowns can be used, choose the one that uses the minimum number of transistors. This may require applying DeMorgan s Law or minimizing the logic equation first. If none of the above pulldowns meets this goal, write NONE. (A) F a, b, c = a + (b c) Choice or NONE: (B) F a, b, c = a + (b c) Choice or NONE: (C) F a, b, c = a b + c Choice or NONE: (D) F a, b, c, d = a + b(c + d) Choice or NONE: END OF PRACTICE QUIZ 1! 6.S084 Spring of 10 - Practice Quiz #1