CPE 335 Computer Organization. MIPS Arithmetic Part I. Content from Chapter 3 and Appendix B
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1 CPE 335 Computer Organization MIPS Arithmetic Part I Content from Chapter 3 and Appendix B Dr. Iyad Jafar Adatped from Dr. Gheith Abandah Slides CPE 232 MIPS Arithmetic 1
2 MIPS Number Representations Computer programs calculate both positive a negative numbers. One approach is to use the sign and magnitude representation. Use separate bit for the sign Shortcomings: Where to put the sign? Positive and negative zeros! Need complex hardware to perform arithmetic Alternative: use the complement notation; specifically the two s complement! CPE 232 MIPS Arithmetic 2
3 MIPS Number Representations 32-bit signed numbers (2 s complement): MSB two = 0 ten two = + 1 ten maxint two = + 2,147,483,646 ten two = + 2,147,483,647 ten two = 2,147,483,648 8 ten two = 2,147,483,647 ten two = 2 ten minint two = 1 ten two LSB If we use N bits to represent a signed number using two s complement, then The maximum number is 2 N-1 1 The minimum number is -2 N-1 ten CPE 232 MIPS Arithmetic 3
4 Review: 2 s Complement Binary Representation Negate 1011 and add a complement all the bits -2 3 = -(2 3-1) = = 2 sc binary decimal CPE 232 MIPS Arithmetic 4
5 MIPS Number Representations Converting signed numbers to decimal ( ) 2 = -1*2^7 + 1*2^6 + 1*2^5 + 1*2^4 + 1*2^3 + 2^2 + 1*2^1 + 0*2^0 = -2 Converting <32-bit values into 32-bit values Sign Extension: copy the most significant bit (the sign bit) into the empty bits > > Zero Extension: place zeros in the extended bits > > CPE 232 MIPS Arithmetic 5
6 MIPS Number Representation How to negate a number? There e is no special instruction Suppose we have x = - x sub $s0, $zero, $s0 This is in contrast to complementing a number! x = ~x Bitwise complement of x There is no single instruction Recall the XOR operation x 1 = x addi $t0, $zero, -1 xor $s0, $s0, $t0 CPE 232 MIPS Arithmetic 6
7 MIPS Instruction Support for Signed numbers add vs addu, sub vs subu, and addi vs addiu Addition/subtraction o is performed ed in the same manner Is overflow exception generated? lb vs lbu lb sign extend the additional bits lbu zero extend the additional bits slt vs sltu and slti vs sltiu slt and slti perform signed comparison with a constant sltu and sltiu perform unsigned comparison with a constant CPE 232 MIPS Arithmetic 7
8 Example Suppose that $s0 = $s1 = then what is the value stored in $t0 in the following cases : slt $t0, $s1, $s0 Signed comparison $t0 = 0 since $s1 = 1 and $s0 = -1 sltu $t0, $s1, $s0 Unsigned comparison $t0 = 1 since $s1 = 1 and $s0 = 2^32-1 CPE 232 MIPS Arithmetic 8
9 Binary Addition Binary addition is simple! = 0 and 0 carry = 1 and 0 carry = 1 and 0 carry = 0 and 1 carry Add corresponding bits and propagate the carry, if any, to the next bit. CPE 232 MIPS Arithmetic 9
10 Review: A Full Adder A B carry_in A B carry_in carry_out S bit Full Adder carry_out S S=A B carry_in carry_out = A&B A&carry_in B&carry_in How can we use it to build a 32-bit adder? How can we modify it easily to build an adder/subtractor? CPE 232 MIPS Arithmetic 10
11 A 32-bit Ripple Carry Adder/Subtractor Remember 2 s complement is just complement all the bits control (0=add,1=sub) B 0 if control = 0,!B 0 if control = 1 B 0 add a 1 in the least significant ifi bit Subtraction is equivalent to adding the negative of the number add/sub B 0 B 1 B 2 A 0 A 1 A 2 c 0 =carry_in 1-bit FA S 0 c 1 1-bit FA S 1 c 2 1-bit FA S 2... c 3 c 31 1-bit FA S 31 A B 31 B c 32=carry_ out CPE 232 MIPS Arithmetic 11 A 31
12 Overflow Detection Overflow: the result is too large to represent in 32 bits Overflow occurs when adding two positives yields a negative or, adding two negatives gives a positive or, subtract a negative from a positive gives a negative or, subtract a positive from a negative gives a positive On your own: Prove that you can detect overflow by: Carry into MSB XOR Carry out of MSB, ex for 4 bit signed numbers CPE 232 MIPS Arithmetic 12
13 Improving Addition Performance The ripple-carry adder is slow We have to wait until the carry is propagated to the final position in order to read out the addition/subtraction result. Carry generation is associated with two levels of gates at each bit position (Co i = A i B i + A i Cin i + B i Cin i ). Total delay = gate delay x 2 x number of bits Example: 16 bit adder delay is 32 delay units CPE 232 MIPS Arithmetic 13
14 Carry-Lookahead Adder Need fast way to find the carry Design a separate unit that computes carries for different bits in parallel! CPE 232 MIPS Arithmetic 14
15 Carry-Lookahead Adder In a 4 bit adder, the equations of the carries are c1 = (b0. c0) + (a0. c0) + (a0. b0) c2 = (b1. c1) + (a1. c1) + (a1. b1) c3 = (b2. c2) + (a2. c2) + (a2. b2) c4 = (b3. c3) + (a3. c3) + (a3. b3) By substitution c2 = (a1. a0. b0) + (a1. a0. c0) + (a1. b0. c0) + (b1. a0. b0) + (b1. a0. c0 ) + (b1. b0. c0) + (a1.b1) c3 = (b2. a1. a0. b0) + (b2. a1. a0. c0) + (b2. a1. b0. c0) + (b2. b1. a0. b0) + (b2. b1. a0. c0 ) + (b2. b1. b0. c0) + (b2. a1. b1) + (a2. a1. a0. b0) + (a2. a1. a0. c0) + (a2. a1. b0. c0) + (a2. b1. a0. b0) + (a2. b1. a0. c0 ) + (a2. b1. b0. c0) + (a2. a1. b1) + (a2.b2) c4 = Imagine the equation if the adder is 32 bits??. CPE 232 MIPS Arithmetic 15
16 Carry-Lookahead Adder We can reduce the logic cost by simple simplification ci+1 = (bi. ci) + (ai. ci) + (ai. bi) = (ai. bi) + (ai + bi). ci = gi + pi. ci gi : carry generate pi : carry propagate Carry equations for 4 bit adder c1 = g0 + p0. c0 c2 = g1 + (p1. g0) + (p1. p0. c0) c3 = g2 + (p2. g1) + (p2. p1. g0) + (p2. p1. p0. c0) c4 = g3 + (p3. g2) + (p3. p2. g1) + (p3. p2. p1. g0) + (p3. p2. p1. p0. c0) Delay to generate c4 is 3 gate delay Still cost is high for larger adders!!! CPE 232 MIPS Arithmetic 16
17 Carry-Lookahead Adder- Second level of Abstraction Assume 16 bit adder that consists of 4 single 4-bit adders with carry-lookahead implementation c4 g0 p0 c0 c3 c2 c1 a0 b bit carry lookahead adder s0 CPE 232 MIPS Arithmetic 17
18 Carry-Lookahead Adder- Second level of Abstraction Need to generate the carry propagate and generate signals at higher level Think of each 4-bit adder block as a single unit that can either generate or propagate a carry. Super propagate signals P0 = p3 p2 p1 p0 P1 = p7 p6 p5 p4 P2 = p11 p10 p9 p8 P3 = p15 p14 p13 p12 Super generate signals G0 = g3+(p3 g2)+(p3 p2 g1)+(p3 p2 p1 g0) G1 = g7+(p7 g6)+(p7 p6 g5)+(p7 p6 p5 g4) G2 = g11+(p11 g10)+(p11 p10 g9)+(p11 p10 p9 g8) G3 = g15+(p15 g14)+(p15 p14 g13)+(p15 p14 p13 g12) CPE 232 MIPS Arithmetic 18
19 Carry-Lookahead Adder- Second level of Abstraction Carry signal at higher levels are C1 = G0 + (P0 c0) C2 = G1 + (P1 G0) + (P1 P0 c0) P0 0) C3 = G2 + (P2 G1) + (P2 P1 G0) + (P2 P1 P0 c0) C4 = G3 + (P3 G2) + (P3 P2 G1) + (P3 P2 P1 G0) + (P3 P2 P1 P0 c0) Each supper carry signal is two level implementation in terms of Pi and Gi Pi is one level of gates while Gi is two and expressed in terms of pi and gi pi and gi are one level of gates Total delay is = 5 16-bit CLA is 5 times faster than the 16-bit ripple carry adder CPE 232 MIPS Arithmetic 19
20 MIPS Arithmetic Logic Unit (ALU) Need to support the logic operations Need to support arithmetic operations Need to support the set-on-less-than instruction Need to support test for equality Immediates are sign or zero extended outside the ALU with wiring (i.e., no logic needed) CPE 232 MIPS Arithmetic 20
21 MIPS Arithmetic Logic Unit (ALU) Must support the Arithmetic/Logic operations of the ISA add, addi, addiu, addu sub, subu, neg mult, multu, div, divu sqrt and, andi, nor, or, ori, xor, xori beq, bne, slt, slti, sltiu, sltu A B zero ovf 1 1 ALU 32 4 m (operation) result With special handling for sign extend addi, addiu andi, ori, xori, slti, sltiu zero extend lbu, addiu, sltiu no overflow detected addu, addiu, subu, multu, divu, sltiu, sltu CPE 232 MIPS Arithmetic 21
22 MIPS Arithmetic Logic Unit (ALU) Start with 1-bit ALU Can easily implement the logic instruction AND and OR since they map directly to hardware. Perform all possible operations in parallel then use a multiplexer to select the result based on the instruction type. The control signal Operation is issued by the control unit CPE 232 MIPS Arithmetic 22
23 MIPS Arithmetic Logic Unit (ALU) For the ADD instruction, use a full adder. The CarryIn input will be used later on to expand the 1-bit ALU to n- Bit. Expand the multiplexer inputs and select lines to accommodate for the add instruction. CPE 232 MIPS Arithmetic 23
24 MIPS Arithmetic Logic Unit (ALU) For the subtract instruction, we use 2 s complement subtraction. We need to complement B and add 1. Define Binvert to select between B and B and set CarryIn to 1. CPE 232 MIPS Arithmetic 24
25 MIPS Arithmetic Logic Unit (ALU) Combine Binvert and CarryIn in one signal Bnegate since they have the same value all the time. CPE 232 MIPS Arithmetic 25
26 MIPS Arithmetic Logic Unit (ALU) Supporting the NOR operation requires no separate gate. Use Demorgan s theorem and the AND gate and define the signal Ainvert (A+B) = A.B CPE 232 MIPS Arithmetic 26
27 MIPS Arithmetic Logic Unit (ALU) Constructing 32-bit ALU Replicate the 1-bit ALU and connect the CarryIn signals All cells receive the same control signals CPE 232 MIPS Arithmetic 27
28 MIPS Arithmetic Logic Unit (ALU) Supporting the SLT instruction Expand the multiplexer for one more input. Subtract the two registers and feed the sign bit (the result of bit 31) back to the least significant bit. The slt input of the multiplexer is connected to 0 for remaining bits. CPE 232 MIPS Arithmetic 28 LSB MSB
29 MIPS Arithmetic Logic Unit (ALU) 32-bit ALU with SLT support. CPE 232 MIPS Arithmetic 29
30 MIPS Arithmetic Logic Unit (ALU) Supporting conditional branch instructions Need to generate a signal that indicates whether the result is zero or not. Simply OR the result bits and take the complement. This signal will be used to make the selection between the branch address and the PC. Example on using the Zero signal to select the address for BEQ instruction CPE 232 MIPS Arithmetic 30
31 MIPS Arithmetic Logic Unit (ALU) Final ALU with overflow detection CPE 232 MIPS Arithmetic 31
32 MIPS Arithmetic Logic Unit (ALU) Control signals values and corresponding operations Ainvert Bnegate Operation Instruction ti AND OR ADD SUB SLT NOR CPE 232 MIPS Arithmetic 32
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