# Combinational Devices and Boolean Algebra

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1 Combinational Devices and Boolean Algebra Silvina Hanono Wachman M.I.T. L02-1

2 6004.mit.edu Home: Announcements, course staff Course information: Lecture and recitation times and locations Course materials Summary of assignments, quizzes, and grading policy. Resources: Lecture slides, take-home problem, worksheets, solutions, and lecture videos. Additional resources Labs: Lab assignment handouts Builds: Automated build system [Username]: Your grades L02-2

3 The Digital Abstraction Different specifications for inputs and outputs Digital output: 0 V OL, 1 V OH Digital input: 0 V IL, 1 V IH V OL < V IL < V IH < V OH VALID INPUT REPRESENTATIONS Valid 0 V OL V IL Undefined V IH V OH Valid 1 volts NOISE MARGINS VALID OUTPUT REPRESENTATIONS A digital device accepts marginal inputs and provides unquestionable outputs (to leave room for noise). L02-3

4 Combinational Devices Static discipline A combinational device is a circuit element that has one or more digital inputs one or more digital outputs a functional specification that details the value of each output for every possible combination of valid input values a timing specification consisting (at a minimum) of a propagation delay (t PD ): an upper bound on the required time to produce valid, stable output values from an arbitrary set of valid, stable input values input A input B Output a 1 if at least 2 out of 3 of my inputs are a 1. Otherwise, output 0. output Y input C I will generate a valid output in no more than 2 minutes after seeing valid inputs L02-4

5 Composing Combinational Devices A set of interconnected elements is a combinational device if each circuit element is combinational every input is connected to exactly one output or to a constant (0 or 1) the circuit contains no directed cycles L02-5

6 Example: Is This a Combinational Device? A, B and C are combinational devices. Is the following circuit a combinational device? X Y A C W Z B Does it have digital inputs? Yes Does it have digital outputs? Yes Can you derive a functional description? W = f C (f A (X, Y), f B (f A (X, Y), Z)) Can you derive a t PD? t PD = t PD,A + t PD,B + t PD,C L02-6

7 Functional Specifications There are many ways to specify the function of a combinational device A B C If C is 0 then copy A to Y, otherwise copy B to Y Y We will use two systematic approaches: Truth tables enumerate the output values for all possible combinations of input values Boolean expressions are equations containing binary (0/1) variables and three operations: AND ( ), OR (+), and NOT (overbar) Y = ҧ C A + C B Truth Table C B A Y Any combinational function can be specified as a truth table or Boolean expression L02-7

8 Boolean Algebra Boolean algebra comprises Two elements, 0 and 1 Two binary operators, AND ( ) and OR (+) One unary operator, NOT (overbar) a b a b a b a+b a a All of Boolean algebra can be derived from the definitions of AND, OR, and NOT September 11, 2018 MIT Fall 2018 L02-8

9 Boolean Algebra Axioms Instead of using truth tables to define AND, OR, and NOT, we can derive all of Boolean algebra using a small set of axioms: identity a 1=a a+0=a null a 0=0 a+1=1 negation 0=1 1=0 Duality principle: If a Boolean expression is true, then replacing 0 1 and AND OR yields another expression that is true This principle holds for the axioms Holds for all expressions Halves the number of expressions you have to learn September 11, 2018 MIT Fall 2018 L02-9

10 Useful Boolean Algebra Properties Using the axioms, we can derive several useful properties to manipulate and simplify Boolean expressions: commutative a b = b a a+b = b+a associative a (b c) = (a b) c a+(b+c) = (a+b)+c distributive a (b+c) = a b+a c a+b c = (a+b) (a+c) complements a ഥa = 0 a+ഥa = 1 absorption a (a+b) = a a+a b = a reduction a b + a b ഥ = a (a+b) (a+ b) ഥ = a DeMorgan s Law a b = ഥa+ b ഥ a+b = ഥa b ഥ September 11, 2018 MIT Fall 2018 L02-10

11 Useful Boolean Algebra Properties Many of these properties are easy to remember because they match the ones for integer algebra, but be aware of the differences e.g., distributive property for Boolean + a+b c = (a+b) (a+c) does not hold for integer +! To familiarize yourself with the properties, we recommend that you simply prove them Example: DeMorgan s Law a b a b ഥa+ b ഥ September 11, 2018 MIT Fall 2018 L02-11

12 Equivalence and Normal Form Given a truth table, it is easy to derive an equivalent Boolean expression: write a sum of product terms where each term covers a single 1 in the truth table C B A Y Y =CBA+CBA+CBA+CBA This representation is called the function s normal form It is unique, but there may be simpler expressions Corollary: Boolean expressions can represent any combinational function L02-12

13 Logic Synthesis L02-13

14 From Boolean Algebra to Gates A logic diagram represents a Boolean expression as a circuit schematic with logic gates and wires Basic logic gates: A B AND Z = A B A B OR Z = A + B A Inverter Z = A We often use AND and OR gates with more than two inputs A B C D Z=A B C D AND, OR, and NOT are universal: They can implement any combinational function Why? September 11, 2018 MIT Fall 2018 L02-14

15 Straightforward Logic Synthesis We can implement any sum-of-products (SOP) Boolean expression with three levels of gates: 1. Inverters 2. ANDs 3. OR Y = CBA+CBA+CBA +CBA However, we can often implement the same function with fewer gates. This requires simplifying its Boolean expression to use fewer operations. L02-15

16 Boolean Simplification of SOPs A minimal sum-of-products is a sum-of-products expression that has the smallest possible number of AND and OR operators Unlike the normal form, it is not unique (a function may have multiple minimal SOPs) Minimal SOPs can be implemented with fewer gates Simple algebraic manipulation (using the properties we ve seen) is sufficient to minimize small expressions (3-4 variables) Y = CBA + CBA + CBA + CBA Y = CBA + CB + CBA Y = CA + reduction reduction More sophisticated techniques exist (e.g., K-maps), but we will not need them in this course L02-16 CB

17 Truth Tables with Don t Cares Another way to reveal simplification is to rewrite the truth table using don t cares (-- or X) to indicate when the value of a particular input is irrelevant in determining the value of the output. C B A Y C B A Y 0 X X X X 1 X X CA CB BA Note: Some input combinations (e.g., 000) are matched by more than one row in the don t care table. It would be a bug if all matching rows didn t specify the same output value! L02-17

18 Multi-Level Boolean Simplification We can often reduce the number of gates by using more logic levels than an SOP Find common subexpressions and factor them out into independent variables Example: F = A C + B C + A D + B D (minimal SOP) F = (A+B) C + (A+B) D X = A + B F = X C + X D A B C X D F Multi-level simplification has no well-defined optimum Adding levels may reduce gates but increase delay L02-18

19 Logic Optimization In practice, tools use Boolean simplification and other techniques to synthesize a circuit that meets certain area, delay, and power goals: High-level circuit specification (e.g., Boolean algebra, Bluespec) Standard cell library (set of gates and their physical characteristics) Synthesis tool Optimized circuit implementation (using standard cell library gates) Optimization goals (area/delay/power) September 11, 2018 MIT Fall 2018 L02-19

20 Other Common Gates XOR (Exclusive-OR) A B Z A B = ҧ A B + A തB Inverting logic A B NAND Z = A B A B NOR Z = A+ B September 11, 2018 MIT Fall 2018 L02-20

21 Universal Building Blocks NANDs and NORs are universal: = = = = = = Any logic function can be implemented using only NANDs (or, equivalently, NORs) September 11, 2018 MIT Fall 2018 L02-21

22 Standard Cell Library Library of gates and their physical characteristics Example: Gate Delay (ps) Area (μ 2 ) Inverter Buffer AND NAND OR NOR AND NAND OR Observations: 1. In current technology (CMOS), inverting gates are faster and smaller 2. Delay and area grow with number of inputs NOR September 11, 2018 MIT Fall 2018 L02-22

23 Design Tradeoffs: Delay vs Size AND4: t PD = 90 ps, size = 40μ 2 NAND4 + INV: t PD = 90 ps, size = 40μ 2 Demorgan s Laws: A B = A+ B A+ B = A B 2*NAND2 + NOR2: t PD = 1 NAND2 + NOR2 = 65 ps, size = 2 NAND2 + NOR2 = 46μ 2 L02-23

24 Example: Mapping a Circuit to a Standard Cell Library Find an implementation of a circuit, e.g., Using gates from a standard cell library, e.g., Area That optimizes for some goal, e.g., minimum area September 11, 2018 MIT Fall 2018 L02-24

25 Example: Mapping a Circuit to a Standard Cell Library Possible implementations: 7 NAND2 (3) = 21 5 INV (2) = 10 Total area cost: 31 2 INV = 4 2 NAND2 = 6 1 NAND3 = 4 1 NAND4 = 5 Total area cost: 19 September 11, 2018 MIT Fall 2018 L02-25

26 Logic Optimization Takeaways Synthesizing an optimized circuit is a very complex problem Boolean simplification Mapping to cell libraries with many gates Multidimensional tradeoffs (e.g., minimize area-delaypower product) Infeasible to do by hand for all but the smallest circuits! Instead, hardware designers write circuits in a hardware description language, and use a synthesis tool to derive optimized implementations L02-26

27 Summary Any combinational (Boolean) function can be specified by a truth table or a Boolean expression (binary literals and AND, OR, NOT, which form a Boolean algebra) Any combinational function can be expressed as a sumof-products (SOP) and implemented with three levels of logic gates (NOTs, ANDs, OR) Boolean simplification (finding a minimal SOP, multilevel simplification) results in simpler circuits There are MANY design tradeoffs in mapping Boolean functions to gates. We will use synthesis tools to find optimized circuit implementations L02-27

28 Take-Home Problem 1. Find a minimal SOP expression for the following Boolean (SOP) expression: ABC + ABC + ABC + ABC 2. Using the gates in slide #22, find an implementation of this minimal SOP that minimizes area. September 11, 2018 MIT Fall 2018 L02-28

29 Thank you! Next lecture: Describing combinational circuits in Bluespec L02-29

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