# EE 109L Review. Name: Solutions

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1 EE 9L Review Name: Solutions Closed Book / Score:. Short Answer (6 pts.) a. Storing temporary values in (memory / registers) is preferred due to the (increased / decreased) access time. b. True / False: A circuit whose VOL value is V can successfully communicate a logic '' to a circuit whose VIL is.5 V? c. A family of circuits have IOH=-2 ma, IOL = ma, IIH = -.2 ma and IIL =.25 ma. How many other inputs can a single output be successfully wired to ensure operation in any condition? When outputting logic '' ten gates (2mA/.2mA) can be connected but when outputting logic '' only 4 gates (ma/.25ma) can be connected. Thus 4 is the limit. d. The address bus of a new computer is 38-bits wide, approximately how many bytes of memory and I/O locations can the computer address? Show any work = 2 8 *2 3 = 256 GB 2. Integer Operations (2 pts). Perform the following hexadecimal operations and state whether OVerflow occurred. For subtraction, find the complement and add. a.) C 5 A B E C 5 A C E 2 b.) F B 4 B + 9 F A 8 signed ov: y /n signed ov: y /n unsigned ov: y /n unsigned ov: y /n

2 3. Adders ( pts.) Build a circuit that takes three, 3-bit unsigned numbers, X[2:], Y[2:], and Z[2:], as input and produces an output F = X + 4Y + 4Z. Note: In binary, multiplying by 4 = 2 simply requires appending two 's to the end of the number just as in decimal, multiplying by just means adding two 's (i.e. 937* = 937 in decimal). a.) How many bits are required for F? (2 pts.) Max = = 63 => 6-bits b.) The columns of addition are shown below. Implement the addition using a minimal number of 74LS283 4-bit adders. One has been drawn below. Add more as necessary. (8 pts.) x2 x x y2 y y + z2 z z Z2 Y2 Z Y Z Y X2 X X B3 A3 B2 A2 B A B A 4-bit Binary Adder (74LS283) C C4 S3 S2 S S F5 F4 F3 F2 F F

3 4. State Machine Design (Down Counter w/ Restart): Design a synchronous state machine circuit that implements a 2-bit down counter (i.e. counts,,,, ). The circuit has an external input, R (RESTART), that when should force the counter back to the state no matter what the current state is. As long as R stays, the counter should stay in the state. The circuit should also have one output Z. Z= when in the state and Z = otherwise. Let us use 4 states: S3 (initial state on reset) The count should be 2 = 3 S2 The count should be 2 = 2 S The count should be 2 = S The count should be 2 = a.) Complete the state diagram below by filling in all necessary transitions and the values of Z. On Reset (power on) R = R = R = S3 Z = R = S2 Z = S Z = S Z = R = R = b.) What is the minimum number of flip-flops required to implement this state machine? 2 Flip Flops c.) Complete the state transition/output table given below. (Note: We have provided the state assignment already). We have ordered the states in such a way to use gray code ordering, so take care when translating your state diagram to the transition/output table. Current State Next State Output R= R= State State ** State ** Z S S3 S3 S S S3 S3 S2 S3 S2 S S3

4 d.) Assume we will implement our circuit using D Flip-Flops. Use the K-Maps below to find minimal expressions for D, D, and Z. D Map D Map Z Map R R 2 3 Z = D = R + + D = R + e.) Show how to implement the initial state (power-on/reset state) by connecting the PRE (PRESET) and CLR inputs of the FF s appropriately. Assume the signal /RESET is available to you. You do not need to implement the next-state or output-function logic. RESET D D PRE CLR / RESET D D PRE CLR / CLK

5 f.) Using your design above draw the waveform for the sequence of states that the machine will go through and what the output will be for the given input sequence of X. Remember you are using positive edge-triggered devices. CLK RESET R Z 5. True / False a.) A 4-to- multiplexer requires at least 4 select lines: true / false FALSE b.) 3 separate 2-to- muxes can be used to build a single 4-to- mux: true / false TRUE c.) 5 flip-flops are required to implement a state machine with 5 states: true / false FALSE d.) In binary, performing X-Y can be performed by adding X to the 2 s complement of Y: true / false TRUE

6 6. Design a circuit takes a 2-bit, unsigned number A=(AA) and a -bit, unsigned number B=(B) as input and produces the output C = A B represented in the 2 s complement system. (25 pts.) a.) Complete the block diagram of this circuit by showing and labeling the inputs and outputs. Think how many output bits are required. (2 pts.) B A A C C C2 b.) Write out a truth table for this circuit. (8 pts.) A A B C2 C C c.) Find the minimal SOP expression for each bit of output by using the 3 K-Maps furnished below. Make sure to add the variable labels for the axes of each K-Map and add your gray code. Clearly indicate the minimal expressions you find for each output. (2 pts.) B AA B AA B AA C2 = A A B C = A A B + AA + AB C2 = AB + A B

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