Instruction Level Parallelism. ILP, Loop level Parallelism Dependences, Hazards Speculation, Branch prediction
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1 Instruction Level Parallelism ILP, Loop level Parallelism Dependences, Hazards Speculation, Branch prediction
2 Basic Block A straight line code sequence with no branches in except to the entry and no branches out except at the exit Loop: L.D F0, 0(R1) ADD.D F4, F0, F2 S.D F4, 0(R1) DADDUI R1, R1, #-8 BNE R1, R2, Loop L1: DADDUI R1, 0(R2) BEQZ R2, L1 LW R1, 0(R2)
3 ILP for (i=0; i<=999; i=i+1) x[i] = x[i] + a; Data Dependence Name Dependence Loop: L.D F0, 0(R1) ADD.D F4, F0, F2 S.D F4, 0(R1) DADDUI R1, R1, #-8 BNE R1, R2, Loop Name dependence antidependence, output dependence Register renaming Hazard ADD.D ADD.D F4, F0, F2 F4, F6, F8 Overlap during execution would change the order of access to the operand involved in the dependence.
4 Hazards Program Order ILP preserves program order only where it affects the outcome of the program Structural Hazards Resource conflicts Data Hazards RAW, WAW, WAR
5 Structural Hazard i1 i2 i3 i4 i5... MEM ID EX MEM WB MEM ID EX MEM WB MEM ID EX MEM WB MEM ID EX MEM WB MEM ID EX MEM WB HAZARD!!!
6 Data Hazard DADD DSUB AND OR XOR R1,R2,R3 R4,R1,R5 R6,R1,R7 R8,R1,R9 R10,R1,R11 Time (clock cycles) DADD IM REG ALU DM REG DSUB IM REG ALU DM REG AND IM REG ALU DM REG OR IM REG ALU DM XOR IM REG ALU
7 Avoiding Data Hazards Forwarding DADD DSUB AND OR XOR R1,R2,R3 R4,R1,R5 R6,R1,R7 R8,R1,R9 R10,R1,R11 Time (clock cycles) DADD IM REG ALU DM REG DSUB IM REG ALU DM REG AND IM REG ALU DM REG OR IM REG ALU DM XOR IM REG ALU
8 LD DSUB AND OR R1,0(R2) R4,R1,R5 R6,R1,R7 R8,R1,R9 Load Delay Slot The loaded value might not be available in the destination register for use by the instruction immediately following the load LOAD DELAY SLOT Time (clock cycles) LD IM REG ALU DM REG DSUB IM REG ALU DM REG AND IM REG ALU DM REG OR IM REG ALU DM
9 Cost of Stalls Data references = 40%. Ideal CPI=1. Processor with hazard is 1.1 times faster than the processor without hazard. Which processor is faster? Pipeline CPI = Ideal pipeline CPI + Structural stalls+ Data hazard stalls +Control stalls
10 Pipeline Scheduling Reorder the instructions of the program so that dependent instructions are far enough apart Done by the compiler, before the program runs: Static Instruction Scheduling Done by the hardware, when the program is running: Dynamic Instruction Scheduling
11 Pipeline Scheduling Original Program LW R3, 0(R1) ADDI R5, R3, 1 ADD R2, R2, R3 LW R13, 0(R11) ADD R12, R13, R3 stall stall Scheduled Code LW R3, 0(R1) LW R13, 0(R11) ADDI R5, R3, 1 ADD R2, R2, R3 ADD R12, R13, R3 Total Execution Cycles: 7 Total Execution Cycles: 5
12 Loop-level Parallelism Original Loop: Loop: L.D F0, 0(R1) ADD.D F4, F0, F2 S.D F4, 0(R1) DADDUI R1, R1, #-8 BNE R1, R2, Loop Loop: L.D F0, 0(R1) ADD.D F4, F0, F2 S.D F4, 0(R1) L.D F6, -8(R1) ADD.D F8, F2, F6 S.D F8, -8(R1) L.D F10, -16(R1) ADD.D F12, F2, F10 S.D F12, -16(R1) L.D F14, -24(R1) ADD.D F16, F2, F14 S.D F16, -24(R1) DADDUI R1, R1, #-32 BNE R1, R2, Loop U N R O L L E D L O O P
13 Loop Unrolling Instr producing result FP ALU op Instr using result Latency to avoid a stall Another FP ALU op FP ALU op Store Double 2 Load Double FP ALU op 1 Load Double Store double 0 Total Cycles: 27 cycles 3 Loop: L.D ADD.D S.D L.D ADD.D S.D L.D ADD.D S.D L.D ADD.D S.D F0, 0(R1) F4, F0, F2 F4, 0(R1) F6, -8(R1) F8, F2, F6 F8, -8(R1) F10, -16(R1) F12, F2, F10 F12, -16(R1) F14, -24(R1) F16, F2, F14 F16, -24(R1) DADDUI R1, R1, #-32 BNE R1, R2, Loop
14 Loop Unrolling Instr producing result FP ALU op Instr using result Latency to avoid a stall Another FP ALU op FP ALU op Store Double 2 Load Double FP ALU op 1 Load Double Store double 0 3 Loop: L.D L.D L.D L.D ADD.D ADD.D ADD.D ADD.D F0, 0(R1) F6, -8(R1) F10, -16(R1) F14, -24(R1) F4, F0, F2 F8, F2, F6 F12, F2, F10 F16, F2, F14 Total Cycles: 14 cycles S.D F4, 0(R1) S.D F8, -8(R1) DADDUI R1, R1, #-32 Code Size Register pressure S.D S.D BNE F12, 16(R1) F16, 8(R1) R1, R2, Loop
15 Exceptions Certain exceptional events that occur during program execution, handled by the processor hardware Control transfer to specific OS code based on the family of exception I/O device requests, System call, Breakpoint, Integer arithmetic overflow, FP arithmetic anomaly, Page fault, Undefined or unimplemented instruction, Hardware malfunctions, Power failure.
16 Exceptions Synchronous vs. Asynchronous User requested vs. Coerced User maskable vs. User non-maskable Within vs. Between instructions Save, and restore processor state restartable pipeline Resume vs. Terminate
17 Stopping and Restarting Execution Trap instruction, Turn off writes, Save PC, Save processor state, Exception handler, RFE Precise exceptions Pipeline stage IF ID EX MEM WB Problem exceptions occurring Page fault on IF, misaligned memory access; memory protection violation Undefined or illegal opcode Arithmetic exception Page fault on data fetch; misaligned memory access; memory protection violation None
18 Precise Exceptions LD IF ID EX MEM WB DADD IF ID EX MEM W B Exceptions at the same cycle Early exception by a later instruction Instruction Status Vector Check before commit
19 Control Dependences Program correctness Data flow and Exception behaviour Software Speculation Liveness DADDU BEQZ LW L1: R2, R3, R4 R2, L1 R1, 0(R2) DADDU R1, R2, R3 BEQZ R12, L1 DSUBU R4, R5, R6 DADDU R5, R4, R9 L1: OR R7, R8, R9 DADDU BEQZ DSUBU L1:... OR R1, R2, R3 R4, L1 R1, R5, R6 R7, R1, R8
20 Branch Hazards Time (clock cycles) Branch IF ID EX MEM WB Branch Successor Branch Successor + 1 Branch Successor + 2 IF IF ID EX MEM WB IF ID EX MEM WB IF ID EX MEM WB 1 stall cycle for every branch yields a performance loss of 10% to 30%!
21 Reducing Pipeline Branch Penalties Freeze the pipeline Static Prediction Predict Taken, Predict Untaken Fill Branch Delay Slot From the MIPS ISA Manual The transfer of control takes place only following the instruction immediately after the control transfer instruction Time (clock cycles) Branch IF ID EX MEM WB Branch Delay Slot Branch Successor Branch Successor + 1 IF ID EX MEM WB IF ID EX MEM WB IF ID EX MEM WB
22 Branch Delay Slot
23 Performance of Branch Schemes Speedup pipelining = Pipeline depth 1+ Pipeline stall cycles per instruction Stall cycles Branches = Branch frequency Branch penalty Speedup pipelining = Pipeline depth 1+ Branch frequency Branch penalty
24 Exception type I/O device request Classes of Exceptions Synchronous vs. Async User request vs. Coerced User maskable vs. nonmaskable Within vs. between instructions Resume vs. Terminate Async Coerced Nonmaskable Between Resume Invoke OS Sync User request Nonmaskable Between Resume Tracing Instruction Execution Sync User request User maskable Breakpoint Sync User request User maskable Arithmetic Overflow FP underflow or overflow Sync Coerced User maskable Sync Coerced User maskable Between Between Within Within Resume Resume Resume Resume Page fault Sync Coerced Nonmaskable Within Resume Undefined Instructions Hardware malfunctions Sync Coerced Nonmaskable Within Terminate Async Coerced Nonmaskable Within Terminate Power Failure Async Coerced Nonmaskable Within Terminate Smith and Pleszkun, Implementing precise interrupts in pipelined processors, IEEE Transactions on Computers, 37(5), 1998.
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