There are only 16 possible 2-input gates Let s examine all of them. Some we already know, others are just silly.

Size: px
Start display at page:

Download "There are only 16 possible 2-input gates Let s examine all of them. Some we already know, others are just silly."

Transcription

1 ll the Gates There are only 6 possible 2-input gates Let s examine all of them. Some we already know, others are just silly. Do we really need all of these gates? How many of these gates can be implemented using a single MOS gate? N-FETs can only pull the ouput to, and only if one or more of their inputs is a. P-FETs can only pull the ouput to, and only if one or more of their inputs is a. Nope! Once we realize that we can describe all of them using just NOT, followed by ND, followed by OR.

2 omposing gates to build others Let s start with a couple of basics, ND and OR. Each can be constructed using a pair of MOS gates, ND is just NND with an inverter, and OR is just NOR with an inverted output. ND OR y These two gates are particularly important. Using them will allows us to develop a systematic approach for constructing any combinational function. 2

3 omposing arbitrary gates > XOR y How many different gates do we really need? We can always do it with 3 different types of gates (ND, OR, INVERT), and sometimes with 2, but, can we use fewer? The TRIK is to OR the NDs of all input combinations that generate an output of. ou don t need the OR gate if only one input combination results in a. ou need Inverters to handle input combinations involving s, NDs, and ORs. 3

4 One will do! NNDs and NORs are UNIVERSL! UNIVERSL gate is one that can be used to implement *N* OMINTIONL FUNTION. There are many UNIVERSL gates, but not all gates are UNIVERSL. Q: What is a OMINTIONL FUNTION? : ny function that can be written as a truth table. = = = = = = h!, but what if we want more than 2-inputs? 4

5 Few More Gates omposing gates for high fan-in SOP logic synthesis MUX logic 5

6 Stupid Gate Tricks Suppose we have some 2-input XOR gates: t pd = ns nd we want an N-input XOR: output = iff number of s input is ODD ( PRIT ) t pd = N ns -- WORST SE. an we compute an N-input XOR faster? 6

7 I Think That I Shall Never See a Gate Lovely as a log N 2 log N N-input TREE has O( ) levels... 2 EVER N-Input ombinational function be implemented using only 2-input gates? ut, it s handy to have gates with more than 2-inputs when needed. Signal propagation takes O( log N ) gate delays. 7

8 systematic Design pproach Truth Table ) Write the functional spec as a truth table 2) Write down a oolean expression for every in the output = (! &&! && ) (! && && ) ( && &&!) ( && && ) 3) Wire up the ideal gates, replace them with equivalent realizable gates, call it a day, and go home! -it s systematic! -it works! -it s easy! -we get to go home! This approach will always give us logic expressions in a particular form: SUM-OF-PRODUTS 8

9 Straightforward Synthesis We can implement SUM-OF-PRODUTS with just 3 levels of logic. INVERTERS/ND/OR 9

10 Other Useful Gate ombinations NND-NND!(&&) =!! Pushing and ancelling ubbles DeMorgan s Laws NOR-NOR!( ) =! &&!

11 Other Useful MOS Gates V dd OI (ND-OR-INVERT) D OI (OR-ND-INVERT) D V dd OI and OI structures can be realized as a single MOS gate. However, their function is equivalent to 3 levels of logic. n OI s DeMorgan equivalent is usually easier to think about. D D D

12 nother Interesting 3-Input Gate ased on, select the or input to be copied to. If is then copy to, otherwise copy to Truth Table 2-input Multiplexer schematic Gate symbol 2

13 MUX ompositions and Shortcuts 4-input Mux (implemented as a tree) 4-bit wide 2-input Mux S I I I 2 I 3 S S S S S D S S S S S -3 S 3

14 MUX Function Synthesis onsider implementation of some arbitrary ombinational function, F(,,)... using a MULTIPLEXER as the only circuit element: Mux Logic: n example configurable logic element,,

15 MUX Logic tricks We can apply certain optimizations to MUX Function synthesis Desired Logic Function Largely by inspection or exhaustive search There s something interesting going on in those MUXes, - uild any N-input gate with an N- input MUX & one inverter 5

16 Next Time inary ircuits that: DD SUTRT SHIFT 6

Logic Design (Part 2) Combinational Logic Circuits (Chapter 3)

Logic Design (Part 2) Combinational Logic Circuits (Chapter 3) Digital Logic Circuits Logic Design (Part ) Combinational Logic Circuits (Chapter 3) ² We saw how we can build the simple logic gates using transistors ² Use these gates as building blocks to build more

More information

2/8/2017. SOP Form Gives Good Performance. ECE 120: Introduction to Computing. K-Maps Can Identify Single-Gate Functions

2/8/2017. SOP Form Gives Good Performance. ECE 120: Introduction to Computing. K-Maps Can Identify Single-Gate Functions University of Illinois at Urbana-Champaign Dept. of Electrical and Computer Engineering ECE 120: Introduction to Computing Two-Level Logic SOP Form Gives Good Performance s you know, one can use a K-map

More information

Digital Logic Design (3)

Digital Logic Design (3) Digital Logic Design (3) ENGG1015 1 st Semester, 2010 Dr. Kenneth Wong Dr. Hayden So Department of Electrical and Electronic Engineering Last lecture ll logic functions can be represented as (1) truth

More information

Boolean logic. Boolean Algebra. Introduction to Computer Yung-Yu Chuang NOT AND NOT

Boolean logic. Boolean Algebra. Introduction to Computer Yung-Yu Chuang NOT AND NOT oolean lgebra oolean logic ased on symbolic logic, designed by George oole oolean variables take values as or. oolean expressions created from: NOT, ND, OR Introduction to Computer ung-u Chuang with slides

More information

Lecture 7 Logic Simplification

Lecture 7 Logic Simplification Lecture 7 Logic Simplification Simplification Using oolean lgebra simplified oolean expression uses the fewest gates possible to implement a given expression. +(+)+(+) Simplification Using oolean lgebra

More information

ENEL Digital Circuits Midterm Examination

ENEL Digital Circuits Midterm Examination Name: Lecture Section: L0 N. artley :-:50 L02 S. Norman, 2:-2:50 ENEL 353 - igital ircuits Midterm Examination Wednesday, October 30, 203 Instructions: Time allowed is 90 minutes. In order to minimize

More information

Administrivia. CSE 370 Spring 2006 Introduction to Digital Design Lecture 9: Multilevel Logic

Administrivia. CSE 370 Spring 2006 Introduction to Digital Design Lecture 9: Multilevel Logic SE 370 Spring 2006 Introduction to igital esign Lecture 9: Multilevel Logic Last Lecture Introduction to Verilog Today Multilevel Logic Hazards dministrivia Hand in Homework #3 Homework #3 posted this

More information

Functional Block: Decoders

Functional Block: Decoders University of Wisconsin - Madison EE/omp Sci 352 Digital Systems Fundamentals harles R. Kime Section 2 Fall 2 hapter 3 ombinational Logic Design Part 2 Tom Kaminski & harles R. Kime harles Kime & Thomas

More information

Solutions for 3824 Midterm Exam 3/4/ Truth table. A B C Z

Solutions for 3824 Midterm Exam 3/4/ Truth table. A B C Z Solutions for 3824 Midterm Exam 3/4/04 1. Truth table. ----------- 0 0 0 1 0 0 1 1 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 1 1 1 1 0 2. When analyzing a circuit built with NN-gates, the easiest approach

More information

At this point in our study of digital circuits, we have two methods for representing combinational logic: schematics and truth tables.

At this point in our study of digital circuits, we have two methods for representing combinational logic: schematics and truth tables. HPTER FIVE oolean lgebra 5.1 Need for oolean Expressions t this point in our study of digital circuits, we have two methods for representing combinational logic: schematics and truth tables. 0 0 0 1 0

More information

Abstraction of State Elements. Sequential Logic Implementation. Forms of Sequential Logic. Finite State Machine Representations

Abstraction of State Elements. Sequential Logic Implementation. Forms of Sequential Logic. Finite State Machine Representations Sequential ogic Implementation! Models for representing sequential circuits " Finite-state machines (Moore and Mealy) " epresentation of memory (states) " hanges in state (transitions)! Design procedure

More information

Chapter 3 working with combinational logic

Chapter 3 working with combinational logic hapter 3 working with combinational logic ombinational Logic opyright 24, Gaetano orriello and Randy H. Katz Working with combinational logic Simplification two-level simplification exploiting don t cares

More information

Digital Fundamentals

Digital Fundamentals Digital Fundamentals Tenth Edition Floyd Chapter 3 Modified by Yuttapong Jiraraksopakun Floyd, Digital Fundamentals, th 28 Pearson Education ENE, KMUTT ed 29 The Inverter Summary The inverter performs

More information

1. Prove that if you have tri-state buffers and inverters, you can build any combinational logic circuit. [4]

1. Prove that if you have tri-state buffers and inverters, you can build any combinational logic circuit. [4] HW 3 Answer Key 1. Prove that if you have tri-state buffers and inverters, you can build any combinational logic circuit. [4] You can build a NAND gate from tri-state buffers and inverters and thus you

More information

Student Name: University of California at Berkeley College of Engineering Department of Electrical Engineering and Computer Science

Student Name: University of California at Berkeley College of Engineering Department of Electrical Engineering and Computer Science University of alifornia at erkeley ollege of Engineering epartment of Electrical Engineering and omputer Science EES 5 all 2 R. H. Katz IRST MITERM EXMINTION Tuesday, 3 October 2 INSTRUTIONS RE THEM NOW!

More information

Lecture (05) Boolean Algebra and Logic Gates

Lecture (05) Boolean Algebra and Logic Gates Lecture (05) Boolean Algebra and Logic Gates By: Dr. Ahmed ElShafee ١ Minterms and Maxterms consider two binary variables x and y combined with an AND operation. Since eachv ariable may appear in either

More information

Learning Objectives: Topic Karnaugh Maps. At the end of this topic you will be able to;

Learning Objectives: Topic Karnaugh Maps. At the end of this topic you will be able to; Topic.2.3 Karnaugh Maps Learning Objectives: t the end of this topic you will be able to; Draw a Karnaugh map for a logic system with up to four inputs and use it to minimise the number of gates required;

More information

Combinational Logic Worksheet

Combinational Logic Worksheet Combinational Logic Worksheet Concept Inventory: Truth tables sum-of-products equations implementation using NOT/AND/OR Demorgan s Law, implementation using NAND/NOR Simplification, truth tables w/ don

More information

Combinational Circuits

Combinational Circuits Combinational Circuits Q. What is a combinational circuit? A. Digital: signals are or. A. No feedback: no loops. analog circuits: signals vary continuously sequential circuits: loops allowed (stay tuned)

More information

6. Combinational Circuits. Building Blocks. Digital Circuits. Wires. Q. What is a digital system? A. Digital: signals are 0 or 1.

6. Combinational Circuits. Building Blocks. Digital Circuits. Wires. Q. What is a digital system? A. Digital: signals are 0 or 1. Digital Circuits 6 Combinational Circuits Q What is a digital system? A Digital: signals are or analog: signals vary continuously Q Why digital systems? A Accurate, reliable, fast, cheap Basic abstractions

More information

2B 52 AB CA 3E A1 +29 A B C. CS120 Fall 2018 Final Prep and super secret quiz 9

2B 52 AB CA 3E A1 +29 A B C. CS120 Fall 2018 Final Prep and super secret quiz 9 S2 Fall 28 Final Prep and super secret quiz 9 ) onvert 8-bit (2-digit) 2 s complement hex values: 4-29 inary: Hex: x29 2) onvert 8-bit 2 s complement hex to decimal: x3 inary: xe5 Decimal: 58 Note 3*6+

More information

Combinational Devices and Boolean Algebra

Combinational Devices and Boolean Algebra Combinational Devices and Boolean Algebra Silvina Hanono Wachman M.I.T. L02-1 6004.mit.edu Home: Announcements, course staff Course information: Lecture and recitation times and locations Course materials

More information

CS Spring Combinational Examples - 1

CS Spring Combinational Examples - 1 S 5 - Spring 2 - ombinational Examples - ombinational Logic esign ase Studies General esign Procedure for ombinational Logic General design procedure Examples alendar subsstem to 7-segment displa controller

More information

Written exam for IE1204/5 Digital Design Thursday 29/

Written exam for IE1204/5 Digital Design Thursday 29/ Written exam for IE1204/5 Digital Design Thursday 29/10 2015 9.00-13.00 General Information Examiner: Ingo Sander. Teacher: William Sandqvist phone 08-7904487 Exam text does not have to be returned when

More information

Lecture 6: Signed Numbers & Arithmetic Circuits. BCD (Binary Coded Decimal) Points Addressed in this Lecture

Lecture 6: Signed Numbers & Arithmetic Circuits. BCD (Binary Coded Decimal) Points Addressed in this Lecture Points ddressed in this Lecture Lecture 6: Signed Numbers rithmetic Circuits Professor Peter Cheung Department of EEE, Imperial College London (Floyd 2.5-2.7, 6.1-6.7) (Tocci 6.1-6.11, 9.1-9.2, 9.4) Representing

More information

Experiment 4 Boolean Functions Implementation

Experiment 4 Boolean Functions Implementation Experiment 4 Boolean Functions Implementation Introduction: Generally you will find that the basic logic functions AND, OR, NAND, NOR, and NOT are not sufficient to implement complex digital logic functions.

More information

QUESTION BANK FOR TEST

QUESTION BANK FOR TEST CSCI 2121 Computer Organization and Assembly Language PRACTICE QUESTION BANK FOR TEST 1 Note: This represents a sample set. Please study all the topics from the lecture notes. Question 1. Multiple Choice

More information

Boolean Unit (The obvious way)

Boolean Unit (The obvious way) oolean Unit (The obvious way) It is simple to build up a oolean unit using primitive gates and a mux to select the function. Since there is no interconnection between bits, this unit can be simply replicated

More information

ECE 550D Fundamentals of Computer Systems and Engineering. Fall 2017

ECE 550D Fundamentals of Computer Systems and Engineering. Fall 2017 ECE 550D Fundamentals of Computer Systems and Engineering Fall 2017 Combinational Logic Prof. John Board Duke University Slides are derived from work by Profs. Tyler Bletsch and Andrew Hilton (Duke) Last

More information

CHAPTER II SWITCH NETWORKS AND SWITCH DESIGN

CHAPTER II SWITCH NETWORKS AND SWITCH DESIGN HPTER II- HPTER II HPTER II ND R.M. Dansereau; v.. HPTER II-2 SI IDEL SWITH Simplest structure in a computing system is a switch IDEL SWITH INPUT OUTPUT Path exists between INPUT and OUTPUT if Switch is

More information

211: Computer Architecture Summer 2016

211: Computer Architecture Summer 2016 211: Computer Architecture Summer 2016 Liu Liu Topic: Storage Project3 Digital Logic - Storage: Recap - Direct - Mapping - Fully Associated - 2-way Associated - Cache Friendly Code Rutgers University Liu

More information

Gate-Level Minimization. section instructor: Ufuk Çelikcan

Gate-Level Minimization. section instructor: Ufuk Çelikcan Gate-Level Minimization section instructor: Ufuk Çelikcan Compleity of Digital Circuits Directly related to the compleity of the algebraic epression we use to build the circuit. Truth table may lead to

More information

Department of Electrical Engineering McGill University ECSE 221 Introduction to Computer Engineering Assignment 2 Combinational Logic

Department of Electrical Engineering McGill University ECSE 221 Introduction to Computer Engineering Assignment 2 Combinational Logic Department of Electrical Engineering McGill University ECSE 221 Introduction to Computer Engineering Assignment 2 Combinational Logic Question 1: Due October 19 th, 2009 A convenient shorthand for specifying

More information

Chapter 3. Boolean Algebra and Digital Logic

Chapter 3. Boolean Algebra and Digital Logic Chapter 3 Boolean Algebra and Digital Logic Chapter 3 Objectives Understand the relationship between Boolean logic and digital computer circuits. Learn how to design simple logic circuits. Understand how

More information

CS 31: Intro to Systems Digital Logic

CS 31: Intro to Systems Digital Logic CS 3: Intro to Systems Digital Logic Martin Gagné Swarthmore College January 3, 27 You re going to want scratch papr today borrow some if needed. Quick nnouncements Late Policy Reminder 3 late days total

More information

LAB 5 Implementing an ALU

LAB 5 Implementing an ALU Goals To Do Design a practical ALU LAB 5 Implementing an ALU Learn how to extract performance numbers (area and speed) Draw a block level diagram of the MIPS 32-bit ALU, based on the description in the

More information

What s a Tri-state Buffer?

What s a Tri-state Buffer? What s a Tri-state Buffer? 2003 by Charles C. Lin. All rights reserved. Introduction Before we talk about tri-state buffers, let s talk about an inverter. You can read about inverters in the notes about

More information

COMP combinational logic 1 Jan. 18, 2016

COMP combinational logic 1 Jan. 18, 2016 In lectures 1 and 2, we looked at representations of numbers. For the case of integers, we saw that we could perform addition of two numbers using a binary representation and using the same algorithm that

More information

! Replace maxterm OR gates with NOR gates! Place compensating inversion at inputs of AND gate

! Replace maxterm OR gates with NOR gates! Place compensating inversion at inputs of AND gate Two-level logic using NN gates (cont d) ELE 4 igital Electronics Week : ombinational Logic Implementation! OR gate with inverted inputs is a NN gate " de Morgan's: ' ' = ( )'! Two-level NN-NN network "

More information

Chapter 2. Boolean Expressions:

Chapter 2. Boolean Expressions: Chapter 2 Boolean Expressions: A Boolean expression or a function is an expression which consists of binary variables joined by the Boolean connectives AND and OR along with NOT operation. Any Boolean

More information

Digital Circuits ECS 371

Digital Circuits ECS 371 Digital Circuits ECS 37 Dr. Prapun Suksompong prapun@siit.tu.ac.th Lecture 7 Office Hours: KD 36-7 Monday 9:-:3, :3-3:3 Tuesday :3-:3 Announcement HW2 posted on the course web site Chapter 4: Write down

More information

Section 001. Read this before starting! You may use one sheet of scrap paper that you will turn in with your test.

Section 001. Read this before starting! You may use one sheet of scrap paper that you will turn in with your test. Points missed: Student's Name: Total score: /100 points East Tennessee State University Department of Computer and Information Sciences CSCI 2150 (Tarnoff) Computer Organization TEST 1 for Fall Semester,

More information

DIGITAL CIRCUIT LOGIC UNIT 7: MULTI-LEVEL GATE CIRCUITS NAND AND NOR GATES

DIGITAL CIRCUIT LOGIC UNIT 7: MULTI-LEVEL GATE CIRCUITS NAND AND NOR GATES DIGITAL CIRCUIT LOGIC UNIT 7: MULTI-LEVEL GATE CIRCUITS NAND AND NOR GATES 1 iclicker Question 13 Considering the K-Map, f can be simplified as (2 minutes): A) f = b c + a b c B) f = ab d + a b d AB CD

More information

Combinational Circuits Digital Logic (Materials taken primarily from:

Combinational Circuits Digital Logic (Materials taken primarily from: Combinational Circuits Digital Logic (Materials taken primarily from: http://www.facstaff.bucknell.edu/mastascu/elessonshtml/eeindex.html http://www.cs.princeton.edu/~cos126 ) Digital Systems What is a

More information

Date Performed: Marks Obtained: /10. Group Members (ID):. Experiment # 09 MULTIPLEXERS

Date Performed: Marks Obtained: /10. Group Members (ID):. Experiment # 09 MULTIPLEXERS Name: Instructor: Engr. Date Performed: Marks Obtained: /10 Group Members (ID):. Checked By: Date: Experiment # 09 MULTIPLEXERS OBJECTIVES: To experimentally verify the proper operation of a multiplexer.

More information

Working with Combinational Logic

Working with Combinational Logic KTZ_238576_M3.fm Page 93 Thursday, November 4, 24 2:38 PM H P T E R Working with ombinational Logic Introduction Now that we ve learned about two-level logic and had a short introduction to multilevel

More information

Topics of this Slideset. CS429: Computer Organization and Architecture. Digital Signals. Truth Tables. Logic Design

Topics of this Slideset. CS429: Computer Organization and Architecture. Digital Signals. Truth Tables. Logic Design Topics of this Slideset CS429: Computer Organization and rchitecture Dr. Bill Young Department of Computer Science University of Texas at ustin Last updated: July 5, 2018 at 11:55 To execute a program

More information

Parallel logic circuits

Parallel logic circuits Computer Mathematics Week 9 Parallel logic circuits College of Information cience and Engineering Ritsumeikan University last week the mathematics of logic circuits the foundation of all digital design

More information

Objectives: 1. Design procedure. 2. Fundamental circuits. 1. Design procedure

Objectives: 1. Design procedure. 2. Fundamental circuits. 1. Design procedure Objectives: 1. Design procedure. 2. undamental circuits. 1. Design procedure Design procedure has five steps: o Specification. o ormulation. o Optimization. o Technology mapping. o Verification. Specification:

More information

Jan Rabaey Homework # 7 Solutions EECS141

Jan Rabaey Homework # 7 Solutions EECS141 UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences Last modified on March 30, 2004 by Gang Zhou (zgang@eecs.berkeley.edu) Jan Rabaey Homework # 7

More information

Chapter 2 Part 4 Combinational Logic Circuits

Chapter 2 Part 4 Combinational Logic Circuits University of Wisconsin - Madison EE/omp Sci 352 Digital Systems undamentals Kewal K. Saluja and Yu Hen Hu Spring 2002 hapter 2 Part 4 ombinational Logic ircuits Originals by: harles R. Kime and Tom Kamisnski

More information

Bawar Abid Abdalla. Assistant Lecturer Software Engineering Department Koya University

Bawar Abid Abdalla. Assistant Lecturer Software Engineering Department Koya University Logic Design First Stage Lecture No.6 Boolean Algebra Bawar Abid Abdalla Assistant Lecturer Software Engineering Department Koya University Outlines Boolean Operations Laws of Boolean Algebra Rules of

More information

Chapter 3. Gate-Level Minimization. Outlines

Chapter 3. Gate-Level Minimization. Outlines Chapter 3 Gate-Level Minimization Introduction The Map Method Four-Variable Map Five-Variable Map Outlines Product of Sums Simplification Don t-care Conditions NAND and NOR Implementation Other Two-Level

More information

Outline. EECS Components and Design Techniques for Digital Systems. Lec 11 Putting it all together Where are we now?

Outline. EECS Components and Design Techniques for Digital Systems. Lec 11 Putting it all together Where are we now? Outline EECS 5 - Components and Design Techniques for Digital Systems Lec Putting it all together -5-4 David Culler Electrical Engineering and Computer Sciences University of California Berkeley Top-to-bottom

More information

(Refer Slide Time 6:48)

(Refer Slide Time 6:48) Digital Circuits and Systems Prof. S. Srinivasan Department of Electrical Engineering Indian Institute of Technology Madras Lecture - 8 Karnaugh Map Minimization using Maxterms We have been taking about

More information

Gate-Level Minimization. BME208 Logic Circuits Yalçın İŞLER

Gate-Level Minimization. BME208 Logic Circuits Yalçın İŞLER Gate-Level Minimization BME28 Logic Circuits Yalçın İŞLER islerya@yahoo.com http://me.islerya.com Complexity of Digital Circuits Directly related to the complexity of the algebraic expression we use to

More information

Identity. p ^ T p p _ F p. Idempotency. p _ p p p ^ p p. Associativity. (p _ q) _ r p _ (q _ r) (p ^ q) ^ r p ^ (q ^ r) Absorption

Identity. p ^ T p p _ F p. Idempotency. p _ p p p ^ p p. Associativity. (p _ q) _ r p _ (q _ r) (p ^ q) ^ r p ^ (q ^ r) Absorption dam lank pring 27 E 3 Identity Pre-Lecture Problem Do it! Do it now! What are you waiting for?! Use Logical Equivalences to show!! $! & & $! p ^ T p p _ F p Domination p _ T T p ^ F F Idempotency p _ p

More information

EECS 270 Midterm Exam

EECS 270 Midterm Exam EECS 270 Midterm Exam Fall 2009 Name: unique name: Sign the honor code: I have neither given nor received aid on this exam nor observed anyone else doing so. Scores: NOTES: Problem # Points 1 /11 2 /4

More information

Assignment (3-6) Boolean Algebra and Logic Simplification - General Questions

Assignment (3-6) Boolean Algebra and Logic Simplification - General Questions Assignment (3-6) Boolean Algebra and Logic Simplification - General Questions 1. Convert the following SOP expression to an equivalent POS expression. 2. Determine the values of A, B, C, and D that make

More information

6.1 Combinational Circuits. George Boole ( ) Claude Shannon ( )

6.1 Combinational Circuits. George Boole ( ) Claude Shannon ( ) 6. Combinational Circuits George Boole (85 864) Claude Shannon (96 2) Digital signals Binary (or logical ) values: or, on or off, high or low voltage Wires. Propagate logical values from place to place.

More information

Lecture 10: Combinational Circuits

Lecture 10: Combinational Circuits Computer Architecture Lecture : Combinational Circuits Previous two lectures.! TOY machine. Net two lectures.! Digital circuits. George Boole (85 864) Claude Shannon (96 2) Culminating lecture.! Putting

More information

1. Mark the correct statement(s)

1. Mark the correct statement(s) 1. Mark the correct statement(s) 1.1 A theorem in Boolean algebra: a) Can easily be proved by e.g. logic induction b) Is a logical statement that is assumed to be true, c) Can be contradicted by another

More information

Austin Herring Recitation 002 ECE 200 Project December 4, 2013

Austin Herring Recitation 002 ECE 200 Project December 4, 2013 1. Fastest Circuit a. How Design Was Obtained The first step of creating the design was to derive the expressions for S and C out from the given truth tables. This was done using Karnaugh maps. The Karnaugh

More information

MODULE 5 - COMBINATIONAL LOGIC

MODULE 5 - COMBINATIONAL LOGIC Introduction to Digital Electronics Module 5: Combinational Logic 1 MODULE 5 - COMBINATIONAL LOGIC OVERVIEW: For any given combination of input binary bits or variables, the logic will have a specific

More information

Logic and Computer Design Fundamentals. Chapter 2 Combinational Logic Circuits. Part 3 Additional Gates and Circuits

Logic and Computer Design Fundamentals. Chapter 2 Combinational Logic Circuits. Part 3 Additional Gates and Circuits Logic and Computer Design Fundamentals Chapter 2 Combinational Logic Circuits Part 3 Additional Gates and Circuits Charles Kime & Thomas Kaminski 28 Pearson Education, Inc. (Hyperlinks are active in View

More information

Lecture 7. Summary of two-level combinational-logic. Ways of specifying circuits. Solving combinational design problems. Verilog versus VHDL

Lecture 7. Summary of two-level combinational-logic. Ways of specifying circuits. Solving combinational design problems. Verilog versus VHDL Lecture 7 Summary of two-level combinational-logic Logistics Homework due today Homework out today due next Wednesday First midterm a week Friday: Friday Jan 0 Will cover up to the of Multiplexers/DeMultiplexers

More information

Computer Organization and Levels of Abstraction

Computer Organization and Levels of Abstraction Computer Organization and Levels of Abstraction Announcements Today: PS 7 Lab 8: Sound Lab tonight bring machines and headphones! PA 7 Tomorrow: Lab 9 Friday: PS8 Today (Short) Floating point review Boolean

More information

Topic Notes: Building Memory

Topic Notes: Building Memory Computer Science 220 ssembly Language & Comp. rchitecture Siena College Fall 2011 Topic Notes: Building Memory We ll next see how we can use flip-flop devices to construct memory. Buffers We ve seen and

More information

Building a Virtual Computer

Building a Virtual Computer uilding a Virtual Computer From Gates to Operating System Student Researcher: Elisa Elshamy Faculty Mentor: Dr. Victoria Gitman bstract modern computer can carry a plethora of multifaceted computations.

More information

ELCT201: DIGITAL LOGIC DESIGN

ELCT201: DIGITAL LOGIC DESIGN ELCT201: DIGITAL LOGIC DESIGN Dr. Eng. Haitham Omran, haitham.omran@guc.edu.eg Dr. Eng. Wassim Alexan, wassim.joseph@guc.edu.eg Lecture 3 Following the slides of Dr. Ahmed H. Madian محرم 1439 ه Winter

More information

Fundamentals of Computer Systems

Fundamentals of Computer Systems Fundamentals of Computer Systems Combinational Logic Stephen. Edwards Columbia University Summer 7 Combinational Circuits Combinational circuits are stateless. Their output is a function only of the current

More information

CS8803: Advanced Digital Design for Embedded Hardware

CS8803: Advanced Digital Design for Embedded Hardware CS883: Advanced Digital Design for Embedded Hardware Lecture 2: Boolean Algebra, Gate Network, and Combinational Blocks Instructor: Sung Kyu Lim (limsk@ece.gatech.edu) Website: http://users.ece.gatech.edu/limsk/course/cs883

More information

GC03 Boolean Algebra

GC03 Boolean Algebra Why study? GC3 Boolean Algebra Computers transfer and process binary representations of data. Binary operations are easily represented and manipulated in Boolean algebra! Digital electronics is binary/boolean

More information

9/10/2016. ECE 120: Introduction to Computing. The Domain of a Boolean Function is a Hypercube. List All Implicants for One Variable A

9/10/2016. ECE 120: Introduction to Computing. The Domain of a Boolean Function is a Hypercube. List All Implicants for One Variable A University of Illinois at Urbana-Champaign Dept. of Electrical and Computer Engineering ECE 120: Introduction to Computing To Simplify, Write Function as a Sum of Prime Implicants One way to simplify a

More information

VLSI for Multi-Technology Systems (Spring 2003)

VLSI for Multi-Technology Systems (Spring 2003) VLSI for Multi-Technology Systems (Spring 2003) Digital Project Due in Lecture Tuesday May 6th Fei Lu Ping Chen Electrical Engineering University of Cincinnati Abstract In this project, we realized the

More information

ELCT201: DIGITAL LOGIC DESIGN

ELCT201: DIGITAL LOGIC DESIGN ELCT201: DIGITAL LOGIC DESIGN Dr. Eng. Haitham Omran, haitham.omran@guc.edu.eg Dr. Eng. Wassim Alexan, wassim.joseph@guc.edu.eg Lecture 3 Following the slides of Dr. Ahmed H. Madian ذو الحجة 1438 ه Winter

More information

ECE3663 Design Project: Design Review #1

ECE3663 Design Project: Design Review #1 ECE3663 Design Project: Design Review #1 General Overview: For the first stage of the project, we designed four different components of the arithmetic logic unit. First, schematics for each component were

More information

1. Fill in the entries in the truth table below to specify the logic function described by the expression, AB AC A B C Z

1. Fill in the entries in the truth table below to specify the logic function described by the expression, AB AC A B C Z CS W3827 05S Solutions for Midterm Exam 3/3/05. Fill in the entries in the truth table below to specify the logic function described by the expression, AB AC A B C Z 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2.

More information

Summary. Boolean Addition

Summary. Boolean Addition Summary Boolean Addition In Boolean algebra, a variable is a symbol used to represent an action, a condition, or data. A single variable can only have a value of or 0. The complement represents the inverse

More information

Chapter 2. Boolean Algebra and Logic Gates

Chapter 2. Boolean Algebra and Logic Gates Chapter 2. Boolean Algebra and Logic Gates Tong In Oh 1 Basic Definitions 2 3 2.3 Axiomatic Definition of Boolean Algebra Boolean algebra: Algebraic structure defined by a set of elements, B, together

More information

Combinational Logic & Circuits

Combinational Logic & Circuits Week-I Combinational Logic & Circuits Spring' 232 - Logic Design Page Overview Binary logic operations and gates Switching algebra Algebraic Minimization Standard forms Karnaugh Map Minimization Other

More information

Review. EECS Components and Design Techniques for Digital Systems. Lec 05 Boolean Logic 9/4-04. Seq. Circuit Behavior. Outline.

Review. EECS Components and Design Techniques for Digital Systems. Lec 05 Boolean Logic 9/4-04. Seq. Circuit Behavior. Outline. Review EECS 150 - Components and Design Techniques for Digital Systems Lec 05 Boolean Logic 94-04 David Culler Electrical Engineering and Computer Sciences University of California, Berkeley Design flow

More information

IT 201 Digital System Design Module II Notes

IT 201 Digital System Design Module II Notes IT 201 Digital System Design Module II Notes BOOLEAN OPERATIONS AND EXPRESSIONS Variable, complement, and literal are terms used in Boolean algebra. A variable is a symbol used to represent a logical quantity.

More information

ece5745-pla-notes.txt

ece5745-pla-notes.txt ece5745-pla-notes.txt ========================================================================== Follow up on PAL/PROM/PLA Activity ==========================================================================

More information

Optimized Implementation of Logic Functions

Optimized Implementation of Logic Functions June 25, 22 9:7 vra235_ch4 Sheet number Page number 49 black chapter 4 Optimized Implementation of Logic Functions 4. Nc3xe4, Nb8 d7 49 June 25, 22 9:7 vra235_ch4 Sheet number 2 Page number 5 black 5 CHAPTER

More information

CPLD Experiment 4. XOR and XNOR Gates with Applications

CPLD Experiment 4. XOR and XNOR Gates with Applications CPLD Experiment 4 XOR and XNOR Gates with Applications Based on Xilinx ISE Design Suit 10.1 Department of Electrical & Computer Engineering Florida International University Objectives Materials Examining

More information

Digital Logic Design Exercises. Assignment 1

Digital Logic Design Exercises. Assignment 1 Assignment 1 For Exercises 1-5, match the following numbers with their definition A Number Natural number C Integer number D Negative number E Rational number 1 A unit of an abstract mathematical system

More information

University of Toronto Faculty of Applied Science and Engineering Edward S. Rogers Sr. Department of Electrical and Computer Engineering

University of Toronto Faculty of Applied Science and Engineering Edward S. Rogers Sr. Department of Electrical and Computer Engineering University of Toronto Faculty of Applied Science and Engineering Edward S. Rogers Sr. Department of Electrical and Computer Engineering Final Examination ECE 241F - Digital Systems Examiners: S. Brown,

More information

Chap-2 Boolean Algebra

Chap-2 Boolean Algebra Chap-2 Boolean Algebra Contents: My name Outline: My position, contact Basic information theorem and postulate of Boolean Algebra. or project description Boolean Algebra. Canonical and Standard form. Digital

More information

structure syntax different levels of abstraction

structure syntax different levels of abstraction This and the next lectures are about Verilog HDL, which, together with another language VHDL, are the most popular hardware languages used in industry. Verilog is only a tool; this course is about digital

More information

Here is a list of lecture objectives. They are provided for you to reflect on what you are supposed to learn, rather than an introduction to this

Here is a list of lecture objectives. They are provided for you to reflect on what you are supposed to learn, rather than an introduction to this This and the next lectures are about Verilog HDL, which, together with another language VHDL, are the most popular hardware languages used in industry. Verilog is only a tool; this course is about digital

More information

Chapter 6. CMOS Functional Cells

Chapter 6. CMOS Functional Cells Chapter 6 CMOS Functional Cells In the previous chapter we discussed methods of designing layout of logic gates and building blocks like transmission gates, multiplexers and tri-state inverters. In this

More information

Combinational Logic II

Combinational Logic II Combinational Logic II Ranga Rodrigo July 26, 2009 1 Binary Adder-Subtractor Digital computers perform variety of information processing tasks. Among the functions encountered are the various arithmetic

More information

ECE COMBINATIONAL BUILDING BLOCKS - INVEST 16 READ ONLY MEMORIES

ECE COMBINATIONAL BUILDING BLOCKS - INVEST 16 READ ONLY MEMORIES ECE 24 - CMBINATINAL BUILDING BLCKS - INVEST 6 READ NL MEMRIES FALL 23 A.P. FELZER To do "well" on this investigation you must not only get the right answers but must also do neat, complete and concise

More information

Boolean Analysis of Logic Circuits

Boolean Analysis of Logic Circuits Course: B.Sc. Applied Physical Science (Computer Science) Year & Sem.: IInd Year, Sem - IIIrd Subject: Computer Science Paper No.: IX Paper Title: Computer System Architecture Lecture No.: 7 Lecture Title:

More information

6.1 Combinational Circuits. George Boole ( ) Claude Shannon ( )

6.1 Combinational Circuits. George Boole ( ) Claude Shannon ( ) 6. Combinational Circuits George Boole (85 864) Claude Shannon (96 2) Signals and Wires Digital signals Binary (or logical ) values: or, on or off, high or low voltage Wires. Propagate digital signals

More information

University of Technology

University of Technology University of Technology Lecturer: Dr. Sinan Majid Course Title: microprocessors 4 th year Lecture 5 & 6 Minimization with Karnaugh Maps Karnaugh maps lternate way of representing oolean function ll rows

More information

Menu. Algebraic Simplification - Boolean Algebra EEL3701 EEL3701. MSOP, MPOS, Simplification

Menu. Algebraic Simplification - Boolean Algebra EEL3701 EEL3701. MSOP, MPOS, Simplification Menu Minterms & Maxterms SOP & POS MSOP & MPOS Simplification using the theorems/laws/axioms Look into my... 1 Definitions (Review) Algebraic Simplification - Boolean Algebra Minterms (written as m i ):

More information

Experiment 3: Logic Simplification

Experiment 3: Logic Simplification Module: Logic Design Name:... University no:.. Group no:. Lab Partner Name: Mr. Mohamed El-Saied Experiment : Logic Simplification Objective: How to implement and verify the operation of the logical functions

More information

Supplement to. Logic and Computer Design Fundamentals 4th Edition 1

Supplement to. Logic and Computer Design Fundamentals 4th Edition 1 Supplement to Logic and Computer esign Fundamentals 4th Edition MORE OPTIMIZTION Selected topics not covered in the fourth edition of Logic and Computer esign Fundamentals are provided here for optional

More information