Combinational Verilog Intro. EECS 270 Labs

Transcription

1 Combinational Verilog Intro EECS 270 Labs

2 From Schematics to Verilog e-gate-arrays-fpga _US/pdfs/literature/wp/wp pdf

3 Schematics to Verilog cont. a1 module add_half (a, b, s, cout); input a, b; output s, cout; wire s, cout; assign s = a ^ b;assign cout = a & b; endmodule // end of half adder module module add_full (a, b, cin, s, cout); input a, b, cin; output s, cout; wire s, cout; assign s = a ^ b ^ cin; assign cout = (a & b) (a & cin) (b & cin); endmodule // end of full adder module module add_2bit (a, b, s, cout); input [1:0] a, b; output [1:0] s; output cout; wire [1:0] s; wire cout; // Both a and b are 2 bit inputs // s[1] = MSB of s, s[0] = LSB of s wire c0; add_half a1(a[0], b[0], s[0], c0); // intermediate carry between adders add_full a2(a[1], b[1], c0, s[1], cout); endmodule a2

4 Verilog Modular Structure Module Definition: module <module name> (<input list>, <output list>); input <name>, output endmodule Input list and output list (in that order) are comma-separated list of variable names (identifiers) Can define multi-bit signals with type[n:0] name representing a n+1 bit input/output Module Instantiations: <module name> <instance name> (<parameter list>);

5 Verilog Literals <size><base format><number> Size: In decimal, the number of bits of <number> Base Format Options: b binary d decimal o octal h hexadecimal Examples: 549 'h8ff 'o765 4'b11 // 4-bit binary number 'd3 // 5-bit decimal number

6 Macros `define <MACRO_NAME> <literal> a = b & `<MACRO_NAME>; Don t forget the `, same key as tilda on the keyboard. Example: `define FORWARD 7 b ; hex[6:0] = `FORWARD;

7 Behavioral Verilog Operators & Bitwise AND Bitwise OR ~ Bitwise Negation (eg. ~A, ~(A & B), (~A B) ^ Bitwise XOR << n Left shift by n >> n Right shift by n {} Concatenation {a,b,c} puts a, b, and c after one another into a single value {n{m}} makes a single value that is n copies of m, one after the other cond? iftrue : iffalse Ternary (Conditional Operator) assign mux_out = (sel == 1)? in1 : in0; If sel equals 1, mux_out = in1, else mux_out = in0;

8 Structural Verilog Specifically indicates which gates to instantiate AND, OR, XOR, NOT, NAND, NOR <gate type> <instance name> (<output name> <input list>); If output name is a multi-bit signal, multiple instances of the gate will be made Input bit widths must match output bit widths module add_half (a, b, s, cout); input a, b;output s, cout;wire s, cout; xor x1 (s, a, b); and a1 (cout, a, b); endmodule // end of half adder module module add_full (a, b, cin, s, cout); input a, b, cin; output s, cout; wire s, cout; wire ab, ac, bc; // Intermediate AND gate outputs xor x2 (s, a, b, cin); and a2 (ab, a, b); and a3 (ac, a, cin); and a4 (bc, b, cin); or o1 (cout, ab, bc, ac); endmodule // end of full adder module

9 Behavioral vs Structural Verilog A LUT ( Look Up Table) as a truth table Behavioral Verilog takes advantage of LUTs that condense boolean logic to single logic blocks Structural Verilog instantiates individual gates in ea. Logic block University of Florida ECE Department Reconfigurable Architectures

10 Lab 3 Intro EECS 270 Labs

11 Robbie Goal: Drive to a beacon by controlling two wheels Robbie can go straight, right, or left Inputs to Robbie: Sensors on Front, Right and Left Sensor outputs 1 if detects beacon Outputs from Robbie: Right and Left Wheel Motion Each wheel can either go forward (F), or stop (S). Schematic & Verilog Versions, use separate Quartus Projects!

12 Robbie s Rules (Logic) Go straight if Forward beacon sensor or Right and Left sensors are 1 Go right if: Go left if: Stop if: Forward and Right sensors but not Left sensor Right sensor only Forward and Left sensors but not Right sensor Left sensor only Forward, Right, and Left None (All sensors drive low)

13 Controlling Robbie Action Left Wheel Right Wheel Straight Forward Forward Right Forward Stop Left Stop Forward Stop Stop Stop

14 Schematic and Verilog Implementations Sensors: Wheels SW[2] : Left SW[1] : Forward SW[0] : Right LEDR[1] (ON/OFF): Left Wheel Forward/Stopped LEDR[0] (ON/OFF): Right Wheel Forward/Stopped Sensors: Wheels SW[2] : Left SW[1] : Forward SW[0] : Right HEX1 -> F/S: Left Wheel Forward/Stopped HEX0 -> F/S: Right Wheel Forward/Stopped (HEX are active low!)

15 Robbie Verilog Top-level module name must be same as your project name Inputs: Left sensor, forward sensor, right sensor Outputs: [6:0] left wheel drive [6:0] right wheel drive HEX submodules will take a single control bit input (Forward or Stopped) and write to the hex displays Every time you instantiate a new submodule it must have a new instance name E.g. outputsf osf1(<input_parameter_list>,<output_params_list>); outputsf osf2(<input_parameter_list>,<output_params_list>);

16 Quick aside on bit sets/bit strings/busses [n-1:0] a_name = n hfa800f LSB: a_name[0] MSB: a_name[n-1] = 1 output [6:0] lwd, rwd assign lwd = 7 h11 lwd[0] = 1 lwd[4] = 1 lwd[6:5], lwd[3:1] are 0 [0] [1] [2] n n [n-1]

17 Robbie Verilog Top level module name = verilog file name = quartus project name Submodules can be in the same verilog file. FPGA pin assignments ( QSF file ) are made to the top-level-module s inputs and output names E.g. set_location_assignment PIN_H21 -to LEDG[4] Replace LEDG[4] with the output name you used in top level module

18 Renee (no schematic, only verilog) Goal: Drive to the beacon, responding to obstacles Inputs: Beacon Sensors [2:0] 2 sensors, front-left, front-right 3-bit unsigned number: signal strength, higher = closer Bumper Sensors (Active Low) 4 sensors, front, back, right, left Outputs: Wheels Forward (F), Backwards (r), Stop (S) Left Bumper Left Beacon Sensor Front Bumper Renee Back Bumper Right Beacon Sensor Right Bumper

19 Renee s Rules (Logic) First priority is dealing w/obstacles, then head to beacon (Robbie beacon logic) Go forward if Back bumper sensor only is active Right and Left beacon sensors are both not 0 and are both equal strength Go reverse if Go right if: Go left if: Front bumper sensor only is active Left and Back bumpers only are active Right and Back bumpers only are active Go left-back if Right and Front bumpers only are active Right bumper only is active Go right-back if Stop if: Left and Front bumpers only are active Left bumper only is active Right and Left beacon sensors are both 0 Right and Left bumpers are active Top and Bottom bumpers are active

20 Controlling Renee Action Left Wheel Right Wheel Forward Forward Forward Left Stop Forward Right Forward Stop Stop Stop Stop Left Back Stop Reverse Right Back Reverse Stop Reverse Stop Reverse

21 Verilog Implementation Beacon Sensors: SW[6:4] : Left SW[2:0] : Right Note: SW[3] unused Bumper Sensors: Key3 : Left Key0 : Right Key2: Front Key1 : Back Note: Buttons are Active low, collision occurs if key is pressed (like an actual bumper) Wheels HEX1 -> F/S/r: Left Wheel Forward/Stopped/reverse HEX0 -> F/S/r: Right Wheel Forward/Stopped/reverse Note: r is displayed as segments 4 & 6 on the hex.

22 Renee Verilog Notes Top level module name = verilog file name = quartus project name renee renee.v renee.qpf module renee(ls,rs,fb,rb,lb,bb,lwd,rwd); input [2:0] ls,rs; //Beacon sensors input fb, rb, lb, bb; //Bumper sensors output [6:0]lwd,rwd; //wheel outputs

23 Renee Verilog Hints Don t try to write a truth table for Renee, think about the logic description in english and how ifs may translate to ands, ors, etc. in verilog Make intermediate results, be ~modular~ Ideas: Modules to represent sensor/ bumper driven modes? Module to compare the sensor values? Module to determine where beacon is? Use a submodule to manage hex, like Robbie s but with edits for reverse No conditionals allowed in this lab (if, else) Declare hex outputs as sets in Verilog (i.e. output [6:0] lwd) so they can be displayed as a bus on the simulation waveform.

24 In-Lab and Post-Lab Deliverables In-Lab Demo Part 1: Robbie Verilog running on DE2 board In-Lab Demo Part 2: Renee running on DE2 board (Signed separate from part 1), due the week after demo part 1 Post Lab: Robbie functional sim waveform and testbench Post Lab: Renee functional sim waveform and testbench for given test cases For both sims display wheels as a bus ( see bottom for what this should look like ) Post Lab: Verilog code for Robbie and Renee Post Lab: Questions in Post Lab Post Lab is due the week after Demo Part 2. Example of what a simulation displaying the output as a bus looks like. You will achieve this by labeling the output as a bus in the testbench (using [6:0] instead of listing each segment of the display)