University of Toronto Faculty of Applied Science and Engineering Edward S. Rogers Sr. Department of Electrical and Computer Engineering

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1 University of Toronto Faculty of Applied Science and Engineering Edward S. Rogers Sr. Department of Electrical and Computer Engineering Final Examination ECE 241F - Digital Systems Examiners: S. Brown, J. Rose, and B. Wang December 10, 2008 Duration: 2.5 Hours ANSWER ALL QUESTIONS. USE ONLY THESE SHEETS, USING THE BACKS IF NECESSARY. Exam Type D, these specific aids allowed: i. Original Versions (no photocopies) of the course text, Fundamentals of Digital Logic with Verilog Design (1 st or 2 nd edition), by Brown & Vranesic, ISBN ii. One 8.5 x 11 two-sided aid sheet. The amount of marks available for each question is given in square brackets []. LAST NAME: FIRST NAME: STUDENT NUMBER: Question Total Maximum Mark Mark Obtained Page 1 of 24

2 [12] Q1. Miscellaneous questions on logic and binary numbers. [3] a) For the logic function, determine the minimal product-of-sum (POS) expression. You are required to use the K-map provided below: ab cd Solution: ab cd [1 mark] for correct K-map entries [2 marks] for correct POS expression Page 2 of 24

3 Q1, cont d [3] b) Determine if the Boolean equation given below is correct. If it is correct, use Boolean Algebra to prove it and identify (by name or the number from Chapter 2 of the textbook) the Boolean axioms and theorems used to do so. Otherwise, simply state that it is not correct. Solution: L.H. = = = = 12b 15b 8a 6b 16a L.H. = R.H. therefore, the equation is correct. [2] c) Fill in the blanks in the table below: 8-bit two s complement number Signed decimal number bit two s complement number Signed decimal number [2 marks] [1] d) Specify the range of decimal numbers that can be represented in the two s complement number representation using a word length of 8 bits. to -128 to +127 [0.5 marks each] Page 3 of 24

4 Q1, cont d [3] e) Consider the logic circuit shown below. Design a functionally equivalent circuit that minimizes the total cost, where cost = number of gates + number of inputs. You are allowed to use AND, OR and NOT gates (with any number of inputs) in your circuit. Show how you arrive at your solution. Solution: f = = = [2 marks] [1 mark] Page 4 of 24

5 [15] Q2. [2] a) Using just one 2-to-1 multiplexer and as few other AND, OR or NOT logic gates as possible, implement the function. (Hint: use Shannon s decomposition theorem) Solution: [2] marks [6] b) Consider the two logic functions, f and g shown below. Implement both functions using ONLY 2-to-1 multiplexers, and use as few as possible. (Hint: use Shannon s theorem and reuse multiplexers whenever possible.) Solution: [1] [1] [4] marks for the correct and 4 mux circuit -2 marks for using other gate(s) -1 mark for each extra mux used Page 5 of 24

6 Q2, cont d [7] c) Consider the logic function, f, implemented using three 3-LUTs as shown below: Determine the logic function in the minimal sum-of-product (SOP) form, in the following three steps: [2] (i) Determine f 1 : Solution: by inspection f1 [2] [2] (ii) Determine f 2 : f2 [2] [3] (iii) Determine f in minimal SOP form: f3 = [2] [1] marks for the minimal SOP form Page 6 of 24

7 [10] Q3. Consider the following state diagram for a one-input (with input g), one-output (with output Z) state machine: You are to determine a portion of the gate-level design of this fully-encoded state machine using the following state encoding: State Code S 2 S 1 S 0 A 000 B 001 C 010 D 011 E 100 F 101 You are to create your design in the following steps, beginning on the next page: Page 7 of 24

8 Q3, continued [3] (a) Determine the State-Assigned Table below: Current State Next State Output Solution Current State Next State Output g=0 g=1 S 2 S 1 S 0 S 2 S 1 S 0 A 000 A 000 C B 001 B 001 F C 010 B 001 E D 011 A 000 A E 100 D 011 F F 101 B 001 B marks, 0.5 for each row of the table; 0.25 off for each mistake. Page 8 of 24

9 [2] (b) Give the circuit diagram for the state flip-flops only for this state machine. You should label the current state with S2, S 1, and S 0. You should also clearly label the inputs of the flip-flops. You will use these labels in answers to part (c) and (d) below. Also, assuming that there is a state machine reset signal called Reset, your circuit should include the appropriate clear and preset connections to the flip-flops. Solution: worth 2 marks 0.5 for D s 0.5 for S s and 1 for correct reset: [3] (c) Determine the minimal sum-of-products expression for only the next-state logic for state flip-flop S 2. (Notice that you don t have to do the logic for all three flip-flops, just the one for S 2 ). Use the labels you created in part (b). The K-map below is provided for your convenience: Page 9 of 24

10 Solution: D2 = S2 S1 S0g + S1S0 g +S2S0 g Worth 3 marks for each of D2; -0.5 for each mistake to to max of 2; [2] (d) Determine the minimal sum-of-products expression for the output logic of the machine, again making use of the labels you used in part (b) above. Solution: Z = S1 + S2 S0 2 Marks Page 10 of 24

11 [6] Q4. The CMOS circuit given below is supposed to implement a logic function, f. However, there are some mistakes in the circuit. Assuming that the pull-up network (PUN) portion is correct, you are to make the necessary corrections to the pull-down network (PDN) directly on the circuit diagram below. To make the corrections you can both draw an additional wire if needed, or, draw an X on a wire if it should be removed. Also, determine the intended logic function, f (no simplification is required). Correct Logic Function: Solution 3 marks or Page 11 of 24 3 marks

12 [8] Q5. Consider the following circuit: The adder in the above circuit is a ripple-carry adder which consists of eight Full Adders, each designed as below: Furthermore, the timing parameters of the logic gates and flip-flops in the circuit are given below: Gate Maximum Propagation Delay Minimum Propagation Delay Exclusive-OR 2ns 0.5ns AND 2ns 0.5ns OR 1ns 0.5ns Flip-Flop Clock-to-Q 2ns 0.5ns Flip-Flop Set-up Time Flip-Flop Hold Time 2ns 1.5ns Page 12 of 24

13 Q5, cont d [3] (a) What is the minimum clock period for which this circuit will function correctly? (Do not consider hold time violations for this part of the analysis). Show how you arrive at your answer. Solution: 8 x ( 2 + 1) = 24ns delay through 8 carry logic computations 1 Clock to Q = 2ns Setup Time = 2ns Total: 28ns Worth 3 marks. [5] (b) Determine if the hold time for all of the flip-flops in Register S are met in this circuit, and indicate which are not. For those flip-flops for which the hold time is violated, give a change to the circuit, using just the type of gates in the table above, that corrects the hold-time violation. Your correction should increase the minimum clock period (which you computed in part (a) above) as little as possible. Solution: there is a hold time violation on all flip flops in register S because the minimum propagation delay after a positive edge is min Clock-to-Q (0.5ns) plus min exor (0.5ns) = 1.0ns < 1.5 ns hold. Worth 3 marks. Fix: add an OR gate with one input wired to ground in series with every output of the adder. (OR gate is the fastest gate, so it minimizes the increase in cycle time) Worth 2 marks. Page 13 of 24

14 [11] Q6. Verilog/Lab questions. [6] a) Consider the Verilog code shown below: module Dude (input Clock, Resetn, sync, output reg blah); reg [2:0] slow; wire z; Clock) slow <= slow + 1'b1; assign z = slow[2] slow[1] slow[0]; Clock) if (Resetn == 1'b0) blah <= 1'b0; else blah <= (!blah & sync) (blah & z); endmodule (i) [3] Draw a circuit schematic that corresponds to this code. You may assume that an n-bit counter is available for the slow signal, but otherwise only basic gates, multiplexers, and flip-flops can be used in your circuit. ANSWER: 3 marks: 1 for counter with gate, 1 for mux, 1 for Flip-flop Page 14 of 24

15 (ii) [3] Explain briefly, in a few sentences, the function of the circuit that is described by this Verilog code. In other words, what does the circuit do? ANSWER: Marking for above: 3 marks, 1 for synchronous clear, 1 for how FF set, for how FF cleared Page 15 of 24

Q6, continued [5] b) Consider the Verilog code shown below: module S_up (input CLOCK_50,input [0:0] KEY, input [1:0] SW, output [7:0] LEDG); reg [23:0] Y; reg [7:0] Thing; always @(posedge CLOCK_50)

16 Q6, continued [5] b) Consider the Verilog code shown below: module S_up (input CLOCK_50,input [0:0] KEY, input [1:0] SW, output [7:0] LEDG); reg [23:0] Y; reg [7:0] Thing; CLOCK_50) Y <= Y + 1'b1; assign z = (Y == 0)? 1 : 0; CLOCK_50) if (KEY[0] == 1'b0) Thing <= 8'b ; else if (z) if (SW[0]) begin Thing[7] <= Thing[0]; Thing[6:0] <= Thing[7:1]; end else if (SW[1]) begin Thing[0] <= Thing[7]; Thing[7:1] <= Thing[6:0]; end assign LEDG = Thing; endmodule [5] Explain briefly, in a few sentences, the function of the circuit that is described by this Verilog code. In other words, what does the circuit do? Explain what you could observe if you implemented this circuit on a DE2 board, and tested its operation (additional space for your answer is given on the top of the next page). ANSWER: Page 16 of 24

17 5 marks: 1 for counter 1 for shift register 2 for rate of the shift (three times per second) 1 for green LEDs Page 17 of 24

ANSWER: [2] b) In Lab 7 you connected a VGA display to the DE2 board.

18 [4] Q7. Lab Related Questions. [2] a) In Lab 6 you connected a PS/2 keyboard and speakers to the DE2 board. In the circuit you created, what was the purpose of the signal called PS2_tx_start? In your answer explain how your circuit used this signal. ANSWER: [2] b) In Lab 7 you connected a VGA display to the DE2 board. The circuit, provided for you, that produces the timing information for the VGA display was called the VGA Adaptor. In this VGA Adaptor, there is an input signal called plot (this input was also called WriteEn in the lab writeup). Explain how the plot signal is used, and what happens in the VGA Adaptor as a result of asserting this signal. ANSWER: Page 18 of 24

19 [10] Q8. Finite state machine word problem. For this question you need to design a circuit that communicates with a device. This device has two inputs called Reset and Init, as well as a Clock input, and four outputs called Data8, Y, N, and E. The Data8 output is 8-bits in width. The Init input is used to initialize the device, which must be done after the circuit is reset. The initialization protocol is defined by the timing diagram below (note that the reset operation is not shown in this diagram). Note that you cannot determine how many clock cycles are needed after Init is set to 1 until Y becomes 1 to indicate completion of the initialization operation. The purpose of the N output is to indicate that there is a problem with the device. If N becomes set to 1, then your circuit must reinitialize the device (i.e. go through the initialization process again). After successful initialization the device will begin sending data at some point in time. The protocol for sending data is shown below: Page 19 of 24

Q8, cont d [7] a) You are to draw the state diagram for a finite state machine that controls the device. Provide a reset state for the FSM, and make sure to initialize the device as needed.

device, your FSM should set a signal Done to 1 for one clock cycle. This process should continue as long as no error (indicated by N becoming 1) occurs.

20 Q8, cont d [7] a) You are to draw the state diagram for a finite state machine that controls the device. Provide a reset state for the FSM, and make sure to initialize the device as needed. Additionally, your FSM needs to do the following: when the device is sending data, your FSM needs to keep track of how many bytes of data it has sent after each third byte of data is sent by the device, your FSM should set a signal Done to 1 for one clock cycle. This process should continue as long as no error (indicated by N becoming 1) occurs. Inside each state bubble, show the FSM outputs as two digits. For example, if the FSM outputs were Init = 1 and Done = 0 in a state called A, then you would draw the corresponding bubble as. ANSWER: [3] b) You are to design a circuit that stores the last three valid 8-bit data bytes produced by the device. Design the simplest circuit you can, and draw its schematic below. Hint: you do not need to use any signals generated by the FSM for this part. ANSWER: Page 20 of 24

21 [12] Q9. Consider a digital synchronous 32 x 5 memory: [1] (a) How many bits are in this memory? Solution 32 x 5 = 160 bits. Worth 1 mark. [2] (b) Give a diagram of the external connections to this memory; that is, show just the inputs and outputs of the memory, with appropriate names. Be sure also to show the direction of information flow of each input and output, with an arrow pointing in the correct direction. Assume that the data inputs and data outputs are separate. Solution: a box with 5 address lines (A0-A4) flowing in, 5 data in lines flowing in (DATAIN0-4), a R/W or WREN flowing in, a clock, and 5 data out lines flowing out (DATAOUT0-4)Worth 2 mark, -.5 for each mistake. [2] (c) Give the logic expression that generates the internal word (also called the select) line for word number 7 of the memory, using the labels as given in the diagram in part (b). Solution: Word7 = A4 A3 A2A1A0 Worth 2 marks. Page 21 of 24

22 Q9, cont d [7] (d) Using this memory, design a larger circuit (in schematic form) that acts like a memory but has the additional ability, under the control of a signal named ZERO to set all of the memory bits in this memory to zero. Your circuit can use any type of logic gate or flip-flop we have discussed in class. For a finite state machine, show the state machine as a box with its inputs and outputs, and give its state diagram separately. Solution: Worth 7 marks. Page 22 of 24

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University of Toronto Faculty of Applied Science and Engineering Edward S. Rogers Sr. Department of Electrical and Computer Engineering

University of Toronto Faculty of Applied Science and Engineering Edward S. Rogers Sr. Department of Electrical and Computer Engineering Final Eamination ECE 4F - Digital Systems Eaminers: S. Brown, J.