Memories. Design of Digital Circuits 2017 Srdjan Capkun Onur Mutlu.

Size: px

Start display at page:

Download "Memories. Design of Digital Circuits 2017 Srdjan Capkun Onur Mutlu."

Jean Singleton
5 years ago
Views:

1 Memories Design of Digital Circuits 2017 Srdjan Capkun Onur Mutlu Adapted from Digital Design and Computer Architecture, David Money Harris & Sarah L. Harris 2007 Elsevier 1

2 What will we learn today? Common sequential building blocks Counters Shift registers How can we store data? Array organization of memories 2

3 Common Sequential Building Blocks Various Counters Up / down, program counters Serial / Parallel Converters Serial In - Serial Out : Shift Register Serial In - Parallel Out Parallel In - Serial Out Parallel In - Parallel Out : Normal Register 3

4 + Counters Increments on each clock edge. Used to cycle through numbers. For example, 000, 001, 010, 011, 100, 101, 110, 111, 000, 001 Example uses: Digital clock displays Program counter: keeps track of current instruction executing Symbol Implementation CLK N CLK Q Reset N 1 N N r Reset N Q 4

5 Shift Register Shift a new value in on each clock edge Shift a value out on each clock edge Serial-to-parallel converter: converts serial input (S in ) to parallel output (Q 0:N-1 ) Symbol CLK Implementation Q N S in S out S in S out Q 0 Q 1 Q 2 Q N-1 5

6 Shift Register with Parallel Load When Load = 1, acts as a normal N-bit register When Load = 0, acts as a shift register Now can act as a serial-to-parallel converter (S in to Q 0:N-1 ) or a parallel-to-serial converter (D 0:N-1 to S out ) Load Clk S in D 0 D 1 D 2 D N S out Q 0 Q 1 Q 2 Q N-1 6

7 Motivation: Memory Elements Memories are large blocks A significant portion of a modern circuit is memory. Memories are practical tools for system design Programmability, reconfigurability all require memory Allows you to store data and work on data Not all algorithms are designed to process data as it comes, some require data to be. Data type determines required storage SMS: 160 bytes 1 second normal audio: 64 kbytes 1 HD picture: 7.32 Mbytes 7

8 Die photograph of an Intel processor in 45nm 8

9 Larger Memory Blocks 9

10 How can we store data Flip-Flops (or Latches) Very fast, parallel access Expensive (one bit costs 20+ transistors) 10

11 How can we store data Flip-Flops (or Latches) Very fast, parallel access Expensive (one bit costs 20+ transistors) Static RAM (we will describe them in a moment) Relatively fast, only one data word at a time Less expensive (one bit costs 6 transistors) 11

12 How can we store data Flip-Flops (or Latches) Very fast, parallel access Expensive (one bit costs 20+ transistors) Static RAM (we will describe them in a moment) Relatively fast, only one data word at a time Less expensive (one bit costs 6 transistors) Dynamic RAM (we will describe them a bit later) Slower, reading destroys content (refresh), one data word at a time, needs special process Cheaper (one bit is only a transistor) 12

13 How can we store data Flip-Flops (or Latches) Very fast, parallel access Expensive (one bit costs 20+ transistors) Static RAM (we will describe them in a moment) Relatively fast, only one data word at a time Less expensive (one bit costs 6 transistors) Dynamic RAM (we will describe them a bit later) Slower, reading destroys content (refresh), one data word at a time, needs special process Cheaper (one bit is only a transistor) Other storage technology (hard disk, flash) Much slower, access takes a long time, non-volatile Per bit cost is lower (no transistors directly involved) 13

14 Array Organization of Memories Efficiently store large amounts of data Consists of a memory array (stores data) Address selection logic (selects one row of the array) Readout circuitry (reads data out) Address An M-bit value can be read or written at each unique N-bit address All values can be accessed, but only M-bits at a time Access restriction allows more compact organization N Array M Data 14

15 Memory Arrays Two-dimensional array of bit cells Each bit cell stores one bit An array with N address bits and M data bits: 2 N rows and M columns Depth: number of rows (number of words) Width: number of columns (size of word) Array size: depth width = 2 N M Address Data Address N Array Address 2 Array depth M Data Data width 15

16 Memory Array: Example bit array Number of words: 4 Word size: 3-bits For example, the 3-bit word at address 10 is 100 Address Data Address 2 Array depth Data width 16

17 Memory Arrays Address word x 32-bit Array 32 Data 17

18 Types of Memories Volatile memories (loses data when power is off) Static Random Access Memory (SRAM) Dynamic Random Access Memory (DRAM) Non-volatile memories (keeps data even without power) Read Only Memory (ROM) Various forms of flash memory (i.e. EEPROM) 18

19 Static Random Access Memory Volatile: Stores data by cross coupled inverters, once data is the inverters keep the value (therefore static) Historically called Random Access Memory, because data can be accessed in any order (unlike magnetic tapes which allowed only serial access) 19

20 Dynamic Random Access Memory wordline bitline wordline Volatile: Stores data by charging a (small) capacitor bitline + + Problem is that the charge on the capacitor will slowly discharge (memory will forget the value) with time. It is called Dynamic, because we have to refresh the contents before memory forgets what it. The larger the capacitor, the longer it takes to forget This costs area, ingenious methods are used to increase capacitance 20

21 Memory Array Organization Storage nodes in one column connected to one bitline Address decoder activates only ONE wordline Content of one line of storage available at output Address 2 2:4 Decoder wordline 3 wordline 2 wordline 1 wordline 0 bitline 2 bitline 1 bitline 0 Data 2 Data 1 Data 0 21

22 Memory Array Organization Storage nodes in one column connected to one bitline Address decoder activates only ONE wordline Content of one line of storage available at output Address :4 Decoder wordline 3 Active wordline wordline 2 wordline 1 wordline 0 bitline 2 bitline 1 bitline 0 Data 2 Data 1 Data

23 How is Access Controlled? Access transistors configured as switches connect the bit storage to the bitline. Access controlled by the wordline wordline bit bitline bitline wordline wordline bitline bitline DRAM SRAM 23

24 Read Only Memories Non Volatile: Read Only Memories (ROM) can be made much denser No need to change the content (no storage transistors) Denser array Used for keeping content that will not change Program of an embedded system Configuration data Look up tables Re-writable (flash) memories are commonly used These are actually programmable, but writing is very slow From an application point of view identical to ROMs 24

25 ROMs: Dot Notation Address 2 2:4 Decoder wordline bit cell containing 0 bitline 01 wordline bitline 00 bit cell containing 1 Data 2 Data 1 Data 0 25

26 ROM Storage Address 2 2:4 Decoder Address Data depth 00 width Data 2 Data 1 Data 0 26

27 ROM Logic 2:4 Decoder 11 Address 2 10 Data 2 = A 1 A 0 Data 1 = A 1 + A 0 01 Data 0 = A 1 A 0 00 Data 2 Data 1 Data 0 27

28 Logic with Memory Arrays Implement the following logic functions using a 22 3-bit memory array: X = AB Y = A + B Z = A B A, B 2 2:4 Decoder wordline 3 wordline 2 wordline 1 wordline 0 bitline 2 bitline 1 bitline 0 X Y Z 28

29 Logic with Memory Arrays Called lookup tables (LUTs): look up output at each input combination (address) 4-word x 1-bit Array Truth Table A B Y A B 2:4 Decoder 00 A 1 01 A bitline 29

30 Multi-ported Memories Port: address/data pair 3-ported memory: 2 read ports (A 1 /RD 1, A 2 /RD 2 ) 1 write port (A 3 /WD 3, WE 3 enables writing) Small multi-ported memories are called register files CLK N N A1 A2 WE3 RD1 RD2 M M N M A3 WD3 Array 30

31 Memory Arrays in Verilog // 256 x 3 memory module with one read/write port module dmem( input clk, // clock input we, // write enable input [7:0] a // 8-bit address input [2:0] wd, // 3-bit write data output [2:0] rd); // 3-bit read data reg [2:0] RAM[255:0]; // Memory array, holds // 256 entries each 3 bits wide assign rd = RAM[a]; // Read access clk) if (we) RAM[a] <= wd; endmodule // with rising clock // if write enable // write data is in array 31

32 What have we learned? Different ways of storing data Registers Static Memory Dynamic Memory Array organization Compact form One row active at a time 32

Chapter 5. Digital Design and Computer Architecture, 2 nd Edition. David Money Harris and Sarah L. Harris. Chapter 5 <1>

Chapter 5. Digital Design and Computer Architecture, 2 nd Edition. David Money Harris and Sarah L. Harris. Chapter 5 <1> Chapter 5 Digital Design and Computer Architecture, 2 nd Edition David Money Harris and Sarah L. Harris Chapter 5 Chapter 5 :: Topics Introduction Arithmetic Circuits umber Systems Sequential Building