HANSABA COLLEGE OF ENGINEERING & TECHNOLOGY (098) SUBJECT: DIGITAL ELECTRONICS ( ) Assignment


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1 Assignment 1. What is multiplexer? With logic circuit and function table explain the working of 4 to 1 line multiplexer. 2. Implement following Boolean function using 8: 1 multiplexer. F(A,B,C,D) = (2,3,5,7,8,9,12,13,14,15) 3. Implement the given function using multiplexer. F (A, B, C) = Ʃ (1, 3, 5, 6) 4. Implement the given function using 8 X 1 Multiplexer F (A,B,C,D) = Σm (0,1,2,3,5,8,9,11,14) 5. Design a 8 to 1 multiplexer by using the four variable function given by F(A,B,C,D) =Σm (0,1,3,4,8,9,15). 6. Implement following logic function using 8X1 MUX. F = Σm (0, 1, 3, 5, 7, 11, 13, 14, 15) 7. Explain half adder and full adder in detail. 8. Design a full adder using 3X8 decoder followed by gates. 9. Design 4 X 16 decoder using two 3 X 8 decoder. 10. Explain full adder and design a full adder circuit using 3 to 8 decoder and two OR gates. 11. Implement Full Subtractor Circuit with the help of Decoder and logic gates. 12. Explain Full Subtractor with truth table and circuit diagram. 13. Design one bit magnitude comparator. 14. Draw & explain in brief pin diagram of 7485 fourbit magnitude comparator. 15. Design 3bit parity generator circuit using even parity bit. 16. Define Following Terms 1. Positive Logic 2. Negative Logic 3. Fan In 4. Fan out 5. Noise Margin 17. State and Prove D Morgan Theorem. 18. State and Prove D Morgan Theorem. 19. Convert the expression Y= A + BC into the standard SOP form. 20. Simplify Using boolean laws and draw the logic diagram for the simplified expression. 21. Simplify following Boolean function by using the tabulation method 22. Prove that NAND gate as Universal gate. 23. Simplify following Boolean function using VEM. 24. State and Prove D Morgan Theorem for three variables.
2 25. Convert the decimal number to base 3, base 4, base 7 and base 8. Design a combinational circuit with four input lines that represent a decimal digit in BCD and four output lines that generates the 9 s Complement of the input digit. 26. Simplify Boolean function using KMap 27. State the advantages of Finite State Machine. 28. Explain JK flip flop with its characteristic table and excitation table. 29. Explain Master Slave JK flipflop with truth table and circuit diagram. 30. Draw and explain Ring counter 31. Design a counter to generate the repetitive sequence 0, 1, 2,4,3, Plot the out waveform referenced to the clock signal assuming the initial contents of the flipflops is q=0. Assume all flipflops are edge triggered. 33. Write short note on Programmable Logic Arrays. 34. Explain the Fundamental Mode Model of Asynchronous State Machine with suitable example 35. Find the 10 s complement of the following: (1) (935)11 (2) (6106) Using D as the VEM, reduce Y=AʹBʹCʹDʹ+AʹBʹCDʹ+ABʹCʹDʹ+ABʹCʹD+ABʹCDʹ+ABʹCD. 37. Obtain the truth table of the function: F= xy + xyʹ + yʹz. 38. Explain RS flip flop in detail. 39. Design BCD to Excess3 code convertor circuit. 40. Show that (A + C) (A + D) (B + C) (B + D) = AB + CD. 41. Explain Moore machine. 42. Design Modulo8 counter using T flip flop. 43. Explain edge triggering and level triggering. 44. Explain 4 bit serial in serial out shift register. 45. Design 3bit synchronous up counter using T flip flop. 46. Give classification of logic families. Also list the characteristics of digital IC. 47. Explain Half Adder circuit with neat diagram. 48. Write short note on Read Only Memory (ROM).
3 49. What is race around condition in JK flip flop. 50. How does a counter works as frequency divider? Explain with suitable example. 51. A combinational logic circuit is defined by the functions: F1= Ʃ (3, 5, 6, 7) and F2= Ʃ (0, 2, 4, 7). 52. Implement the circuit with a PLA having three inputs, four product terms and two outputs 53. Convert decimal number (0.252)10 to binary with an error less than 1 %. 54. Minimize the following Boolean expressions. 1. X = ( (A'B'C')' + (A'B)' )' 2. Y = AB + ABC' + A'BC + A'BC' 55. Using D as the MEV, reduce Y = A'B'C'D' + A'B'CD' + AB'C'D' + AB'C'D + AB'CD + AB'CD'. Minimize following Boolean function using Kmap & design the simplified function using logic gates. F = Σ m(1, 2, 4, 6, 7, 11, 15) + Σ d(0, 3). 56. Draw a frequency divider using JK FFs to divide input clock frequency by a factor of 8. Reduce following Boolean function and then realize the reduced one using NOR gate only. X = A (B'+C') (A+D) 57. For the figures 1, 2, & 3, plot the output waveforms referenced to the clock signal assuming the initial contents of all FFs is Q = 0. Assume all FFs are edge triggered.
4 58. Draw a general model for a sequential or state machine. Also list out various types of FSMs. 59. Fill in values for S & R to cause the Q values of the SR FF given in figure Plot the output waveform for the inputs shown in figure 5, assuming the initial contents of the FF is Q = Design a 3bit synchronous up counter using Kmaps and positive edgetriggered JK FFs. 62. Draw & explain in brief a high assertion input SR latch. 63. Construct next state table for the state diagram given in figure 6.
5 64. What do you mean by an output glitch problem? Explain any one method to eliminate the glitch from an OFL circuit. Draw suitable waveforms and logic diagrams. 65. Draw & explain in brief general architecture of Xilinx FPGA. 66. Explain critical race problem of an asynchronous state machines with the help of one example. 67. Implement following functions using ROM. F1 = Σ m(1, 3, 4, 6) F2 = Σ m(2, 4, 5, 7) F3 = Σ m(0, 1, 5, 7) F4 = Σ m(1, 2, 3, 4) 68. With the help of next state D input maps given in figure 7, construct IFL using MUXs of suitable size and number. 69. Explain oscillation problem of an asynchronous state machines with the help of one example.
6 70. Compare TTL, ECL, & CMOS logic families. 71. Reduce the given function using Kmap and implement the same using gates. F(A,B,C,D ) = Σm (0,1,3,7,11,15) + Σd ( 2,4) 72. Do as directed (i) Convert (75)10 = ( )2 (ii) Convert (101011)2 = ( )10 (iii) Convert ( )2 = ( )16 = ( )8 (iv) What is self complementing code? Represent (472)10 in 2421 self complementing code. (v) Find the logic required at R input. (i) Convert (96)10 to its equivalent gray code and EX3 code. (ii) Perform addition in BCD format (79)BCD + (16)BCD 73. Discuss NAND gate as universal gate (implement NOT, AND, OR & NOR gate using NAND gate). 74. Perform subtraction of (78)10 (58)10 using 2 s complement method. 75. Draw the truth table of full subtractor and implement using minimum number of logic gates. 76. Convert D flip flop into SR flip flop. 77. Compare ROM, PLA and PAL 78. Design 4bit ripple counter using negative edge triggered JK flip flop. 79. With neat sketch design 4bit bidirectional shift register. 80. Define followings ( i to iv with respect to logic families and v to vii with respect to finite state machine) (i) Fan in (ii) Fan out (iii) Noise Margin (iv) Propogation delay (v) State table (vi) Melay machine (vii) Moore machine 81. Simplify using Boolean laws and draw the logic diagram for the given expression.
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