# QUESTION BANK (DESCRIPTIVE) UNIT I Binary Systems, Boolean Alegebra & Logic Gates. 1. What are the characteristics of Digital Systems.

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1 SIDDHARTH INSTITUTE OF ENGINEERING & TECHNOLOGY :: PUTTUR Siddharth Nagar, Narayanavanam Road QUESTION BANK (DESCRIPTIVE) Subject with Code : Digital Logic Design(18CS502 ) Year & Sem: I-B.Tech & II-Sem Course & Branch: B.Tech - CSE Regulation: R18 UNIT I Binary Systems, Boolean Alegebra & Logic Gates 2 MARKS QUESTIONS 1. What are the characteristics of Digital Systems. (2M) 2. Convert (15) 10 to Binary (2M) 3. Explain about Diminished Radix complement (2M) 4.What is meant by parity bit? (2M) 5. Define duality property. (2M) 6. Define binary logic? (2M) 7. Which gates are called as the universal gates? What are its advantages? (2M) 8. State the associative property of Boolean algebra. (2M) 9 Explain classification of Number system (2M) 10. What is a prime implicate? (2M) 10 MARKS QUESTIONS 1 a) Convert the following numbers (L5) (5M) i)( ) 10 to Octal number ii)( ) 2 to base-8 and base-4 iii)(4567) 10 to base2 iv) (4D.56) 16 to Binary b) Subtract (111001) 2 from (101011) using 1 s complement? (L5) (5M) 2. a) Represent the decimal number 3452 in i)bcd ii)excess-3 (L5) (5M) b) perform (-50)-(-10) in binary using the signed-2 s complement (L4) (2M) c) Determine the value of base x if(211)x=(152) 8 (L4) (2M) 3. a) Convert the following numbers (L5) (3M) i) (250.5) 10 = ( ) 2 ii) ) (673.23) 10 = ( ) 8 iii)( ) 2 =( ) 8 b) Convert the following to binary and then to gray code (AB33) 16 (L2) (2M) Digital Logic Design Page 1

2 c) Perform the following Using BCD arithmetic (7129) 10 + (7711) 10 (L3) (3M) 4. Explain the Binary codes with examples? (L5) (10M) 5. a) What is Digital System? Characteristics of digital systems. (L5)(5M) b) Explain the difference between analog and digital systems (L5) (5M) 6. a) Design the circuit by Using NAND gates F= ABC + DE+ AB D (L5) (5M) b) Simplify and implementation the following SOP function using NOR gates (L3) (5M) F(A,B,C,D)= m(0,1,4,5,10,11,14,15) 7. Convert the following (L2) (5M) a)(1ad) 16 =( ) 10 b) (453) 8 =( ) 10 c) ( ) 2 =( ) 10 d) (5436) 10 =( ) 3. 8 a)explain binary to Gray & Gray to binary conversion with example? (L5) (5M) b) State and Explain the DeMorgan s Theorem and Consensus Theorem (L3) (5M) 9) Convert the following numbers (L2) (5M) i) (615) 10 = ( ) 16 ii) ) (214) 10 = ( ) 8 iii)(0.8125) 10 =( ) 2 iv) ( ) 10 =( ) 8 v)(54) 10 =( ) 2 10) Explain the Excess-3 code? Write about Error correction & Detection? (L5) (5M) \ Digital Logic Design Page 2

3 UNIT II Gate Level Minimization 2 MARKS QUESTIONS 1. What is meant by karnaugh map or K-Map method? (2M) 2. Define Pair, Quad, and Octet (2M) 3. What are called don t care conditions? (2M) 4. What are the 2 forms of Boolean expression? (2M) 5. Define Minterm & Maxterm (2M) 6. Explain SOP and POS form (2M) 7. Explain Canonical SOP form (2M) 8. State De Morgan's theorem (2M) 9. Explain demorgan s law (2M) 10. What is an essential prime implicante (2M) 10 MARKS QUESTIONS 1. Simplify the Boolean expression using K-MAP (L5) (10M) F(A,B,C,D,E)= m(0,1,4,5,16,1721,25,29) 2. Simplify the Boolean expression using K-MAP (L5) (10M) F(A,B,C,D) = m(1,2,3,8,9,10,11,14) +d(7,15) 3. Simplify the Boolean expression using K-map and implement using NAND gates F(A,B,C,D) = m(0,2,3,8,10,11,12,14) (L4) (10M) 4. Simplify the Boolean expressions to minimum number of literals i) (A + B)(A + C )(B + C ) (L3) (3M) ii) AB + (AC) + AB C (AB + C) iii) (A+B) (A +B ) (L3)(4M) (L5) (3M) 5. Reduce the expression f(x,y,z,w)= πm(0,2,7,8,9,10,11,15).d (3,4) using K-Map? (L5) (10M) 6. Simplify the Boolean expression using K-map? (L5) (10M) F(A,B,C,D,E)= m(0,2,4,6,9,11,13,15,17,21,25,27,29,31) Digital Logic Design Page 3

4 7. Obtain the a) SOP b) POS expression for the function given below (L5) (10M) F(A,B,C,D)= = m(0,1,2,5,8,9,10) 8. a) Simplify the Boolean expressions to minimum number of literals (L4) (5M) i) X + XY + X Z + XYZ ii) (X+Y) (X+Y ) 9. b) Obtain the Complement of Boolean Expression (L4) (5M) i) A+B+A B C ii) AB + A (B +C) + B (B+D) 10. Determine the minimal sum of product form of (L4) (5M,5M) a) f(w,x,y,z)= m(4,5,7,12,14,15) +d(3,8,10) b) F(A,B,C,D)=πM(0,3,5,6,8,12,15) Digital Logic Design Page 4

5 UNIT III Combinational Logic 2 MARKS QUESTIONS 1. Define combinational logic. (2M) 2. Explain the design procedure for combinational circuits (2M) 3. Define Half adder and full adder (2M) 4. What is Decoder (2M) 5. Define Encoder? (2M) 6. Construct 2:1 multiplexer? (2M) 7. Define subtractor? (2M) 8. Difference between encoder and decoder (2M) 9. Define de-multiplexer? (2M) 10. Explain Applications of Multiplexer (2M) 10 MARKS QUESTIONS 1. Implement BCD to 7-segment decoder for cathode type using 4:16 decoder? (L5) (10M) 2. A)Implement the following Boolean function using 8:1 multiplexer (L5) (5M) F(A, B, C, D) = A BD + ACD + A C D +B CD B)Explain about Full Adder? (L2) (5M) 3. A) Explain about 2-bit Magnitude Comparator? (L2) (5M) B) Explain Full binary subtractor in detail? (L2) (5M) 4. Design the combinational circuit binary to gray code? (L5) (10M) 5. A)Explain about Binary Multiplier? (L2) (5M) B)What is memory decoding? Explain about the construction of 4 X 4 RAM? (L2) (5M) 6. A) Implement the following Boolean function using 8:1 multiplexer (L5)(5M) F(A,B,C.D) = Σm (0,1,2,5,7,8,9,14,15) B) Explain about Decimal Adder? (L2) (5M) 7. A)Design a 4 bit adder-subtractor circuit and explain the operation in detail? (L5) (5M) B) Explain the functionality of a Multiplexer? (L2) (5M) Digital Logic Design Page 5

6 8. Explain The Half adder? Implement the full adder using two half adders (L5) (10M) 9. A)Design a 4 bit binary parallel subtractor and the explain operation in detail? (L5) (5M) B) Design the combinational circuit of 4 Bit Parallel Adder? (L5) (5M) 10. a)what is the truth table of Half-subtractor? (L1) (2M) b) Define priority encoder? (L1) (2M) c) Explain the design procedure for combinational circuit? (L1) (2M) d) Design 4 bit parallel Adder? (L5) (2M) e)define Multiplexer and applications of multiplexer? (L1) (2M) Digital Logic Design Page 6

7 UNIT IV Synchronous Sequential Logic 2 MARKS QUESTIONS 1. What are the classifications of sequential circuits? (2M) 2. What is the operation of D flip-flop? (2M) 3. What is flip-flop (2M) 4. Define Race Around Condition (2M) 5. Difference between latch and flip-flop (2M) 6. Define Propagation Delay (2M) 7. What is Master Slave Flip-flop (2M) 8. Explain Shift Registers (2M) 9. What are the applications of Flip-flops (2M) 10. What is state diagram (2M) 10 MARKS QUESTIONS 1. A) Explain the Logic diagram of JK flip-flop? (L2) (5M) B) Write difference between Combinational & Sequential circuits? (L4) (5M) 2. A) Explain the Logic diagram of SR flip-flop? (L2) (5M) B) Design and draw the 3 bit up-down synchronous counter? (L5) (5M) 3. A) Draw and explain the operation of D Flip-Flop? (L5) (5M) B) Explain about Shift Registers? (L2) (5M) 4. A) Draw and explain the operation of SR LATCH? (L5) (5M) B) Explain about Ring counter? (L2) (5M) 5. A) Explain about ripple counter? (L2) (5M) B) What is state assignment? Explain with a suitable example? (L2) (5M) 6. Explain the working of the following (L2 & L5) (10M) i) J-K flip-flop ii) S- R flip-flop iii) D flip-flop 7. Explain the design of a 4 bit binary counter with parallel load in detail? (L2) (10M) Digital Logic Design Page 7

8 8. How does it set eliminate is a Master slave J-K flip-flop? (L2)(10M) 9. A) Explain synchronous and ripple counters compare their merits and demerits? (L2) (5M) B) Design a 4 bit binary synchronous counters with D-flip flop? (L5 (5M) 10. a)write the truth table of clocked T- Flip Flop? (L1) (2M) b) Define shift registers? (L1) (2M) c) Write the differences between latches and flip flops? (L1)(2M) d) Write the differences between synchronous and asynchronous counters? (L1) (2M) e)define Flip-flop and various types of flip flops? (L1) (2M) Digital Logic Design Page 8

9 UNIT V Memory and Programmable Logic, Digital Logic Circuits 2 MARKS QUESTIONS 1. Explain the Classification of memory (2M) 2. Define ROM (2M) 3. What is Read and Write Operations (2M) 4. List the major differences between PLA and PAL (2M) 5. Define PLA (2M) 6. Differentiate volatile and non-volatile memory (2M) 7. What are the different types of ROM (2M) 8. Define the Static RAM and Dynamic RAM (2M) 9. What is BIT,BYTE and WORD (2M) 10. What is Cache Memory (2M) 10 MARKS QUESTIONS 1. A) Write difference between PROM,PLA &PAL? (L4) (5M) B) Explain about Hamming code? (L2) (5M) 2. Encode the 11-bit code into 15 bit information code? (L3)(10M) 3. Implement the following function using PLA (L5)(10M) A(x,y,z)= m(1,2,4,6) B(x,y,z)= m(0,1,6,7) C(x,y,z)= m(2,6) 4. Design PAL for a combinational circuit that squares a 3 bit number? (L5)(10M) 5. Write about the following (L2)(10M) i) Transistor-transistor Logic (TTL) ii) Emitter coupled Logic (ECL) iii) CMOS Logic 6. Construct the PROM using the conversion from BCD code to Excess-3 code? (L5)(10M) 7. Implement the following functions using PLA. (L5)(10M) A(x,y,z) = m(1,2,4,6) B(x,y,z) = m(0,1,6,7) c(x,y,z) = m(2,6) 8. A)Construct the PROM using the conversion from BCD code to Excess-3 code? (L5)(10M) 9. A)Explain about TTL family? (L2)(5M) B) Explain about memory decoding error detection and correction? (L2)(5M) Digital Logic Design Page 9

10 10. a)write the difference between PLA & PAL? (L1) (2M) b) Define fan out of a logic gate? (L1) (2M) c) What is the function of EAROM? (L1) (2M) d) Define CMOS? (L1) (2M) e) Write a short notes on Programmable array Logic? (L1) (2M) Prepared by: P Nirupama, G Prasad Babu, V Balaji Digital Logic Design Page 10

11 SIDDHARTH GROUP OF INSTITUTIONS :: PUTTUR Siddharth Nagar, Narayanavanam Road QUESTION BANK (OBJECTIVE) Subject with Code : Digital Logic Design(18CS502) Year & Sem: I-B.Tech & II-Sem Course & Branch: B.Tech - CSE Regulation: R18 UNIT I Binary Systems, Boolean Alegebra & Logic Gates 1. (75.23) is a Octal number convert to it equivalent binary number [ ] A) B) C) D) s complement of 1234 is [ ] A) 8764 B) 8765 C) 7886 D) Find 2 s complement of ( ) [ ] A) B) C) D) none 4. Non-weighted code is [ ] A) Gray code B) Decimal C) Binary D) octal 5. Decimal value base is [ ] A) 10 B) 8 C)16 D) 2 6. A 1 B 1 = [ ] A) A 1 +B 1 B) (A+B) 1 C) AB D) A+B 9. BCD code for 92 [ ] A) B) C) D) s complement of (52520) 10 is [ ] A)42479 B)47479 C)47480 D) (1217) 8 is equivalent to [ ] A) (1217) 16 B) (028F) 16 C) (2297) 10 D) (0B17) A decimal number 19 is in excess 3 code is written as [ ] A) B) C) D) The higher significant bit of this result is called [ ] A) Sum B) carry C) 0 D) none 14. Distributive law is [ ] Digital Logic Design Page 11

12 A) A(B+C) =AB+AC B) AB=BA C) A+(B+C)=(A+B)+C D) none 15. A+1 = [ ] A) A B) 1 C) 0 D) none 16. ABC+ABC = [ ] A) A B) AB C) C D) AC 17. A+AB= [ ] A) 1 B)0 C) A D) none 18. Decimal 12 is in binary number system is [ ] A) 1010 B) 1111 C) 1011 D) Find 1 s complement of ( ) [ ] A) B) C) D) none 20. What is the maximum number of different boolean functions involving n Boolean variables? [ ] A) n 2 B)2 n C)2*n D)2 2n 21. bit represent the sign of the number [ ] A)MSB B)LSB C)both D)none 22. Which gate is generate complement of output to given input [ ] A) NOT B) NAND C)OR D) XNOR 23. codes are non weighted codes [ ] A) Gray B) decimal codes C) binary D) none 24. (A+B)+C=A+(B+C) is law [ ] A) Associative law B) commutative law C) Distributive law D) none 25. Example of weighted code [ ] A) gray B) 8421 C) excess-3 D) none is a binary value convert to it equivalent octal [ ] A) 71 B) 70 C) 15 D) none is a octal value convert to it equivalent decimal [ ] A) 8 B) 10 C) A D) none 28. ASCII stand for [ ] B) American standard coded for information interchange C) American standard coded for interchange information C) both D) none 29. theorem states that AB+(AC) 1 +BC=AB+(AC) 1 [ ] B) Consensus theorem B) duality C) associative law D) none 30. A.A 1 = [ ] Digital Logic Design Page 12

13 B) 1 B)0 C) A D) none 31. A+A 1 B= [ ] A) A+B B) A+BA C) 0 D) none 32. Convert AB6 to binary [ ] A) B) C) D) SOP denotes [ ] A) B) π C)both A&B D) none s complement is also called as [ ] A) Radix B) Dimnished radix C)2 D) Which gate is generate complement of output to given input [ ] A) NOT B) NAND C)OR D) XNOR 36. The of digital logic gate refers to the number of inputs [ ] A) Fan-in B) fan-out C) both D) none 37. POS denotes [ ] A) B)π C) both D) none 38. (A+B)+C=A+(B+C) is law [ ] Associative law B) commutative law C) Distributive law D) none base is 4 convert to decimal value [ ] A) 45 B) 43 C) 42 D) none is decimal value convert to its binary value [ ] A) B) C) D) Digital Logic Design Page 13

14 UNIT II Gate Level Minimization 1. Vietch diagram also known as [ ] A) Karnaugh map B) logic gate C) BSD D) none 2. 2 variable k map contains cells [ ] A) 8 B) 4 C)2 D)none 3. The map method is first proposed by [ ] A) Vietch B) charlas C) karnaugh D) none 4. A grouping of 8 bits in K-map known as [ ] A)byte B) octet C) quad D) none 5. Example of UNIVERSAL GATE is [ ] A)NAND B)NOT C) OR D) none 6. The code used for labeling the cells of k map is [ ] A) gray B) octal C) BCD D) none 7. AND Gate requires Minimum number of inputs. [ ] A)2 B)1 C)4 D) none 8. A pair is a group of adjacent cells in a k-map [ ] A) 2 B) 4 C)8 D) variable k map contains cells [ ] A) 6 B) 8 C) 5 D) is a group of 8 adjacent cells in K-Map [ ] A)octet B)pair C) quad D) none 11. don t care condition represented label as [ ] A) S B) X C) d D)both B&C 12. The output levels are indicated by X or d in the truth tables and are called [ ] A) don t care conditions B) minterms C) output D) none 13. Which gate is not universal gate [ ] A) NAND B) NOR C) XOR D) none 14. Consider the following Boolean function of four variables f(w,x,y,z)= m(1,3,4,11,12,14) The function is [ ] A) independent of one variable B)independent of two variables C) independent of three variables D) Dependant on all the variables Digital Logic Design Page 14

15 15. 4 variable k map contains cells [ ] A) 12 B) 16 C) 15 D) In K-map Pair eliminates variable from output expression. [ ] A) One B)Two C)Three D)Zero 17. In K-map Quad eliminates variable from output expression. [ ] A) One B)Two C)Three D)Zero 18. In K-map octet eliminates variable from output expression. [ ] A) One B)Two C)Three D)Zero variable k map contains cells [ ] A) 32 B) 36 C) 15 D) The sum of all the minterms of a given Boolean function is equal to [ ] A) Zero B)One C)Two D)Three 21. The product of all the maxterms of a given Boolean function is equal to [ ] A) Zero B)One C)Two D)Three 22. Let f(a,b) = A+B, simplified expression for function f(f(x+y,y),z) is [ ] A) x+y+z B)xyz C)1 D)xy+z 23. Maximum number of prime implicants with n binary variable in the reduced expression is [ ] A) 2 n n-1 D)2+n B) 2*n C)2 24.The Logical expression y= )= m(0,3,6,7,10,12,15) is equivalent to [ ] A) Y= πm(0,3,6,7,10,12,15) B)y= πm(1,2,4.,5,8,9,11,13,14) C) Y= M(0,3,6,7,10,12,15) B)y= M(1,2,4.,5,8,9,11,13,14) 25. The minimum number of 2 input NAND gates required to implement the following Boolean function f= (x +y )(z+w) [ ] A) 3 B)4 C)5 D)6 26.What is the value of A+A B [ ] A)A B)B C)0 D)A+B 27. method is used for to simplify the boolean expressions [ ] A) K-map B)Algebric rules C)Tabular method D)ALL Digital Logic Design Page 15

16 28. The pictorial representation of truth table is also called as [ ] A) K-Map B)Tabular map C)Both A&B D)None 29. The map method is modified by [ ] A) Vietch B) charlas C) karnaugh D) none 30. The Sum of product Boolean expression represented the symbol is [ ] A) π B) C) D) 31. The Product of sum Boolean expression represented the symbol is [ ] A) π B) C) D) 32. method is also called as Quine-Mc Cluskey method [ ] A) K-map B)Tabular C)Graph D)None 33.The minimized expression of Y= A B C+A BC is [ ] A) A B B)A C C)AB D)BC 34. The minimized expression of Y=A B C+A BC+ABC+ABC is [ ] A) AC+BC B) A+C C)A C+AB D)AB 35. The Boolean expression is f(a,b,c,d) of m7 representation is [ ] A) ABCD B) ABC D C)A BCD D)A B C D 35. The Boolean expression is f(a,b,c,d) of M12 representation is [ ] A) A+B+C+D B) A+B+C+ D C)A +B+C+D D)A +B +C+D 36. In K-map using the sequences codes are [ ] A) Excess-3 B)Gray C)Binary D)BCD NAND gates equivalent to function. [ ] A)AND 2)OR C)Ex-OR D)Ex-NOR NAND gates equivalent to function. [ ] A)AND 2)OR C)Ex-OR D)Ex-NOR NOR gates equivalent to function. [ ] A)AND 2)OR C)Ex-OR D)Ex-NOR NOR gates equivalent to function. [ ] A)AND 2)OR C)Ex-OR D)Ex-NOR Digital Logic Design Page 16

17 UNIT III Combinational Logic 1. A Combinational circuits consists of [ ] A) Input variables B) logic gates C) output variables D) all of these 2. circuits needs two binary inputs and two binary outputs. [ ] A) Full adder B) half adder C) sequential D) counter 3. In half adder circuit the inputs are high sum is and carry. [ ] A) 0,0 B) 0,1 C) 1,0 D) 1,1 4. A is a combinational circuit that converts binary information from n inputs lines to a maximum of 2 n unique output lines. [ ] A) Encoder B) Decoder C) both A & B D) none of these 5. circuits needs three binary inputs and two binary outputs. [ ] A) Full adder B) half adder C) combinational logic D) none 6. A decoder with n inputs then it produce out puts [ ] A) 2n B)2 n C)n D) n+2 7. A is a combinational circuit that converts binary information from n inputs lines to a of 2 n unique output lines. [ ] A) Encoder B) Decoder C) both A & B D) none of these 8. In which circuits memory is not required [ ] A) Sequential circuits B) synchronous circuits C) both D) none 9. In full adder circuit, the inputs are high sum is and carry. [ ] B) 0,0 B) 0,1 C) 1,0 D) 1,1 10. In full subtractor circuit, the inputs are high sum is and carry. [ ] A) 0,0 B) 0,1 C) 1,0 D) 1,1 11. A is a special combinational circuit designed to compare the binary variables. [ ] A) Multiplexer B)Decoder C)Comparator D)Demultiplexer 12. A circuit with n inputs and produce 2 n outputs. [ ] A) Multiplexer B)Decoder C)Comparator D)Demultiplexer 13. circuit acts as inverse operation of a decoder. [ ] A) Decoder B)Multiplexer C)Encoder D)ALL 14. A circuit with 2 n inputs and produce n data outputs. [ ] A) Multiplexer B) Encoder C)Decoder D)None 15. In, if two or more inputs are equal to 1 at the same time, the input having the highest Priority will take precedence. [ ] Digital Logic Design Page 17

19 33. In full subtractor the inputs are high then difference is & barrow is [ ] A) 0,0 B) 0,1 C) 1,0 D) 1,1 34. Decimal adder is also called as [ ] A) Binary adder B) BCD Adder C) Binary Subtractor D) None 35. adder uses shift register [ ] A) Serial B) Parallel C) Both A&B B) None 36. In circuit there are no selection lines [ ] A) Multiplexer B) Demultiplexer C) Decoder D) None 37. In circuit the selection of specific output line is control by the value of selection lines [ ] A) Multiplexer B) Demultiplexer C) Decoder D) None 38. In full adder the simplified carry output is [ ] A) AB+AC+BC B) AB +A C+BC C) A B+A C+BC D) None 39. In Half adder the simplified carry output is [ ] A) BC B) AB C) A B D) None 40. adder uses register with parallel load capacity [ ] A) Serial B) Parallel C) Both A&B B) None Digital Logic Design Page 19

20 UNIT IV Synchronous Sequential Logic 1. In D-flip flop the input D=0 the output is [ ] A) 1 B) 0 C) X D) In asynchronous are to design [ ] A) easy B) difficult C) both A&B D) medium 3. In SR latch the S referred to [ ] A) Synchronous B) set C) start D) none 4. In T flip flop the input T=1 then Qn+1 is [ ] A) Qn B) Qn C) Qn+1 D) 0 5. In SR latch s=1,r=1 the state is [ ] A) No change B) reset C) set D ) indeterminate 6. In synchronous counter, if then flip flop complements the input at the time of clock edges [ ] A)T=1 B) J=K=1 C) both A & B D) none 7. In Binary counter counts in binary coded decimal from 0000 to and back to [ ] A)1001 B) 1111 C) 1000 D) In SR latch the S referred to [ ] A)Synchronous B) set C) start D) none 9. A is a circular shift register with only one flip flop being set at any particular time, all others are cleared. [ ] A) ring counter B) shift register C) binary counter D) none of these 10. A sequential circuits consists of [ ] A) storage element B) logic gates C) both A& B D) all of these 11. D-flip flop is also known as [ ] A) Delay flip flop B) SR latch C) JK flip flop D) none 12. Flip flops are used for [ ] A) Memory element B) delay element C) both D) none 13. A J-K flip flop is in No Change condition when the value of [ ] A) J=0 K=0 B) J=1 K=1 C) J=0 K=1 D) J=1 K=0 14. How is a JK Flip flop made to toggle state [ ] A) J=0 K=0 B) J=1 K=1 C) J=0 K=1 D) J=1 K=0 15. In counter all the flip flops are clocked simultaneously [ ] A) Asynchronous B)Synchronous C) Ripple D) none of these 16. A J-K flip flop is in No Change condition when the value of [ ] A) J=0 K=0 B) J=1 K=1 C) J=0 K=1 D) J=1 K=0 17.A is a register for counting the no of clock pulses arriving at its clock inputs. [ ] Digital Logic Design Page 20

21 A) Counter B) Register C) Flip Flop D) Decoder 18. How is a JK Flip flop made to toggle state [ ] A) J=0 K=0 B) J=1 K=1 C) J=0 K=1 D) J=1 K=0 19. In counter all the flip flops are clocked simultaneously [ ] A) Asynchronous B) Synchronous C) Ripple D) none of these 20. A is a group of flip flops [ ] A) Register B) latches C) counter D) none of these 21. In SR flip flop S=1,R=0 then the state is [ ] A) set B) reset C) nochange D) indeterminate state 22. D-flip flop is also known as [ ] A) Delay flip flop B) SR latch C) JK flip flop D) none 23.How is a JK Flip flop made to toggle state [ ] A) J=0 K=0 B) J=1 K=1 C) J=0 K=1 D) J=1 K=0 24. In counter all the flip flops are clocked simultaneously [ ] A) Asynchronous B)Synchronous C) Ripple D) none of these 25.In SR latch s=1,r=1 the state is [ ] A) No change B) reset C) set D ) indeterminate 26. In which circuits memory is required [ ] A) Sequential circuits B) synchronous circuits C) botha&b D) none 27. Flip flops are used for [ ] A) Memory element B) delay element C) both D) none GB= [ ] A) 2 30 B) 2 36 C) 2 32 D) none of these 29.In JK flip flop j=1,k=1 then the state is [ ] 1 A) Q n B) Q n C) both D) none of these 30. In which circuits memory is not required [ ] A) Sequential circuits B) synchronous circuits C) both D) none 31.In synchronous counter, if then flip flop complements the input at the time of clock edges [ ] A)T=1 B) J=K=1 C) both A & B D) none 32. Binary counter counts in binary coded decimal from 0000 to and back to 0000 [ ] A)1001 B) 1111 C) 1000 D) In SR latch the S referred to [ ] A)Synchronous B) set C) start D) none 34. In the binary synchronous counter if the present state of a 4-bit counter is A 3 A 2 A 1 A 0 =0011, then the next count is [ ] A) 0010 B) 0100 C) 0101 D) none of these 35. A is a circular shift register with only one flip flop being set at any particular time, all others are cleared. [ ] A) ring counter B) shift register C) binary counter D) none of these 36. The characteristic equation of SR Flipflop is Qn+1= [ ] Digital Logic Design Page 21

22 A) S+R Qn B) S +RQn C) S+R D) Qn 37. The characteristic equation of JK Flipflop is Qn+1= [ ] A) JQn +KQn B) JQn +K Qn C) JQn+KQn D) None 38. The characteristic equation of T Flipflop is Qn+1= [ ] A) TQn +T Qn B) TQn +T Qn C) TQn+TQn D) None 39. The characteristic equation of D Flipflop is Qn+1= [ ] A) DQn B) D Qn C) D D) D 40. sequential circuit is easier to design [ ] A) Asynchronous B)Synchronous C) Ripple D) none of these Digital Logic Design Page 22

23 UNIT V Memory and Programmable Logic, Digital Logic Circuits 1. The is a programmable logic device with a fixed OR array and a programmable AND array. [ ] A) PAL B) PLA C) PROM D) none of these 2. stores the binary information permanently. [ ] A) RAM B) ROM C) both A & B D) none of these 3. In Hamming code technique, if the data does not have any error, then C = [ ] A) B)0000 C) 1001 D) The process of retrieving the information from the memory is called operation. [ ] A) Read B) Write C)Both A&B D)None 5. A group of eight bits is called a [ ] A) Bits B) byte C) kilobyte D) none of these 6. The read only memory is a device [ ] A) Programmable logic B) combinational logic C) A & B D) none 7. ROM performs operation. [ ] A) Read B) Write C) Both A&B D)None 6. Types of ROM memories are [ ] A) EPROM B) EEPROM C) PROM D) All of these. 7. EEPROM abbreviated as [ ] A) Erasable Erasable PROM B) Electrically Erasable PROM C) Electrically- Electrically PROM D) none of these 8. is a nonsaturated digital logic family. [ ] A) ECL B) TTL C) both A & B D) none of these 9. The is a programmable logic device with a fixed OR array and a programmable AND array. [ ] A) PAL B) PLA C) PROM D) none of these 13. stores the binary information permanently. [ ] A)RAM B) ROM C) both A & B D) none of these 14. In Hamming code technique, if the data does not have any error, then C = [ ] A)10001 B)0000 C) 1001 D) The process of retrieving the information from the memory is called operation. [ ] A) Read B) write C) both read & write D) none 16. In the binary synchronous counter if the present state of a 4-bit counter is A 3 A 2 A 1 A 0 =0011, then the nest count is [ ] A) 0010 B) 0100 C) 0101 D) none of these 17. RAM performs operations [ ] A) Read B) write C) both A&B D)none 18. PAL stands [ ] Digital Logic Design Page 23

24 A) Programmable logic array B) programmable array logic C) both A & BD) none of these 19. A memory write stores binary information in group of bits called [ ] A) Words B) bytes C) GB D) none 20.SRAM is made of with [ ] A) capacitors B) register C) latches D) counter 21.How many types of memories are used in digital systems? [ ] A) 2 B) 3 C) 4 D) DRAM abbreviated as [ ] A) Delay RAM B)Determinate RAM C)Dynamic RAM D) none 23. To construct 2 k *n ROM is required OR gates. [ ] A) 2 n B) 2 *n C) n+1 D) n 24. When the memory enable input is active, and read/write input value is 1 then which indicates operation to be performed [ ] A) read B) write C) both A & B D) none of these 25. In Hamming code method if the data bits are 11 range then the parity bits size is [ ] A) 5 B) 4 C) 3 D) none of these 26. information is stored in memory [ ] A)Binary B) decimal C) octal D) none 27.The process of storing data into the memory is called [ ] A) read B) write C) delete D) none of these 28.TTL is [ ] A) Transistor- Transistor Logic B) Transistor- Transfer Logic C) Transistor- Tamsmitter Logic D) none of these 29.The is a programmable logic device with a fixed OR array and a programmable AND array. [ ] A)PAL B) PLA C) PROM D) none of these 30. stores the binary information permanently. [ ] A) RAM B) ROM C) both A & B D) none of these 31.In Hamming code technique, if the data does not have any error, then C = [ ] A)10001 B)0000 C) 1001 D) The process of retrieving the information from the memory is called operation. [ ] A) Read B) Write C)Both A&B D)None 33.A group of eight bits is called a [ ] A)Bits B) byte C) kilobyte D) none of these 34.The read only memory is a device [ ] A) Programmable logic B) combinational logic C) A & B D) none 35.The is a programmable logic device with a fixed OR array and a programmable AND array. [ ] A)PAL B) PLA C) PROM ) none of these 36. stores the binary information permanently. [ ] A)RAM B) ROM C) both A & B D) none of these Digital Logic Design Page 24

25 37. In Hamming code technique, if the data does not have any error, then C = [ ] A)10001 B)0000 C) 1001 D) The process of retrieving the information from the memory is called operation. [ ] A) Read B) write C) both read & write D) none 39. A group of eight bits is called a [ ] A)Bits B) byte C) kilobyte D) none of these 40. The read only memory is a device [ ] A)Programmable logic B) combinational logic C) A & B D) none Prepared by: Prepared by: P Nirupama, G Prasad Babu, V Balaji Digital Logic Design Page 25

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DEMORGAN'S THEOREMS One of DeMorgan's theorems stated as follows: The complement of a product of variables is equal to the sum of the complements of the variables. DeMorgan's second theorem is stated as

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28 The McGraw-Hill Companies, Inc. All rights reserved. 28 The McGraw-Hill Companies, Inc. All rights reserved. All or Nothing Gate Boolean Expression: A B = Y Truth Table (ee next slide) or AB = Y 28

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### ENGINEERS ACADEMY. 7. Given Boolean theorem. (a) A B A C B C A B A C. (b) AB AC BC AB BC. (c) AB AC BC A B A C B C.

Digital Electronics Boolean Function QUESTION BANK. The Boolean equation Y = C + C + C can be simplified to (a) (c) A (B + C) (b) AC (d) C. The Boolean equation Y = (A + B) (A + B) can be simplified to

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### This tutorial gives a complete understanding on Computer Logical Organization starting from basic computer overview till its advanced architecture.

About the Tutorial Computer Logical Organization refers to the level of abstraction above the digital logic level, but below the operating system level. At this level, the major components are functional

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No part of this publication may be reproduced or distributed in any form or any means, electronic, mechanical, photocopying, or otherwise without the prior permission of the author. GATE SOLVED PAPER Computer

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### ii) Do the following conversions: output is. (a) (101.10) 10 = (?) 2 i) Define X-NOR gate. (b) (10101) 2 = (?) Gray (2) /030832/31034

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