Computer Organization and Technology Processor and System Structures
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1 Computer Organization and Technology Processor and System Structures Assoc. Prof. Dr. Wattanapong Kurdthongmee Division of Computer Engineering, School of Engineering and Resources, Walailak University
2 Introduction Computer was built on death and taxes. If it wasn t the military figuring out how to kill people, it was another part of government figuring out how to count their money.
3 Types of Computer Systems A modern-day computer system can be classified as a supercomputer: Embedded computers: largest class/span the widest range of applications and performance. Smartphone/Tablet a large-scale machine (or a mainframe) a minicomputer, or a microcomputer. Other combination of these four major categories. The distinctions are becoming blurred with: advances in hardware technology. Architectural features found in supercomputers and large scale machines eventually appear in mini- and microcomputer systems.
4 Instruction Set Instruction set: The selection of a set of instructions the application for which the machine is intended. For general-purpose data processing the basic arithmetic and logic operations must be included in the instruction set. To be suitable for both scientific and business-oriented processing the IBM 370 have separate instructions for binary and decimal (BCD) arithmetic. In general, an instruction set can be classified according to the type of operand used by each instruction. The operand is located in: A register of processor or I/O module, In a memory location.
5 Instruction Set Instruction set (cont d): Each low-level instruction or machine code must contain the information required by the CPU for execution. These elements are all required information: Operand code/opcode: operation to be performed in binary code. Source operand reference: may involve one or more source operands (input for the operation). Result operand reference: may produce a result. Next instruction reference: tells the CPU where to fetch the next instruction after the execution of this instruction. Source and result operands can be in one of three areas: Main/Virtual Memory CPU register I/O device
6 Instruction Set Instruction Fetch Operand Fetch Operand Store Multiple Operands Multiple Results Instruction Address Calculation Instruction Operation Decoding Operand Address Calculation Data Operation Operand Address Calculation Instruction Complete, Fetch Next Instruction Return for String or Vector Data Instruction Cycle State Diagram
7 Instruction Set Today s computers are built from 2 key principles: Instructions are represented as numbers. Programs are stored in memory to be read/written, just like numbers. These principles lead to the stored-program concept: A computer that performs accounting to become a computer that helps an author write a book. By loading memory with programs and data and telling the computer to begin executing at a given location. Memory can contain: the source code for an editor program, the corresponding compiled machine code (binary numbers), the text that the compiled program is using, and even the compiler that generated the machine code.
8 Instruction Set The stored-program concept Account Program (machine code) Editor Program (machine code) Processor C-Compiler (machine code) Payroll data Book text Memory
9 Instruction Set 4 Bits 6 Bits 6 Bits Opcode Operand Reference Operand Reference 16 Bits Instruction set: Within the computer, each instruction is represented by a sequence of bits. The instruction is divided into fields, corresponding to the elements of the instruction. Example below shows an instruction format: During execution, an instruction is read into an instruction register (IR) in the CPU. The data from the various field is extracted to perform the required operation
10 Instruction Set Consider the following example of 51XA s ADD instructions ADD Rd,#data d d d d #data8 ADD R10,#12h = ADD Rd,#data d d d d upper 8 bits of #data16 lower 8 bits of #data16 ADD R10,#1234h =
11 Instruction Set Consider the following example of 51XA s ADD instructions ADD [Rd],#data d d d #data8 ADD [R7],#89h = ADD [Rd],#data d d d upper 8 bits of #data16 lower 8 bits of #data16 ADD [R5],#8765h =
12 Instruction Set Consider the following example of 51XA s SUB instructions SUB Rd,#data d d d d #data8 SUB R10,#12h = SUB Rd,#data d d d d upper 8 bits of #data16 lower 8 bits of #data16 SUB R10,#1234h =
13 Instruction Set Consider the following example of 51XA s SUB instructions SUB [Rd],#data8 = Subtract at address of Rd d d d #data8 SUB [R7],#89h = SUB [Rd],#data d d d upper 8 bits of #data16 lower 8 bits of #data16 SUB [R5],#8765h =
14 Instruction Set The following 51XA s assembly codes demonstrate variety of instructions. CALL CLEAR CLEAR: MOV R0,#00H MOV R1,#2000H LOOP: MOVX [R1],R0 ADD R1,#01 ADD R0,#01 CJNE R1,#2010H,LOOP RET OpCode Result Operand Source Operand Next Instruction Reference
15 Instruction Set-Quiz Decode the following instructions Are the following instructions valid with respect to the 51XA s instruction template? Why?
16 Instruction Set Instruction set: The typical classes of instructions are: Memory-to-memory instructions: MOV [R0],[R1+] Memory-to-register instructions: MOV [R0],R1 Register-reference functions: MOV [R0],R1L Memory-reference functions: MOVX [R0],R1L Control functions (branch, halt): CJNE R0,#10H,LOOP Input/Output instructions: MOVX [R0],R1L Macroinstructions The complexity of the control unit increases as the number of instructions in the instruction set increases. A CPU with large instruction sets and powerful instructions (very high level of hardware complexity) is called a complex instruction set computers (CISC).
17 Instruction Set A conclusion from a study of application programs only a small set of instructions in a large instruction set are used frequently a small instruction set with the most often used instructions would serve equally well while limiting the hardware complexity. This has had a great effect on processor architectures because the silicon area on an IC chip saved by using a small instruction set can be used to implement more powerful hardware operators and greater word lengths. Reduced Instruction Set Computers (RISC)
18 Instruction Set Instruction Length: The length of an instruction is a function of the number of addresses in the instruction. a certain number of bits are needed for the opcode register references do not require a large number of bits memory references consume the major portion of an instruction. Memory references and memory-to-memory instructions will be longer than the other types of instructions. Variable-length format: conserve the amount of program memory but increases the complexity of the control unit. The number of memory addresses in an instruction dictates the speed of execution of instructions The longer the instruction, the longer the number of fetch cycle to retrieve the complete instruction.
19 Instruction Set For memory access instructions During execution, each memory address needs to be read/write Slower operation than a register transfer. To reduce the execution time: minimize the number of addresses in the instruction. Based on the number of addresses (operands), instruction organization can be: three-address, two-address, one-address and zero-address. Three-address machine: Examples ADD A, B, C M[C] M[A] + M[B] DIV A, B, C M[C] M[A] / M[B]
20 Instruction Set Two-address machine: Examples ADD A, B DIV A, B One-address machine: Examples ADD A DIV A M[B] M[A] + M[B] M[B] M[A] / M[B] ACC ACC + M[A] ACC ACC / M[A] Where ACC is an accumulator or any other register implied by the instruction. Zero-address machine: Examples ADD MPY The second operand is lost after the operation. SL SL + TL, POP SL SL * TL, POP
21 Instruction Set Assuming n bits for an address representation and m bits for the opcode, the instruction lengths in the above four organizations are: Three-address: m + 3n bits Two-address: m + 2n bits One-address: m + n bits Zero-address: m bits Question: If A, B, C, D and F are memory locations which contain integer values, how many cycles are needed to calculate the function F = A B + C D? Assume further that the result in F can be fitted in that memory location. These results are used in the selection of instruction sets and instruction formats and comparison of processor architecture.
22 Instruction Set Three-address Length FETCH EXECUTE MPY A, B, A MPY C, D, C 3(m + 3n) ADD A, C, F Two-address Length FETCH EXECUTE MPY B,A MPY D, C ADD C, A 5(m + 2n) SUB F, F ADD A, F
23 Instruction Set One-address Length FETCH EXECUTE LOAD A MPY B STORE F LOAD C 7(m + n) MPY D ADD F STORE F
24 Instruction Set Zero-address Length FETCH EXECUTE LOAD A LOAD B MPY LOAD C 3m + 5(m + n) LOAD D MPY ADD STORE F
25 Types of Operations Types of Operations: The number of different opcodes varies widely from machine to machine. Th same general types of operations are found on all machines. A useful and typical categorization is the following: Data transfer Arithmetic Logical Conversion Input/output System control Transfer of control
26 Types of Operations Types of Operations: Data transfer Operation Name Move (transfer) Store Load (fetch) Exchange Clear (reset) Set Push Pop Description Transfer data from source to destination Transfer data from processor to memory Transfer data from memory to processor Swap contents of source and destination Transfer data of 0s to destination Transfer data of 1s to destination Transfer data from source to top of stack Transfer data from top of stack to destination
27 Types of Operations Types of Operations: Arithmetic Operation Name Add Subtract Multiply Divide Absolute Negate Increment Decrement Description Compute sum of two operands Compute difference of two operands Compute product of two operands Compute quotient of two operands Replace operand by its absolute value Change sign of operand Add 1 to operand Subtract 1 from operand
28 Types of Operations Operation Name And Or Not (complement) Exclusive-Or Test Compare Set control variables Shift Types of Operations: Logical Rotate Description Perform logical AND Perform logical OR Perform logical NOT Perform logical XOR Test condition and set appropriate flag(s) Make logical and arithmetic comp. of 2 or more operand and set appropriate flag(s) Class of instructions to set controls for protection purposes, interrupt handling, timer control, etc. Left/right shift operand Wrap around left/right shift
29 Types of Operations Types of Operations: Transfer of Control Operation Name Description Jump Jump to subroutine Return Execute Skip Skip conditional Halt Wait No operation Conditional/unconditional transfer. Load PC with specified address or do nothing (for condition) Place current PC in known location, jump to specified address Replace contents of PC and other register from known location Fetch operand from specified location and execute as instruction; do not modify PC Increment PC to skip next instruction Test specified condition; either skip or do nothing based on condition Stop program execution Stop execution, test cond repeatedly and resume when true No operation is performed but program exec cont.
30 Types of Operations Types of Operations: Input/Output Operation Name Input (read) Output (write) Start I/O Test I/O Description Transfer data from specified I/O port or device to destination Transfer data from specified source to I/O port or device Transfer instruction to I/O processor to initiate I/O operation Transfer status information from I/O system to specified destination
31 Types of Operations Types of Operations:Conversion Operation Name Translate Convert Description Translate values in a section of memory based on a table of correspondences Convert the contents of a word from one form to another
32 CPU actions for various Types of Operations Type of Operation Data Transfer Actions Transfer data from one location to another If memory is involved: Determine memory address, Perform virtual to actual memory address transformation Check cache Initial memory read/write Arithmetic/Logical May involve data transfer, before and/or after Perform function in ALU Set condition codes and flags Conversion Transfer of Control I/O Similar to arithmetic and logical. May involve special logic to perform conversion Update program counter. For subroutine call/return, manage parameter passing and linkage Issue command to I/O module If memory-mapped I/O, determine memory-mapped address
33 Addressing The address field or fields in a typical instruction format are relative small. Question: How to be able to refer to a large range of memory? Answer: A variety of addressing techniques have been employed. Different addressing techniques can handle difference amount of address difference flexibility in referring to memory. The most common addressing techniques are: Immediate Direct Indirect Register Register indirect Displacement Stack
34 Addressing Immediate addressing mode: The simplest addressing mode, operand is actually present in the instruction. Example: MOV A,#23H Benefit: no memory reference is required to fetch in order to get the operand. Drawback: the size of variables to be used is limited. Instruction Operand
35 Addressing Direct addressing mode: Another simple form of addressing The same drawback as the immediate addressing mode. The address field contains the effective (actual) address of the operand. Example: MOV R1,1234H Instruction A Memory Direct addressing mode Operand
36 Addressing Indirect addressing mode: From the limitation of the direct addressing mode: the address field is usually less than the word length (this limits the address range). This mode sorts out the limitation by indirectly refer to address of an operand. Example: MOV R0,[1234H] or MOV Instruction Memory Indirect addressing mode A Operand
37 Addressing Register addressing mode: Similar to direct addressing mode. The difference is: the address field refers to a register rather than a main memory address. The amount of addresses referrable is limited but this is an effecttive way to refer to limited register space. Example: MOV R0,R1 Instruction R Register Register addressing mode Operand
38 Addressing Register indirect addressing mode: Uses register to refer to an operand which is stored in memory space. Similar to indirect addressing mode. Example: MOV A,[R1] Try to differentiate between these two addressing modes. Instruction R Register Memory Register indirect addressing mode Operand
39 Addressing Displacement addressing mode: Combines the capabilities of direct and register indirect addressing. Two address fields within the instruction. One address, A,is used directly, the other address refers to a register whose contents are added to A to produce the actual address. Instruction R A Memory Register + Operand
40 Addressing Stack addressing mode: This mode is similar to register indirect addressing mode. Instruction Implicitly refer to stack Top of Stack Register
41 Summary of Addressing Modes Addressing mode Operand field Register-file contents Memory contents Immediate Data Register-direct Register address Data Register indirect Register address Memory address Data Direct Memory address Data Indirect Memory address Memory address Data
42 CPU Structure and Function Followings are the internal operations of CPUs in general: Fetch instruction: The CPU reads an instruction from memory. Interprete instruction: The instruction is decoded to determine what action is required. Fetch data: The execution of an instruction may require reading data from memory or an I/O module. Process data: The execution of an instruction may require performing some arithmetic or logical operation on data. Write data: The results of an execution may require writing data to memory or an I/O module. In general, there are two major components of the CPU: arithmetic logic unit (ALU): compute/process data control unit (CU): controls the movement of data in/out
43 CPU Structure and Function Normally, data are processed within an element of the CPU called register which is a kind of temporary memory. Registers System Bus ALU CPU Control Unit Control Bus Data Bus Address Bus
44 CPU Structure and Function Consider the components and organizations between all of them within the CPU. Arithmetic and Logic Unit Status flag Shifter Complementer Arithmetic and Boolean Unit Internal CPU Bus Registers Control Paths Control Unit
45 CPU Structure and Function The registers in the CPU serve two functions: User visible registers: These registers are visible to programmers. It is possible to optimize registers usage within assembly programs. Control and status registers: These registers are used by the control unit to control the operation of the CPU. The following diagram illustrates two type of registers, classified by mean of their function, together with their members: User Visible Control and Status General-Purpose Registers Data Registers Address Registers (stack pointer) Condition Codes (flag) Program Counter (PC) Instruction Register (IR) Memory Address Registers (MAR) Memory Buffer Registers (MBR)
46 CPU Structure and Function Apart from the previous set of registers, all CPUs also include a register/set of registers called the program status word (PSW) that keeps current CPU s status information. PSW Sign: Keeps the sign bit of the result from the last arithmetic operation. Zero: Set when the result is 0. Carry: Set when the operation requires a borrow or if the result of the operation causes a carry. Equal: Set if a logical compare result is equality. Overflow: Used to indicate arithmetic overflow. Interrupt enable/disable: Used to enable/disable interrupt. Supervisor: Indicates a current CPU mode of operation: supervisor/user.
47 CPU Structure and Function A number of factor go into the design of the control and status register organization: Operating system support: Some kinds of control information might be specific to the operating system. If the CPU designer has a functional understanding of the OS to be used, then the register organization can be adapted/extended to fully support the OS. Consider Transmeta s CRUSOE. Allocation of control information between registers and memory: The trade-off of cost versus speed must be considered.
48 Instruction Pipelining Many approaches to increase computer s performance: utilize faster circuitry Use cache to hold parts of data/program in fast access memory use many registers to process data instead of using only an accumulator. another approach to achieve greater performance = Instruction pipelining. Pipelining: The operation of CPU generally consists of two stages: fetch and execute instruction. During execution, main memory is not being accessed. This time can be used to fetch the next instruction in advance and store it. The instruction is executed once the execution unit is available.
49 Instruction Pipelining The following diagram shows two-stage instruction pipeline. Instruction Fetch Instruction Execute Result Wait New Address Wait Instruction Fetch Instruction Execute Result Discard
50 Instruction Pipelining Non-pipelined Pipelined non-pipelined dish cleaning Time pipelined dish cleaning Time Fetch-instr. Decode Fetch ops Pipelined Execute Store res. Instruction pipelined instruction execution Time
51 Instruction Pipelining The process will speed up the instruction execution: If the fetch and execution stages are of equal duration. In reality, the execution stage takes longer time to finish its job. This makes the fetch stage to wait for some time. It is OK for linear program. if branch instruction is encountered, the execution stage must supply the next location to fetch instruction. This also takes time. The second drawback can be reduced by guessing. When a conditional branch instruction is passed on from the fetch to the execution stage, the fetch stage fetches the next instruction after the branch instruction. This instruction is discarded if the branch is not taken and a new instruction is fetched.
52 Instruction Pipelining Although, some factors reduce the potential effectiveness of the two-stage pipeline, some speedup occurs. To gain further speedup, the pipeline must have more stages. It is reported that by increasing the number of pipeline stages to 6- stage can reduce the execution time for 9-instructions from 54 to 14 time units. Pipelining still suffers from the conditional branch instruction; i.e. CMP R0,R1 BLT LABEL1 BEQ LABEL2 BGT LABEL3 Many approaches have been used to minimize this effect:
53 Instruction Pipelining A variety of approaches have been taken for dealing with conditional branches: Multiple streams: Use two pipelines to hold address of the next instruction. Prefetch branch target: When a conditional branch is recognized, the target address of the branch is prefetched, in addition to the instruction following the branch. Loop buffer: This is a small/high speed memory which contains the n most recently fetched instructions in sequence. This is used to supply the branch target without needing to directly fetch from memory. Branch prediction: There are many approaches to predict the target address of branch address; i.e. keep all taken branches in branch history table. Delayed branch: By rearranging instructions within a program.
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