CONTENTS CHAPTER 1: NUMBER SYSTEM. Foreword...(vii) Preface... (ix) Acknowledgement... (xi) About the Author...(xxiii)

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1 CONTENTS Foreword...(vii) Preface... (ix) Acknowledgement... (xi) About the Author...(xxiii) CHAPTER 1: NUMBER SYSTEM 1.1 Digital Electronics Introduction Advantages of Digital Systems Comparison of Digital and Analog Systems Data Representation and Coding Data Representation in Digital System Data Representation in Coding Schemes Number Representation Fixed Point Representation Floating Point Representation Digital Number System Binary Number System Octal Number System Decimal Number System Hexadecimal Number System Number System Conversion Conversion from Binary Number System to any other Base Conversion from Decimal Number System to any other Base Conversion from Octal Number System to any other Base Conversion from Hexadecimal Number System any other Base (xiii)

2 (xiv) Contents 1.6 Binary Arithmetic Binary Addition Binary Subtraction Binary Multiplication Binary Division Representation of Signed Number Sign Magnitude Representation s Complement Representation s Complement Representation Complements r s and (r-1) s Diminished Radix Complement (r-1) s Complement Radix Complement r s Complement Subtraction using Complements Difference between 1 s Complement and 2 s Complement Hexadecimal Arithmetic Hexadecimal Addition Hexadecimal Subtraction Codes Binary Coded Decimal (BCD) Excess-3 Code Gray Code Sequential Code Alphanumeric Code Error Detection Code Parity Bit Check Sum Parity Data Codes Error Correcting Code Number of Parity Bits Short Answer Questions Previous Year GATE Questions Practice Questions CHAPTER 2: COMBINATIONAL LOGIC SYSTEM 2.1 Introduction Basic Logic Gates AND Gate... 64

3 Contents (xv) OR Gate NOT Gate Advanced Logic Gates NAND Gate NOR Gate EX-OR or XOR Gate EX-NOR or XNOR Gate Boolean Algebra Boolean Variables Boolean Operators Boolean Laws and Theorems Principle of Duality Standard Forms of Boolean Expression Sum of Products (SOP) Product of Sums (POS) Canonical Form Converting SOP to POS Conversion from POS to SOP Karnaugh Map Plotting of Karnaugh Map Grouping of Cells Writing the Equivalent Expression Short Answer Questions Previous Year GATE Questions Practice Questions CHAPTER 3: COMBINATIONAL LOGIC CIRCUITS 3.1 Introduction Design Strategy of Combinational Logic Circuits Adders Half Adder Full Adder Subtractor Half Subtractor Full Subtractor Digital Comparator One-bit Magnitude Comparator Two-bit Magnitude Comparator

4 (xvi) Contents 3.6 Multiplexer to 1 Multiplexer to 1 Multiplexer to 1 Multiplexer Designing of Logic Gates using 2:1 Multiplexer AND Gate OR Gate NAND Gate NOR Gate EXCLUSIVE-OR(XOR) Gate EXCLUSIVE-NOR(XNOR) Gate NOT Gate Demultiplexer to 2 Demultiplexer to 4 Demultiplexer to 8 Demultiplexer Encoder Octal to Binary Encoder Decimal to BCD Encoder Priority Encoder Decoder to 4 Decoder to 8 Decoder Code Converter Binary to BCD Code Converter BCD to Excess-3 Code Converter BCD to Seven Segment Decoder Parity Circuits bit Odd/Even Parity Generator Short Answer Questions Previous Year GATE Questions Practice Questions CHAPTER 4: SEQUENTIAL LOGIC SYSTEMS AND CIRCUITS 4.1 Introduction Types of Sequential Logic Circuits Types of Triggering

5 Contents (xvii) 4.4 Basic Sequential Circuits SR Latch Flip-flops SR Flip-Flop JK Flip-Flop D Flip-Flop T Flip-Flop Conversion of Flip-Flops Convert SR Flip-Flop into JK Flip-Flop Convert JK Flip-Flop into SR Flip-Flop Shift Registers Classification of Shift Registers Shift Registers Counters Counters Classification of Counters Asynchronous Counters Synchronous Counters Design of Counters using Flip-Flops Short Answer Questions Previous Year GATE Questions Practice Questions CHAPTER 5: DIGITAL LOGIC FAMILIES 5.1 Introduction Level of Integration Classification of Logic Families Nomenclature of Logic Family Resistor Transistor Logic (RTL) Diode Transistor Logic (DTL) Transistor Transistor Logic (TTL) TTL with Open Collector Output Configuration TTL with Totem-Pole Configuration TTL with Tri-State Logic Emitter Coupled Logic (ECL)

6 (xviii) Contents 5.7 Complementary Metal Oxide Semiconductor (CMOS) Logic CMOS Inverter CMOS NAND Logic CMOS NOR Logic CMOS TTL Interfacing TTL Driving CMOS CMOS Driving TTL Characteristics of Digital Logic Families Speed of Operation Power Dissipation Fan-in and Fan-Out Noise Margin Operating Temperature Comparison of all Logic Families Short Answer Questions Previous Year GATE Questions Practice Questions CHAPTER 6: SEMICONDUCTOR MEMORIES 6.1 Introduction Semiconductor Memory Memory Capacity Memory Organisation Speed of Memory Chip Memory Operation Classifications of Semiconductor Memory Random Access Memory (RAM) Read Only Memory (ROM) Sequential Access Memory (SAM) Charged Coupled Device (CCD) Memory Content Addressable Memory (CAM) Memory Expansion Word Length Expansion Word Capacity Expansion Short Answer Questions Previous Year GATE Questions Practice Questions

7 Contents (xix) CHAPTER 7: PROGRAMMABLE LOGIC DEVICES 7.1 Introduction Classification of PLDs Simple Programmable Logic Device (SPLD) Programmable Read Only Memory (PROM) Programmable Logic Array (PLA) Programmable Array Logic (PAL) Complex Programmable Logic Device (CPLD) Architecture of CPLD Field Programmable Gate Array (FPGA) Short Answer Questions Previous Year GATE Questions Practice Questions CHAPTER 8: A/D AND D/A CONVERTERS 8.1 Introduction Need of Conversion Digital to Analog Converters Weighted Resistor D/A Converter R-2R Ladder D/A Converter Specifications of D/A Converters Applications of D/A Converters Examples of D/A Converter ICs Analog to Digital Converter Sample and Hold Circuit Quantization and Encoding Types of A/D Converters Flash Type A/D Converters Counter Type A/D Converters Successive Approximation A/D Converter Dual Slope Type A/D Converters Specifications of A/D Converter

8 (xx) Contents 8.9 Applications of A/D Converters Examples of A/D Converter ICs Short Answer Questions Previous Year GATE Questions Practice Question CHAPTER 9: INTRODUCTION TO VERILOG HDL PROGRAM FOR DIGITAL CIRCUIT 9.1 Introduction Need of HDL Digital System Design using Verilog Modelling Styles in Verilog Verilog HDL for Truth Table Verilog HDL for Combinational Logic Circuits Verilog HDL Program for all Logic Gates using Structural Modelling Verilog HDL Program for Half Adder using Structural Modelling Verilog HDL Program for 4-bit Full Adder using Structural Modelling Verilog HDL Program for 1-bit Half Subtractor using Data Flow Modelling Verilog Code for 1-bit Full Subtractor using Data Flow Modelling Verilog HDL Program for 3:8 Decoder using Dataflow Modelling Verilog Code for 8:3 Priority Encoder using Structural Modelling Verilog HDL Program for 1:4Demultiplexer using Behavioral Modelling Verilog HDL Program for 4:1 Multiplexer using Structural Modelling Verilog HDL Program for Sequential Circuits Verilog Code for 4-bit Binary Up-down Counter using Behavioral Modelling

9 Contents (xxi) Verilog HDL Program for D Latch using Behavioral Modelling Verilog HDL Program for D Flip-flop using Behavioral Modelling Verilog HDL Program for JK Flip-flop using Behavioral Modelling Short Answer Questions Practice Questions Annexure I: Digital Circuit IC Numbers Annexure II: List of Keywords, System Tasks & Compilers Directives used in Verilog HDL Program Index

Principles of Digital Techniques PDT (17320) Assignment No State advantages of digital system over analog system.

Principles of Digital Techniques PDT (17320) Assignment No State advantages of digital system over analog system. Assignment No. 1 1. State advantages of digital system over analog system. 2. Convert following numbers a. (138.56) 10 = (?) 2 = (?) 8 = (?) 16 b. (1110011.011) 2 = (?) 10 = (?) 8 = (?) 16 c. (3004.06)