Principles of Digital Techniques PDT (17320) Assignment No State advantages of digital system over analog system.
|
|
- Ruby Haynes
- 5 years ago
- Views:
Transcription
1 Assignment No State advantages of digital system over analog system. 2. Convert following numbers a. (138.56) 10 = (?) 2 = (?) 8 = (?) 16 b. ( ) 2 = (?) 10 = (?) 8 = (?) 16 c. ( ) 8 = (?) 2 = (?) 10 = (?) 16 d. (3A46) 16 = (?) 2 = (?) 8 = (?) 10 e. (857.75) 10 = (?) 2 = (?) 8 = (?) 16 f. ( ) 2 = (?) 10 = (?) 8 = (?) 16 g. (273.56) 8 = (?) 2 = (?) 10 = (?) 16 h. (6D7) 16 = (?) 2 = (?) 8 = (?) 10 i. (420.6) 10 = (?) 2 = (?) 8 = (?) 16 j. ( ) 2 = (?) 10 = (?) 8 = (?) 16 k. ( ) 8 = (?) 2 = (?) 10 = (?) 16 l. (8C47.AB) 16 = (?) 2 = (?) 8 = (?) 10 m. (876.47) 10 = (?) 2 = (?) 8 = (?) 16 n. (776.44) 10 = (?) 2 = (?) 8 = (?) 16 o. ( ) 2 = (?) 10 = (?) 8 = (?) 16
2 Assignment No Perform the Binary addition of following, a c b d Perform the Binary subtraction of following, a c b d Perform the Binary multiplication of following, a X 101 c X b X 10 d X Perform the Binary division of following, a by 11 c by 101 b by 10.1 d by Perform the Binary subtraction of following using 1 s complement method. a c b d Perform the Binary subtraction of following using 2 s complement method. a c b d Convert following decimal numbers into 8421 BCD code. a. 286 b. 807 c d Convert following decimal numbers into Excess-3 a. 40 b. 88 c. 64 d Perform addition using BCD addition method. a c b d Perform subtraction using BCD subtraction method. a c b d Perform the BCD subtraction of following using 9 s and 10 s complement method. a b c d Convert the following binary numbers into Gray code. a c b d Convert following 8421 BCD numbers into decimals. a c b d Convert the following Gray code numbers into binary numbers. a c b d
3 Assignment No Why NAND gate and NOR gate is called Universal Gate? 2. State and prove De-Morgan s first and second theorem. 3. List any four laws of Boolean algebra and prove it. 4. Prove that, ABC ABC AB AC AB. 5. Simplify following Boolean expression to minimum literals and draw logic diagram of reduced expression, Y A BC BC A BC ABC. 6. Draw logic diagram, truth table and circuit diagram for, a. Two input OR Gate b. Two input AND Gate c. Not Gate 7. Realize the following Boolean expressions using basic gates. a. Y AB BC AB. b. Y AB AC. 8. Solve the following expression, Y ABC(ABC ABC ABC). 9. Show that, (A A)(B A) B A B. 10. Simplify the following Boolean expression, Y A B A B AB A B. 11. Simplify the following Boolean expression, Y A(A C)(AB C). 12. Draw pin configuration of IC 7400, IC 7402, IC 7404, IC 7408, IC 7432, IC 7486 and IC State advantages of ECL Logic family. 14. List the advantages of CMOS logic family. 15. Define: a. Fan In b. Fan Out c. Propagation Delay d. Power Dissipation 16. Compare TTL and CMOS Logic family. 17. What is difference between totem pole output and open collector output in TTL logic family? 18. Draw and explain: a. Inverter using CMOS Logic family. b. NAND gate using open collector output. c. Two input OR gate using ECL Logic family 19. Differentiate between TTL and ECL logic family. 20. List any four characteristics of ECL logic family. 21. Explain concept of current sinking. 22. Explain Positive and Negative logic.
4 Assignment No Convert the following expressions into their standard forms; a. Y AB AC BC b. Y ( A B)( A C)( B C) c. Y AB AC BC d. Y AB AC BC 2. Convert following expressions into POS; a. f ( A, B, C, D) m(0,1,2,3,6,7,13,15) b. f ( A, B, C, D) m(0,1,2,3,4,7,10,15) 3. Minimize the following expressions using K-Map. a. f 1 ABC ABC ABC ABC b. f 2 ABC ABC ABC ABC c. f 2 ABCD ABCD ABCD ABCD ABCD ABCD d. f ( A, B, C) m(1,3,5,7) e. f ( X, Y, Z) m(0,2,4,6) f. f ( A, B, C, D) m(4,5,6,12,13,14) g. f ( P, Q, R, S) m(0,1,3,4,5,6,7,13,15) h. f ( A, B, C, D) m(0,2,4,6,7,8,10,12,13,15) i. f 1 m(1, 2,3,6,8,12,14,15) j. f ( A, B, C, D) m(0,1,2,3,6,7,13,15) k. f ( A, B, C, D) m(8,10,11,13,15) d(9,12,14) l. Y m(1,3,7,11,15) d(0, 2,5,8,14) m. f m(1,5,6,12,13,14) d(2,4) n. f ( A, B, C, D) m(1,4,7,10,13) d(5,14,15) o. f ( A, B, C, D) m(4,5,7,12,14,15) d(3,8,10) p. f ( W, X, Y, Z) m(1,3,7,11,15) d(0,2,5) q. f 1 M(0, 4,9,10,11,14,15) r. f ( A, B, C, D) M(0,1,2,3,4,10,11,15) s. f ( W, X, Y, Z) M(2,3,4,6,9,11,12,13) t. f ( A, B, C, D) M(6,7,8,9). d(10,11,12,13,14,15) 4. Design following circuits using K-map techniques a. Half adder b. Full adder c. Half Subtractor d. Full Subtractor e. Gray code to Binary code converter f. Binary to Gray code Converter 5. Draw 4 bit adder/substractor using IC 7483 and explain operation. 6. Draw full adder using two half adders and full Subtractor using two half Subtractors 7. Design BCD adder circuit using IC Explain rules for K-map reduction techniques.
5 Assignment No Give any two applications of multiplexers. 2. Describe how de-multiplexer can be used as decoder. 3. Draw 16:1 multiplexer using 8:1 multiplexer. 4. Draw general block diagram of multiplexer and explain. 5. Draw the circuit diagram of 1:4 de-multiplexer using logic gates. 6. Draw circuit diagram of 1:8 de-multiplexer with truth table. 7. Draw the circuit diagram of 1:2 de-multiplexer using logic gates. 8. Draw 32:1 multiplexer using 16:1 multiplexer and one 2:1 multiplexer. 9. Draw 64:1 multiplexer tree using 16:1 multiplexer. 10. Design 32:1 multiplexer using 8:1 multiplexer. 11. Draw 1:16 demux using 1:4 demux. 12. Draw 1:32 demux using 1:8 demux. 13. Implement following function using multiplexer a. Y m(2,3,5,6) b. Y m(1, 2,5,6,8,12) using 16:1 mux c. f ( A, B, C, D) m(0,2,5,7,11,15) d. f ( A, B, C, D) M(0,1,5,7,10,15) e. f ( A, B, C) m(0,2,5,7) f. f ( A, B, C) M(1,3,4,7) 14. Implement following functions using de-m a. Y1 f ( A, B, C, D) m(0,3,8,9,12) b. Y 2 f ( A, B, C, D) M(0,3,8,9,12) c. f ( A, B, C, D) m(0,1,2,3,5,7,8,9,11,14) d. f ( A, B, C) m(0,2,5,7) e. f ( A, B, C) M(1,3,4,7) 15. Explain the role of multiplexers in digital systems. 16. Draw pin configuration and function table of IC 74181, IC Draw internal diagram of IC and IC with its function table. 18. Explain Demux as decoder. 19. Draw block diagram of 8:3 priority encoder. Also write truth table. 20. Explain in detail Decimal to BCD encoder.
6 Karmaveer Bhaurao Patil Polytechnic, Panmalewadi, Varye, Satara Assignment No Write the difference between combinational and sequential logic circuit. 2. Design 4 bit asynchronous up-counter also write the truth table and draw the waveform. 3. Write the use of preset and clear terminal in a flip-flop. 4. What is the Race-around condition? How it will be eliminated in J-K flip-flop? 5. Draw the diagram of 3-bit twisted ring counter using J-K F/F. Also write its truth table. 6. With neat diagram write the working of serial in serial out shift register. 7. Draw S-R latch using NAND gates only, also write about the received output for each condition using truth table of S-R flip-flop. 8. Define modulus of counter. How many flip flops are required for mod 5 counter. 9. List the types of shift registers. 10. Draw clocked SR flip flop with preset and clear using gates. What is the drawback of SR flip flop. 11. Draw 3 bit asynchronous up counter with truth table and timing diagram. 12. Draw D and T flip flop using JK flip flop. 13. Draw 3 bit twisted ring counter using D flip flop. Give its timing diagram. 14. Write down excitation table for SR flip flop and T flip flop. 15. Design mode 6 counter using IC Draw 3 bit synchronous counter with truth table and timing diagram. 17. State the different triggering methods in digital circuit. 18. Draw the circuit diagram of 3 bit synchronous up counter with its truth table and explain its working. 19. How can IC 7490 be used as a decade counter with neat block diagram. 20. Design MOD 10 asynchronous up counter, with its truth table and timing diagram.
7 Karmaveer Bhaurao Patil Polytechnic, Panmalewadi, Varye, Satara Assignment No What is necessity of A/D and D/A converters? 2. What are the types of Data converters? 3. What are the methods used for D/A conversion? 4. Explain weighted resistor type D/A converter. 5. Explain R-2R ladder network method of D/A conversion with neat circuit diagram and derive the expression for output voltage. 6. Compare R-2R ladder and weighted type D/A converter. 7. State and define specifications of D/A conversion. 8. Draw block diagram of single slope A/D converter and explain operation. 9. Draw block diagram of dual slope A/D converter and explain operation. 10. Draw block diagram of successive approximation type A/D converter and explain operation. 11. What are advantages and disadvantages of successive approximation type DAC? 12. What are features and applications of PCF 8951? 13. Draw block diagram of IC 8951 and explain. 14. Compare successive approximation and dual slope ADC. 15. Explain characteristics of ADC.
8 Karmaveer Bhaurao Patil Polytechnic, Panmalewadi, Varye, Satara Assignment No Classify memories on the basis of principle of operation. 2. Differentiate between: 3. Explain flash memory. 4. Describe memory IC a. EPROM and EEPROM b. SRAM and DRAM c. Volatile and Non-volatile d. RAM and ROM 5. Draw functional block diagram of IC List any two features. 6. State different types ROM and explain any one type of ROM. 7. Draw diagram to illustrate the internal organization of memory. Explain significance of data, address, read and write signals. 8. Explain the role of memory in microprocessor system. Write different characteristics of memory. 9. What is static and dynamic RAM? 10. Draw static and dynamic RAM cell.
Hours / 100 Marks Seat No.
17320 21718 3 Hours / 100 Seat No. Instructions (1) All Questions are Compulsory. (2) Answer each next main Question on a new page. (3) Figures to the right indicate full marks. (4) Assume suitable data,
More informationScheme G. Sample Test Paper-I
Sample Test Paper-I Marks : 25 Times:1 Hour 1. All questions are compulsory. 2. Illustrate your answers with neat sketches wherever necessary. 3. Figures to the right indicate full marks. 4. Assume suitable
More informationHours / 100 Marks Seat No.
17333 13141 3 Hours / 100 Seat No. Instructions (1) All Questions are Compulsory. (2) Answer each next main Question on a new page. (3) Illustrate your answers with neat sketches wherever necessary. (4)
More informationHANSABA COLLEGE OF ENGINEERING & TECHNOLOGY (098) SUBJECT: DIGITAL ELECTRONICS ( ) Assignment
Assignment 1. What is multiplexer? With logic circuit and function table explain the working of 4 to 1 line multiplexer. 2. Implement following Boolean function using 8: 1 multiplexer. F(A,B,C,D) = (2,3,5,7,8,9,12,13,14,15)
More informationVALLIAMMAI ENGINEERING COLLEGE. SRM Nagar, Kattankulathur DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING EC6302 DIGITAL ELECTRONICS
VALLIAMMAI ENGINEERING COLLEGE SRM Nagar, Kattankulathur-603 203 DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING EC6302 DIGITAL ELECTRONICS YEAR / SEMESTER: II / III ACADEMIC YEAR: 2015-2016 (ODD
More informationEND-TERM EXAMINATION
(Please Write your Exam Roll No. immediately) END-TERM EXAMINATION DECEMBER 2006 Exam. Roll No... Exam Series code: 100919DEC06200963 Paper Code: MCA-103 Subject: Digital Electronics Time: 3 Hours Maximum
More informationR10. II B. Tech I Semester, Supplementary Examinations, May
SET - 1 1. a) Convert the following decimal numbers into an equivalent binary numbers. i) 53.625 ii) 4097.188 iii) 167 iv) 0.4475 b) Add the following numbers using 2 s complement method. i) -48 and +31
More informationInjntu.com Injntu.com Injntu.com R16
1. a) What are the three methods of obtaining the 2 s complement of a given binary (3M) number? b) What do you mean by K-map? Name it advantages and disadvantages. (3M) c) Distinguish between a half-adder
More informationCONTENTS CHAPTER 1: NUMBER SYSTEM. Foreword...(vii) Preface... (ix) Acknowledgement... (xi) About the Author...(xxiii)
CONTENTS Foreword...(vii) Preface... (ix) Acknowledgement... (xi) About the Author...(xxiii) CHAPTER 1: NUMBER SYSTEM 1.1 Digital Electronics... 1 1.1.1 Introduction... 1 1.1.2 Advantages of Digital Systems...
More informationSHRI ANGALAMMAN COLLEGE OF ENGINEERING. (An ISO 9001:2008 Certified Institution) SIRUGANOOR, TIRUCHIRAPPALLI
SHRI ANGALAMMAN COLLEGE OF ENGINEERING AND TECHNOLOGY (An ISO 9001:2008 Certified Institution) SIRUGANOOR, TIRUCHIRAPPALLI 621 105 DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING EC1201 DIGITAL
More informationB.Tech II Year I Semester (R13) Regular Examinations December 2014 DIGITAL LOGIC DESIGN
B.Tech II Year I Semester () Regular Examinations December 2014 (Common to IT and CSE) (a) If 1010 2 + 10 2 = X 10, then X is ----- Write the first 9 decimal digits in base 3. (c) What is meant by don
More informationCOLLEGE OF ENGINEERING DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING QUESTION BANK SUBJECT CODE & NAME: EC 1312 DIGITAL LOGIC CIRCUITS UNIT I
KINGS COLLEGE OF ENGINEERING DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING QUESTION BANK SUBJECT CODE & NAME: EC 1312 DIGITAL LOGIC CIRCUITS YEAR / SEM: III / V UNIT I NUMBER SYSTEM & BOOLEAN ALGEBRA
More informationCode No: R Set No. 1
Code No: R059210504 Set No. 1 II B.Tech I Semester Regular Examinations, November 2006 DIGITAL LOGIC DESIGN ( Common to Computer Science & Engineering, Information Technology and Computer Science & Systems
More informationR a) Simplify the logic functions from binary to seven segment display code converter (8M) b) Simplify the following using Tabular method
SET - 1 1. a) Convert the decimal number 250.5 to base 3, base 4 b) Write and prove de-morgan laws c) Implement two input EX-OR gate from 2 to 1 multiplexer (3M) d) Write the demerits of PROM (3M) e) What
More informationUNIT I BOOLEAN ALGEBRA AND COMBINATIONAL CIRCUITS PART-A (2 MARKS)
SUBJECT NAME: DIGITAL LOGIC CIRCUITS YEAR / SEM : II / III DEPARTMENT : EEE UNIT I BOOLEAN ALGEBRA AND COMBINATIONAL CIRCUITS 1. What is variable mapping? 2. Name the two canonical forms for Boolean algebra.
More information(ii) Simplify and implement the following SOP function using NOR gates:
DHANALAKSHMI COLLEGE OF ENGINEERING DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING EE6301 DIGITAL LOGIC CIRCUITS UNIT I NUMBER SYSTEMS AND DIGITAL LOGIC FAMILIES PART A 1. How can an OR gate be
More informationBHARATHIDASAN ENGINEERING COLLEGE Degree / Branch : B.E./ECE Year / Sem : II/ III Sub.Code / Name : EC6302/DIGITAL ELECTRONICS
BHARATHIDASAN ENGINEERING COLLEGE Degree / Branch : B.E./ECE Year / Sem : II/ III Sub.Code / Name : EC6302/DIGITAL ELECTRONICS FREQUENTLY ASKED QUESTIONS UNIT I MINIMIZATION TECHNIQUES AND LOGIC GATES
More informationCode No: R Set No. 1
Code No: R059210504 Set No. 1 II B.Tech I Semester Supplementary Examinations, February 2007 DIGITAL LOGIC DESIGN ( Common to Computer Science & Engineering, Information Technology and Computer Science
More informationKINGS COLLEGE OF ENGINEERING DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING QUESTION BANK NAME OF THE SUBJECT: EE 2255 DIGITAL LOGIC CIRCUITS
KINGS COLLEGE OF ENGINEERING DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING QUESTION BANK NAME OF THE SUBJECT: EE 2255 DIGITAL LOGIC CIRCUITS YEAR / SEM: II / IV UNIT I BOOLEAN ALGEBRA AND COMBINATIONAL
More informationDE Solution Set QP Code : 00904
DE Solution Set QP Code : 00904 1. Attempt any three of the following: 15 a. Define digital signal. (1M) With respect to digital signal explain the terms digits and bits.(2m) Also discuss active high and
More informationScheme I. Sample Question Paper
Sample Question Paper Marks : 70 Time:3 Hrs. Q.1) Attempt any FIVE of the following :- 10 Marks (5X2) (a) Draw the symbol and write the truth table of Universal Gates. (b) In a 3 variable K Map if there
More informationNADAR SARASWATHI COLLEGE OF ENGINEERING AND TECHNOLOGY Vadapudupatti, Theni
NADAR SARASWATHI COLLEGE OF ENGINEERING AND TECHNOLOGY Vadapudupatti, Theni-625531 Question Bank for the Units I to V SEMESTER BRANCH SUB CODE 3rd Semester B.E. / B.Tech. Electrical and Electronics Engineering
More informationDIRECTORATE OF TECHNICAL EDUCATION DIPLOMA IN ELECTRICAL AND ELECTRONICS ENGINEERING II YEAR M SCHEME IV SEMESTER.
DIRECTORATE OF TECHNICAL EDUCATION DIPLOMA IN ELECTRICAL AND ELECTRONICS ENGINEERING II YEAR M SCHEME IV SEMESTER 2015 2016 onwards DIGITAL ELECTRONICS CURRICULUM DEVELOPMENT CENTRE Curriculum Development
More information3. The high voltage level of a digital signal in positive logic is : a) 1 b) 0 c) either 1 or 0
1. The number of level in a digital signal is: a) one b) two c) four d) ten 2. A pure sine wave is : a) a digital signal b) analog signal c) can be digital or analog signal d) neither digital nor analog
More informationUPY14602-DIGITAL ELECTRONICS AND MICROPROCESSORS Lesson Plan
UPY14602-DIGITAL ELECTRONICS AND MICROPROCESSORS Lesson Plan UNIT I - NUMBER SYSTEMS AND LOGIC GATES Introduction to decimal- Binary- Octal- Hexadecimal number systems-inter conversions-bcd code- Excess
More informationDHANALAKSHMI SRINIVASAN COLLEGE OF ENGINEERING AND TECHNOLOGY
DHANALAKSHMI SRINIVASAN COLLEGE OF ENGINEERING AND TECHNOLOGY Dept/Sem: II CSE/03 DEPARTMENT OF ECE CS8351 DIGITAL PRINCIPLES AND SYSTEM DESIGN UNIT I BOOLEAN ALGEBRA AND LOGIC GATES PART A 1. How many
More informationSIDDHARTH GROUP OF INSTITUTIONS :: PUTTUR Siddharth Nagar, Narayanavanam Road QUESTION BANK (DESCRIPTIVE)
SIDDHARTH GROUP OF INSTITUTIONS :: PUTTUR Siddharth Nagar, Narayanavanam Road 517583 QUESTION BANK (DESCRIPTIVE) Subject with Code : STLD(16EC402) Year & Sem: II-B.Tech & I-Sem Course & Branch: B.Tech
More informationCode No: R Set No. 1
Code No: R059210504 Set No. 1 II B.Tech I Semester Regular Examinations, November 2007 DIGITAL LOGIC DESIGN ( Common to Computer Science & Engineering, Information Technology and Computer Science & Systems
More informationR07. Code No: V0423. II B. Tech II Semester, Supplementary Examinations, April
SET - 1 II B. Tech II Semester, Supplementary Examinations, April - 2012 SWITCHING THEORY AND LOGIC DESIGN (Electronics and Communications Engineering) Time: 3 hours Max Marks: 80 Answer any FIVE Questions
More informationCode No: 07A3EC03 Set No. 1
Code No: 07A3EC03 Set No. 1 II B.Tech I Semester Regular Examinations, November 2008 SWITCHING THEORY AND LOGIC DESIGN ( Common to Electrical & Electronic Engineering, Electronics & Instrumentation Engineering,
More informationVALLIAMMAI ENGINEERING COLLEGE
VALLIAMMAI ENGINEERING COLLEGE SRM Nagar, Kattankulathur 603 203 DEPARTMENT OF INFORMATION TECHNOLOGY & COMPUTER SCIENCE AND ENGINEERING QUESTION BANK II SEMESTER CS6201- DIGITAL PRINCIPLE AND SYSTEM DESIGN
More informationCourse Batch Semester Subject Code Subject Name. B.E-Marine Engineering B.E- ME-16 III UBEE307 Integrated Circuits
Course Batch Semester Subject Code Subject Name B.E-Marine Engineering B.E- ME-16 III UBEE307 Integrated Circuits Part-A 1 Define De-Morgan's theorem. 2 Convert the following hexadecimal number to decimal
More informationSUBJECT CODE: IT T35 DIGITAL SYSTEM DESIGN YEAR / SEM : 2 / 3
UNIT - I PART A (2 Marks) 1. Using Demorgan s theorem convert the following Boolean expression to an equivalent expression that has only OR and complement operations. Show the function can be implemented
More informationVALLIAMMAI ENGINEERING COLLEGE
VALLIAMMAI ENGINEERING COLLEGE SRM Nagar, Kattankulathur 603 203 DEPARTMENT OF INFORMATION TECHNOLOGY QUESTION BANK Academic Year 2018 19 III SEMESTER CS8351-DIGITAL PRINCIPLES AND SYSTEM DESIGN Regulation
More informationINSTITUTE OF AERONAUTICAL ENGINEERING (Autonomous) Dundigal, Hyderabad
INSTITUTE OF AERONAUTICAL ENGINEERING (Autonomous) Dundigal, Hyderabad - 500 043 COMPUTER SCIENCE AND ENGINEERING TUTORIAL QUESTION BANK Name : DIGITAL LOGIC DESISN Code : AEC020 Class : B Tech III Semester
More informationwww.vidyarthiplus.com Question Paper Code : 31298 B.E./B.Tech. DEGREE EXAMINATION, NOVEMBER/DECEMBER 2013. Third Semester Computer Science and Engineering CS 2202/CS 34/EC 1206 A/10144 CS 303/080230012--DIGITAL
More informationII/IV B.Tech (Regular/Supplementary) DEGREE EXAMINATION. Answer ONE question from each unit.
Hall Ticket Number: 14CS IT303 November, 2017 Third Semester Time: Three Hours Answer Question No.1 compulsorily. II/IV B.Tech (Regular/Supplementary) DEGREE EXAMINATION Common for CSE & IT Digital Logic
More informationR07
www..com www..com SET - 1 II B. Tech I Semester Supplementary Examinations May 2013 SWITCHING THEORY AND LOGIC DESIGN (Com. to EEE, EIE, BME, ECC) Time: 3 hours Max. Marks: 80 Answer any FIVE Questions
More informationINSTITUTE OF AERONAUTICAL ENGINEERING (Autonomous) Dundigal, Hyderabad
INSTITUTE OF AERONAUTICAL ENGINEERING (Autonomous) Dundigal, Hyderabad - 500043 Course Name : DIGITAL LOGIC DESISN Course Code : AEC020 Class : B Tech III Semester Branch : CSE Academic Year : 2018 2019
More informationii) Do the following conversions: output is. (a) (101.10) 10 = (?) 2 i) Define X-NOR gate. (b) (10101) 2 = (?) Gray (2) /030832/31034
No. of Printed Pages : 4 Roll No.... rd 3 Sem. / ECE Subject : Digital Electronics - I SECTION-A Note: Very Short Answer type questions. Attempt any 15 parts. (15x2=30) Q.1 a) Define analog signal. b)
More informationSIR C.R.REDDY COLLEGE OF ENGINEERING, ELURU DEPARTMENT OF INFORMATION TECHNOLOGY LESSON PLAN
SIR C.R.REDDY COLLEGE OF ENGINEERING, ELURU DEPARTMENT OF INFORMATION TECHNOLOGY LESSON PLAN SUBJECT: CSE 2.1.6 DIGITAL LOGIC DESIGN CLASS: 2/4 B.Tech., I SEMESTER, A.Y.2017-18 INSTRUCTOR: Sri A.M.K.KANNA
More informationPART B. 3. Minimize the following function using K-map and also verify through tabulation method. F (A, B, C, D) = +d (0, 3, 6, 10).
II B. Tech II Semester Regular Examinations, May/June 2015 SWITCHING THEORY AND LOGIC DESIGN (Com. to EEE, ECE, ECC, EIE.) Time: 3 hours Max. Marks: 70 Note: 1. Question Paper consists of two parts (Part-A
More informationMGU-BCA-205- Second Sem- Core VI- Fundamentals of Digital Systems- MCQ s. 2. Why the decimal number system is also called as positional number system?
MGU-BCA-205- Second Sem- Core VI- Fundamentals of Digital Systems- MCQ s Unit-1 Number Systems 1. What does a decimal number represents? A. Quality B. Quantity C. Position D. None of the above 2. Why the
More informationGovernment of Karnataka Department of Technical Education Board of Technical Examinations, Bengaluru
Government of Karnataka Department of Technical Education Board of Technical Examinations, Bengaluru Course Title: DIGITAL ELECTRONICS Course Code : 15EE34T Semester : III Course Group : Core Teaching
More informationDIGITAL ELECTRONICS. Vayu Education of India
DIGITAL ELECTRONICS ARUN RANA Assistant Professor Department of Electronics & Communication Engineering Doon Valley Institute of Engineering & Technology Karnal, Haryana (An ISO 9001:2008 ) Vayu Education
More informationCS6201-DIGITAL PRINCIPLE AND SYSTEM DESIGN I YEAR/II SEM PART-B UNIT-I BOOLEAN ALGEBRA AND LOGIC GATES.
CS6201-DIGITAL PRINCIPLE AND SYSTEM DESIGN I YEAR/II SEM PART-B UNIT-I BOOLEAN ALGEBRA AND LOGIC GATES. 1) Simplify the boolean function using tabulation method. F = (0, 1, 2, 8, 10, 11, 14, 15) List all
More informationCS/IT DIGITAL LOGIC DESIGN
CS/IT 214 (CR) Total No. of Questions :09] [Total No. of Pages : 02 II/IV B.Tech. DEGREE EXAMINATIONS, DECEMBER- 2016 First Semester CS/IT DIGITAL LOGIC DESIGN Time: Three Hours 1. a) Flip-Flop Answer
More informationDigital Logic Design Exercises. Assignment 1
Assignment 1 For Exercises 1-5, match the following numbers with their definition A Number Natural number C Integer number D Negative number E Rational number 1 A unit of an abstract mathematical system
More informationR.M.D. ENGINEERING COLLEGE R.S.M. Nagar, Kavaraipettai
L T P C R.M.D. ENGINEERING COLLEGE R.S.M. Nagar, Kavaraipettai- 601206 DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING EC8392 UNIT - I 3 0 0 3 OBJECTIVES: To present the Digital fundamentals, Boolean
More informationAPPENDIX A SHORT QUESTIONS AND ANSWERS
APPENDIX A SHORT QUESTIONS AND ANSWERS Unit I Boolean Algebra and Logic Gates Part - A 1. Define binary logic? Binary logic consists of binary variables and logical operations. The variables are designated
More information10EC33: DIGITAL ELECTRONICS QUESTION BANK
10EC33: DIGITAL ELECTRONICS Faculty: Dr.Bajarangbali E Examination QuestionS QUESTION BANK 1. Discuss canonical & standard forms of Boolean functions with an example. 2. Convert the following Boolean function
More informationLogic design Ibn Al Haitham collage /Computer science Eng. Sameer
DEMORGAN'S THEOREMS One of DeMorgan's theorems stated as follows: The complement of a product of variables is equal to the sum of the complements of the variables. DeMorgan's second theorem is stated as
More informationMULTIMEDIA COLLEGE JALAN GURNEY KIRI KUALA LUMPUR
STUDENT IDENTIFICATION NO MULTIMEDIA COLLEGE JALAN GURNEY KIRI 54100 KUALA LUMPUR SECOND SEMESTER FINAL EXAMINATION, 2013/2014 SESSION ITC2223 COMPUTER ORGANIZATION & ARCHITECTURE DSEW-E-F 1/13 18 FEBRUARY
More informationPhiladelphia University Student Name: Student Number:
Philadelphia University Student Name: Student Number: Faculty of Engineering Serial Number: Final Exam, First Semester: 2018/2019 Dept. of Computer Engineering Course Title: Logic Circuits Date: 03/01/2019
More informationComputer Logical Organization Tutorial
Computer Logical Organization Tutorial COMPUTER LOGICAL ORGANIZATION TUTORIAL Simply Easy Learning by tutorialspoint.com tutorialspoint.com i ABOUT THE TUTORIAL Computer Logical Organization Tutorial Computer
More informationDigital logic fundamentals. Question Bank. Unit I
Digital logic fundamentals Question Bank Subject Name : Digital Logic Fundamentals Subject code: CA102T Staff Name: R.Roseline Unit I 1. What is Number system? 2. Define binary logic. 3. Show how negative
More informationQUESTION BANK FOR TEST
CSCI 2121 Computer Organization and Assembly Language PRACTICE QUESTION BANK FOR TEST 1 Note: This represents a sample set. Please study all the topics from the lecture notes. Question 1. Multiple Choice
More information1. Mark the correct statement(s)
1. Mark the correct statement(s) 1.1 A theorem in Boolean algebra: a) Can easily be proved by e.g. logic induction b) Is a logical statement that is assumed to be true, c) Can be contradicted by another
More informationDigital Design Using Digilent FPGA Boards -- Verilog / Active-HDL Edition
Digital Design Using Digilent FPGA Boards -- Verilog / Active-HDL Edition Table of Contents 1. Introduction to Digital Logic 1 1.1 Background 1 1.2 Digital Logic 5 1.3 Verilog 8 2. Basic Logic Gates 9
More informationThis tutorial gives a complete understanding on Computer Logical Organization starting from basic computer overview till its advanced architecture.
About the Tutorial Computer Logical Organization refers to the level of abstraction above the digital logic level, but below the operating system level. At this level, the major components are functional
More information1. Draw general diagram of computer showing different logical components (3)
Tutorial 1 1. Draw general diagram of computer showing different logical components (3) 2. List at least three input devices (1.5) 3. List any three output devices (1.5) 4. Fill the blank cells of the
More informationSECTION-A
M.Sc(CS) ( First Semester) Examination,2013 Digital Electronics Paper: Fifth ------------------------------------------------------------------------------------- SECTION-A I) An electronics circuit/ device
More informationKING FAHD UNIVERSITY OF PETROLEUM & MINERALS COMPUTER ENGINEERING DEPARTMENT
KING FAHD UNIVERSITY OF PETROLEUM & MINERALS COMPUTER ENGINEERING DEPARTMENT COE 202: Digital Logic Design Term 162 (Spring 2017) Instructor: Dr. Abdulaziz Barnawi Class time: U.T.R.: 11:00-11:50AM Class
More informationDIGITAL ELECTRONICS. P41l 3 HOURS
UNIVERSITY OF SWAZILAND FACUL TY OF SCIENCE AND ENGINEERING DEPARTMENT OF PHYSICS MAIN EXAMINATION 2015/16 TITLE OF PAPER: COURSE NUMBER: TIME ALLOWED: INSTRUCTIONS: DIGITAL ELECTRONICS P41l 3 HOURS ANSWER
More informationCOPYRIGHTED MATERIAL INDEX
INDEX Absorption law, 31, 38 Acyclic graph, 35 tree, 36 Addition operators, in VHDL (VHSIC hardware description language), 192 Algebraic division, 105 AND gate, 48 49 Antisymmetric, 34 Applicable input
More informationD I G I T A L C I R C U I T S E E
D I G I T A L C I R C U I T S E E Digital Circuits Basic Scope and Introduction This book covers theory solved examples and previous year gate question for following topics: Number system, Boolean algebra,
More informationSwitching Theory & Logic Design/Digital Logic Design Question Bank
Switching Theory & Logic Design/Digital Logic Design Question Bank UNIT I NUMBER SYSTEMS AND CODES 1. A 12-bit Hamming code word containing 8-bits of data and 4 parity bits is read from memory. What was
More informationEECS150 Homework 2 Solutions Fall ) CLD2 problem 2.2. Page 1 of 15
1.) CLD2 problem 2.2 We are allowed to use AND gates, OR gates, and inverters. Note that all of the Boolean expression are already conveniently expressed in terms of AND's, OR's, and inversions. Thus,
More informationSEMESTER SYSTEM, A. PROPOSED SCHEME FOR B.Sc. (ELECTRONICS MAINTENANCE)
SEMESTER SYSTEM, 2010-2013 A PROPOSED SCHEME FOR B.Sc. (ELECTRONICS MAINTENANCE) CLASS/ SEMESTER Sem-III Sem-IV B. Sc (Elex. Maint) EL-2101 Op-Amp & its Applications EL-2102 Digital Electronics II EL-2103
More informationDIPLOMA COURSE IN ELECTRONICS AND COMMUNICATION ENGINEERING
Department of Technical Education DIPLOMA COURSE IN ELECTRONICS AND COMMUNICATION ENGINEERING Third Semester Subject: Digital Electronics & Introduction to Microprocessors Contact Hrs/Week:4 Hrs Contact
More informationELCT 501: Digital System Design
ELCT 501: Digital System Lecture 4: CAD tools (Continued) Dr. Mohamed Abd El Ghany, Basic VHDL Concept Via an Example Problem: write VHDL code for 1-bit adder 4-bit adder 2 1-bit adder Inputs: A (1 bit)
More informationNOTIFICATION (Advt No. 1/2018) Syllabus (Paper III)
NOTIFICATION (Advt No. 1/2018) Syllabus (Paper III) Post Code - 302 Area: Instrumentation COMPUTER PROGRAMMING AND APPLICATION 1. OVERVIEW OF PROGRAMMING: Steps in program development, problem identification,
More informationWritten exam for IE1204/5 Digital Design Thursday 29/
Written exam for IE1204/5 Digital Design Thursday 29/10 2015 9.00-13.00 General Information Examiner: Ingo Sander. Teacher: William Sandqvist phone 08-7904487 Exam text does not have to be returned when
More informationChapter 4. Combinational Logic
Chapter 4. Combinational Logic Tong In Oh 1 4.1 Introduction Combinational logic: Logic gates Output determined from only the present combination of inputs Specified by a set of Boolean functions Sequential
More informationOld Question Papers of PGDCA 1 st Semester H.K. Hi-Tech (College of IT & Management) H.K. Hi-Tech College of IT & Management
() Q.1 (a) What is a computer system? What are the various components of a CPU? Also explain its working. (b) What are the things that computers can do? Also explain the various characteristics of computers?
More informationUnit 6 1.Random Access Memory (RAM) Chapter 3 Combinational Logic Design 2.Programmable Logic
EE 200: Digital Logic Circuit Design Dr Radwan E Abdel-Aal, COE Unit 6.Random Access Memory (RAM) Chapter 3 Combinational Logic Design 2. Logic Logic and Computer Design Fundamentals Part Implementation
More informationCOMBINATIONAL LOGIC CIRCUITS
COMBINATIONAL LOGIC CIRCUITS 4.1 INTRODUCTION The digital system consists of two types of circuits, namely: (i) Combinational circuits and (ii) Sequential circuits A combinational circuit consists of logic
More informationLesson Plan (Odd Semester) Name of the Faculty: Rakesh Gupta
Lesson Plan (Odd Semester) Name of the Faculty: Rakesh Gupta Discipline: Department: Semester: Subject: Data Communication Lesson Plan Duration: 15 weeks ( from July, 2018 to Dec., 2018) **Work load (Lecture
More informationLecture (05) Boolean Algebra and Logic Gates
Lecture (05) Boolean Algebra and Logic Gates By: Dr. Ahmed ElShafee ١ Minterms and Maxterms consider two binary variables x and y combined with an AND operation. Since eachv ariable may appear in either
More informationDigital System Design with SystemVerilog
Digital System Design with SystemVerilog Mark Zwolinski AAddison-Wesley Upper Saddle River, NJ Boston Indianapolis San Francisco New York Toronto Montreal London Munich Paris Madrid Capetown Sydney Tokyo
More informationGATE CSE. GATE CSE Book. November 2016 GATE CSE
GATE CSE GATE CSE Book November 2016 GATE CSE Preface This book is made thanks to the effort of GATE CSE members and Praneeth who made most of the latex notes for GATE CSE. Remaining work of completing
More informationDIGITAL CIRCUIT LOGIC UNIT 9: MULTIPLEXERS, DECODERS, AND PROGRAMMABLE LOGIC DEVICES
DIGITAL CIRCUIT LOGIC UNIT 9: MULTIPLEXERS, DECODERS, AND PROGRAMMABLE LOGIC DEVICES 1 Learning Objectives 1. Explain the function of a multiplexer. Implement a multiplexer using gates. 2. Explain the
More informationB.Sc.-IT (Part I) EXAMINATION, 2010 Computing Logics And Reasoning
1 B.Sc.-IT (Part I) EXAMINATION, 2010 Computing Logics And Reasoning Time allowed : Three Hours Maximum Marks : 50 Answer all ten questions (20 words each). Each question carries equal marks. Answer all
More informationNH 67, Karur Trichy Highways, Puliyur C.F, Karur District DEPARTMENT OF INFORMATION TECHNOLOGY CS 2202 DIGITAL PRINCIPLES AND SYSTEM DESIGN
NH 67, Karur Trichy Highways, Puliyur C.F, 639 114 Karur District DEPARTMENT OF INFORMATION TECHNOLOGY CS 2202 DIGITAL PRINCIPLES AND SYSTEM DESIGN UNIT 1 BOOLEAN ALGEBRA AND LOGIC GATES Review of binary
More informationDepartment of Computer Science & Engineering. Lab Manual DIGITAL LAB. Class: 2nd yr, 3rd sem SYLLABUS
Department of Computer Science & Engineering Lab Manual 435 DIGITAL LAB Class: 2nd yr, 3rd sem SYLLABUS. Verification of Boolean theorems using digital logic gates. 2. Design and implementation of code
More informationTEACHING & EXAMINATION SCHEME For the Examination COMPUTER SCIENCE. B.Sc. Part-I
TEACHING & EXAMINATION SCHEME For the Examination -2015 COMPUTER SCIENCE THEORY B.Sc. Part-I CS.101 Paper I Computer Oriented Numerical Methods and FORTRAN Pd/W Exam. Max. (45mts.) Hours Marks 150 2 3
More informationUNIT II - COMBINATIONAL LOGIC Part A 2 Marks. 1. Define Combinational circuit A combinational circuit consist of logic gates whose outputs at anytime are determined directly from the present combination
More information6.1 Combinational Circuits. George Boole ( ) Claude Shannon ( )
6. Combinational Circuits George Boole (85 864) Claude Shannon (96 2) Signals and Wires Digital signals Binary (or logical ) values: or, on or off, high or low voltage Wires. Propagate digital signals
More informationPROGRAMMABLE LOGIC DEVICES
PROGRAMMABLE LOGIC DEVICES Programmable logic devices (PLDs) are used for designing logic circuits. PLDs can be configured by the user to perform specific functions. The different types of PLDs available
More informationSystems Programming. Lecture 2 Review of Computer Architecture I
Systems Programming www.atomicrhubarb.com/systems Lecture 2 Review of Computer Architecture I In The Book Patt & Patel Chapter 1,2,3 (review) Outline Binary Bit Numbering Logical operations 2's complement
More informationComputer Architecture: Part III. First Semester 2013 Department of Computer Science Faculty of Science Chiang Mai University
Computer Architecture: Part III First Semester 2013 Department of Computer Science Faculty of Science Chiang Mai University Outline Decoders Multiplexers Registers Shift Registers Binary Counters Memory
More informationDIRECTORATE OF DISTANCE EDUCATION COMPUTER ORGANIZATION AND ARCHITECTURE/INTRODUCTION TO COMPUTER ORGANIZATION AND ARCHITECTURE
www.lpude.in DIRECTORATE OF DISTANCE EDUCATION COMPUTER ORGANIZATION AND ARCHITECTURE/INTRODUCTION TO COMPUTER ORGANIZATION AND ARCHITECTURE Copyright 2012 Lovely Professional University All rights reserved
More informationSRM ARTS AND SCIENCE COLLEGE SRM NAGAR, KATTANKULATHUR
SRM ARTS AND SCIENCE COLLEGE SRM NAGAR, KATTANKULATHUR 603203 DEPARTMENT OF COMPUTER SCIENCE & APPLICATIONS LESSON PLAN (207-208) Course / Branch : B.Sc CS Total Hours : 50 Subject Name : Digital Electronics
More informationEE 109L Review. Name: Solutions
EE 9L Review Name: Solutions Closed Book / Score:. Short Answer (6 pts.) a. Storing temporary values in (memory / registers) is preferred due to the (increased / decreased) access time. b. True / False:
More information2008 The McGraw-Hill Companies, Inc. All rights reserved.
28 The McGraw-Hill Companies, Inc. All rights reserved. 28 The McGraw-Hill Companies, Inc. All rights reserved. All or Nothing Gate Boolean Expression: A B = Y Truth Table (ee next slide) or AB = Y 28
More informationProgrammable Logic Devices
Programmable Logic Devices Programmable Logic Devices Fig. (1) General structure of PLDs Programmable Logic Device (PLD): is an integrated circuit with internal logic gates and/or connections that can
More informationAssignment (3-6) Boolean Algebra and Logic Simplification - General Questions
Assignment (3-6) Boolean Algebra and Logic Simplification - General Questions 1. Convert the following SOP expression to an equivalent POS expression. 2. Determine the values of A, B, C, and D that make
More informationSEMESTER SYSTEM, PROPOSED SCHEME FOR B.Sc. (ELECTRONICS), B.Sc. (ELECTRONICS MAINTENANCE)
SEMESTER SYSTEM, 2008 PROPOSED SCHEME FOR B.Sc. (ELECTRONICS), B.Sc. (ELECTRONICS MAINTENANCE) CLASS/ SEMESTER Sem-III Hons.-> Sem-IV Hons.-> B. Sc (Elex) B. Sc (Elex. Maint) EL-2101 Op-Amp & its Application
More informationFinal Exam Solution Sunday, December 15, 10:05-12:05 PM
Last (family) name: First (given) name: Student I.D. #: Circle section: Kim Hu Department of Electrical and Computer Engineering University of Wisconsin - Madison ECE/CS 352 Digital System Fundamentals
More informationCombinational Circuits
Combinational Circuits Combinational circuit consists of an interconnection of logic gates They react to their inputs and produce their outputs by transforming binary information n input binary variables
More information