SFWR ENG 2DA4 Lab 1. Announcements: Marking Scheme: Lab Safety Manual:

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1 SFWR ENG 2DA4 Lab 1 First lab Week of: Sept. 17, 2018 Prep Due week of: (8:40/14:40), Sept. 24, 2018 Demo Due Week of: (11:20/17:20), Sept. 24, 2018 Assignment due in class: 13:40, Sept. 28, 2018 Announcements: Note 1: All lab due dates/times are for your scheduled lab in the indicated week. Note 2: In this lab, you will be working through some tutorials for the Quartus Prime CAD software. They can be downloaded from: leduc/slides2d04/labs/quartustutorials For this and every lab: After you have demonstrated your lab to a TA (see Part 2, point 4), you must the final versions of your Verilog files (the ones demonstrated to the TA) as attachments to the following address: rlta1@cas.mcmaster.ca The subject line should state your lab group, and the lab number. The body of the message should list all group members. You do not have to submit the verilog files created during the tutorial. Failure to submit the files will result in a zero for your demonstration mark. These files will be checked against files submitted by other groups (including from previous years) to make sure students are submitting original work. Marking Scheme: The lab will be marked out of 10. Your preparation is worth 2 marks, and your demonstration of your lab to a TA (i.e. Part 4 below) is worth 6 marks. This mark will be the same for a given lab group. The final 2 marks will come from demonstrating knowledge of the working design by answering questions posed by the TA who marks your lab; it will be specific to each team member. This is to ensure both members understand the lab fully. Questions based directly on the lab are sometimes put on the midterm and final, and will be very difficult to do in the time allotted if you allowed your partner to do most of the work. Lab Safety Manual: Please read the SE 2DA4 Lab Safety Manual (downloadable from the 2DA4 lab website directory) before showing up for the lab. The TAs will give a brief safety introduction at the start of lab 1 and then you must pass a short quiz on the lab safety material before you can participate in the lab. 1

2 Part 1: Assignment Note: You must put your lab section on the top of your assignment as they will be handed back during your lab. The following are relevant (related to this lab and the midterm!) textbook questions to be handed in (in class) 13:40, Sept. 28, 2018: 1-3) Ch. 2# 3, 8, 13 4) For function f 1 in part 2, section 3.b below, provide the truth table, and the canonical product-of-sums. Then provide the minimal product-of-sums expression (show steps of derivation). NOTE: everyone must hand in their OWN assignment. Show ALL steps! WARNING: make sure you are using the correct edition of the textbook. Different editions (such as the international edition) usually have different exercise questions. Part 2: Practical Experience: 1. Purpose: The purpose of this part of the lab is to learn the basics of the Altera design software: design entry, simulation, compilation and device programming. You can use Quartus Prime on the Windows machines. You can also bring files from home, and use them directly on the systems in the lab. From the Altera website, you can download either the Standard Edition or the Lite Edition of Quartus Prime for Windows or Linux to install on your own PC/laptop. This should allow you to prepare your lab at home. See It is recommended to download and install the Quartus Prime Standard Edition, version 17.1, since this is the version that is installed on our lab computers. Quartus Prime Lite Edition is a free version. If you install the Standard Edition, you need to set up the license. To set up the license, click Tools License Setup... from Quartus, input 27000@alteralm.mcmaster.ca (without quotation marks) in the License File box. You may need a VPN connection to use the license file if you are off campus. Our labs will use DE1-SoC boards, which belong to Cyclone V family. Therefore three files are essential to download for the lab projects. They are: 1) Quartus Prime (include NIOS II EDS), 2) ModelSim-Intel FPGA Edition(includes Starter Edition), and 3) Cyclone V device support. For more details about license setup, please refer to the 2DA4 faq at: leduc/faq.html 2

3 2. Background: For Verilog, Section 2.10 and Appendix A (A.1-A.10, A.15). For theory, see course notes on sumof-products and product-of-sums and sections 2.5, 2.6, and 2.8. If this material has not yet been covered in class, you will have to read ahead. 3. Preparation: The purpose of the preparation is so that you show up for the lab session as prepared as possible. Ideally, by the start of the lab session (week of Sept. 24, 2018), your design is complete and simulates correctly. To get full marks for preparation, it must be complete (you have done everything that you have been asked to do), but it does not have to be fully working. This is to allow you to be able to get help from the TAs during the lab session, if needed. NOTE: Everyone does their own prep, then you choose one to hand in for the group. You should arrive at the lab with your preparation ready to hand in. Do not try to print it out at the start of the lab period. You must hand in as your preparation printouts of the Verilog code, the schematic (graphics) and the simulator output for all circuits for part 3(b). You do NOT need to include printouts from the Tutorial circuits. a) Make sure you first read the 2DA4 faq at: leduc/faq.html. It contains information about getting the software license working both at home and in the lab, as well as instructions for programming the boards. Do the three provided Quartus tutorials (see 2DA4 lab folder on course web site). The files are labelled: Quartus II Introduction Schematic.pdf, Quartus Std Introduction Verilog.pdf, and Quartus II Simulation.pdf. Because these tutorial materials may use the same name for projects or files, you need to create a separate project folder for each tutorial project to avoid compile time troubles. b) Design, enter and simulate a circuit, using Verilog as the primary entry method, that implements the following two output logic functions: You are to design two functions, f 1 and f 2, with four inputs named x 1, x 0, y 1, and y 0. Consider X = x 1 x 0 to be a number. The four possible patterns of x 1 x 0, namely 00, 01, 10, and 11 represent the four numbers 0, 1, 2, and 3, respectively. Similarly, consider Y = y 1 y 0 to be another number with the same four possible values. The function f 1 should be 1 when the two numbers represented by X and Y are NOT equal (i.e. X Y). Otherwise, f 1 should be 0. The function f 2 should be 1 when the number represented by X is greater than or equal to the number represented by Y (i.e. X Y), otherwise f 2 should be 0. Create truth tables for functions f 1 and f 2. Derive a Boolean expression in canonical productof-sums form for each function. Use algebraic manipulation to simplify the Boolean expression for f 1 (leave in minimal product-of-sum form or minimal sum-of-products). For f 2, we ll let Quartus do the work for us. Enter the simplified Boolean expressions (canonical for f 2 ) into Quartus in two different ways: 3

4 i) Draw a schematic that includes the logic gates for f 1 using the Block Editor. We are skipping here f 2 as this would be too much work. Call the file dual1.bdf. ii) Write Verilog code that represents both f 1 and f 2 as Boolean equations. Call the file dual2.v. Compile and then simulate the circuits. NOTE:For Quartus Prime version 17.1, timing simulations are not supported for the Cyclone V FPGA. For a project that is set up for Cyclone V, the result of running a timing simulation will be identical to the functional simulation. IMPORTANT: With Quartus version 17.1, the DE1-SoC boards and the Modelsim-Altera simulator, simulating labelled internal signals does not always work well. To correctly simulate these internal nets or regs that are used in your modules, please temporarily declare them as output ports. Verilog includes some synthesis attributes and directives such as/*synthesis keep*/, /*synthesis preserve */ and /*synthesis noprune */ that are supposed to handle this issue by preventing the desired node from being pruned during synthesis and optimization, but they do not currently appear to be working with this combination of software and hardware. 4. Lab Demonstrations of Circuits: You need to demonstrate your circuits to the TAs in the Lab as detailed below. a) For the circuit designed as part of the schematic editor tutorial that implements the function f = x 1 x 2 +x 1 x 2 connect the inputs x 1 and x 2 to toggle switches SW[9] and SW[8]. When the switch is set to its DOWN position (closest to the board edge), you get a logic low (0). The UP position gives logic high (1). Connect output f to the red LED labelled LEDR[9]. Driving the associated pin to a high logic level turns the LED on, and a low logic level turns it off. b) For the Verilog code dual2.v that you created above, connect the inputs x 1,x 0 and y 1,y 0 to toggle switches SW[9], SW[8], SW[7], and SW[6], respectively. Connect f 1 to the red LED labelled LEDR[9] and connect f 2 to the red LED labelled LEDR[8]. In each case you will do this by the following steps: (1) Opening the project file, make it the current project by using the appropriate File Open Project menu option. (2) Assign the Cyclone V FPGA (5CSEMA5F31C) device using the Assignments Device option. (3) Compile the project for the particular device. (4) Assign pins if needed using the Assignment Pin Planner to make the required Pin assignments and then recompile the design. You can look up the required pin assignments in the DE1-SoC User manual (Page 25 for SWs and Page 26 for LEDRs) that accompanies the boards and is also available as a PDF from the URL: leduc/slides2d04/labs/de1-soc User manual ref.pdf. 4

5 (5) With the help of the TAs: Connect a DE1-SoC board to the USB port of a PC running Quartus Prime and download the appropriate *.sof file with the Programmer. NOTE: To get credit for Part 4, YOU MUST DEMONSTRATE YOUR CIRCUITS FOR THE TAs IN THELAB.Youalsomust thefinalversionoftherequiredVerilogfilestotheindicated address. 5