430 Index. D flip-flop, from nands, 189, 191, 192 D flip-flop, verilog, 37
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1 Index *, in event control, 46 -> (event trigger), 177 $display, 34, 146, 165 $display, example, 44 $finish, 11, 165, 195, 196 $fullskew timing check, 297 $hold timing check, 298 $monitor, 34, 174 $nochange timing check, 299 $period timing check, 299 $readmemb, 414 $readmemh, 414 $recovery timing check, 298 $recrem timing check, 299 $removal timing check, 298 $sdf annotate, 407 $setup timing check, 298 $setuphold timing check, 298 $skew timing check, 297 $stop, 165, 195, 302 $strobe, 34, 174 $time, 34 $timeskew timing check, 297 $width timing check, 297, 299 adder vs. counter, 104 ALF, library format, 114 always block, 24, 177, 196 always, event control syntax, 32 always, for concurrency, 203 always, scope, 269 arithmetical shift, 121 array, addressing, 86 array, multidimensional, 85 array, select, 86 array, verilog, 84 arrayed instance, 213 assertion, defined, 34 assertion, example, 58 assign, continuous, 4, 14 assign-deassign, 415 assign-deassign, to avoid, 116 assignment, blocking, 32, 119, 178 assignment, nonblocking, 32, 119, 178 asynchronous control, priority, 48 asynchronous controls, 48, 49 automatic, 206 automatic task or function, 147 back-annotation, 19, 405 Backus-Naur Format (BNF), 45 BASIC programming language, 417 behavioral, 102, 104 behavioral flowchart, 134 behavioral synchronization, serial clock, 132 behavioral synthesis, 140 BIST (Built-In Self-Test), 382 bitwise operators, 12 BNF, 45 boundary scan, 379 bufif1, 122, 185, 217 bufif1, switch-level model, 251 Built-in self-test (BIST), 382 case, 31, 120 case equality, 121, 200 case, example, 122, 199 case, expression match, 199 case-sensitivity, verilog, 11 casex, expression match, 200 casex, to be avoided, 201 casez, expression match, 201 casez, wildcard match, 202 cell, configuration keyword,
2 430 Index charge strengths, 253 checksum, 89 chip failures, causes, 424 clock domains, 108 clock domains, 2-stage synchronizing ffs, 272 clock domains, independent, 235, 271 clock domains, serdes, 130, 131 clock domains, synchronizing latches, 272 clock generator, always, 33 clock generator, concurrent, 196 clock generator, forever, 33 clock generator, restartable, 197 clock, serdes embedded, 232, 235, 237, 239, 240 clocked block, 48 clocks, implementing, 33 cmos, 252 cmos primitive, 251 CMOS, switch-level primitive, 250 collapsing test vectors, 377 comment region, macro, 24, 27 comment tokens, verilog, 11 comment, synthesis directive, 24 comment, verilog, 23 concatenation, 87 concurrent block, 44 concurrent block names, scope, 269 conditional, 121 conditional operator, 31 conditional, expression match, 200 config, 280 config, configuration keyword, 280 config, scope, 269 config, to be avoided, 281 constant, verilog, 43 contention, 115, 124 contention in verilog, 114 continuous assignment, 4, 12, 14, 25, 48 corner case testing, 378 counter, 101, 104 counter, carry look-ahead, 106 counter, gray code, 107 counter, one-hot, 102 counter, ring, 107 counter, ripple, 106 counter, synchronous, 106 counter, unsigned binary, 101 counter, verilog, 71, 77 coverage summary, 377 coverage, hardware testing, 377 coverage, in software, 377 D flip-flop, from nands, 189, 191, 192 D flip-flop, verilog, 37 D latch, verilog, 37 DC macro, predefined, 27 decoder, example, 220 decoder, tree example, 220 decoder, verilog, 122 deep submicron effects, 421 default, configuration keyword, 280 default nettype, 186, 187, 216 define, 215 define, scope, 269 defparam, 415 defparam, to be avoided, 262 delay pessimism, 171 delay pessimism, moderated in specify, 305 delay triplet, example, 285 delay value, units, 13 delay, #0, 172 delay, 6-value in specify, 287 delay, blocking, 172 delay, conditional in specify, 288 delay, conflict within specify, 289 delay, declared on net, 284 delay, distributed, 282 delay, in nonblocking, 169 delay, intra-assignment, 169 delay, lumped, 282 delay, lumped example, 284 delay, min and max, 248 delay, multivalued, 171, 247 delay, nonblocking, 172 delay, not in UDP, 243 delay, overlap with specify, 289 delay, pessimism, 246 delay, polarity in specify, 288 delay, procedural, 23, 171, 178 delay, procedural avoided, 233 delay, regular, 169 delay, scheduled, delay, to x, 171 delay, transport (VHDL), 170 delay, triplet, 249 delay, trireg to x, 253 delay, with strength, 247 DesDecoder, project synthesizable, 339 Deserializer, concurrent schematic, 337 Deserializer, project schematic, 326 Design Compiler, flattening logic, 10 Design Compiler, script functionality, 7 Design for Test (DFT), 375 design partitioning, for synthesis, 271 design partitioning, rules, 270 design vision, netlist viewer, 7 design, configuration keyword, 280 DFT (Design for Test), 375
3 Index 431 DFT, summarized, 383 disable statement, 130 disable, example, 133 disable, task or function, 147 dont touch, in script vs verilog, 78 ECC, 88 90, 92, 93 ECC, finite element, 91 ECC, parity, 90 ECC, serial data, 94 ECO, example, 236 edge, functional defined, 246 edge, timing defined, 246 endconfig, configuration keyword, 280 equivalence checking verification, 425 error limit, pulse filter, 303 error-handler, generic, 164 event (keyword), 177 event control, 24 event 177 event control wait, 178 event control, inline, 32 event queue, stratified, 172, 173 event queue, verilog, 116 event, active, 170, 173, 174 event, declared, 177 event, future, 174 event, inactive (#0), 173, 174 event, monitor, 174 event, nonblocking, 174 event, queue example, 175 event, regular, 170 event, vs. evaluation, 173 exponentiation, 121 expression, defined, 46 fault simulator, 377 FIFO, 131, 151 FIFO bubble diagram, 159 FIFO dataflow, 152 FIFO parts, 153 FIFO project states, 158 FIFO schematic, 158 FIFO state logic, 159 FIFO transition logic, 160, 161, 163 FIFO, dual-port RAM, 338 FIFO, project dual-clocked, 338 FIFO, project synthesizable, 338 for, 31, 195, , 217 for, examples, 198 force-release, 415 force-release, to avoid, 116 forever, 195, 196 fork-join, 149, 170, 202, 203 formal proving verification, 425 format specifier, example, 35 format specifiers, 34 frame, serdes project, 69 full-duplex serdes, 392 full-path delay, 287 function, 146 function declaration, 146, 147 function, automatic, 206 function, example, 148, 233, 234 function, scope, 269 function, width indices, 207 gate-level, 104 generate, generate, block declarations, 218 generate, conditional, 215 generate, decoder tree, 222, 223 generate, loop example, 217 generate, loop scope quiz, 224 generate, looping, 216, 218 generate, no nesting, 216 generate, scope, 269 generate, simple decoder, 219 generate, unrolled naming, 218 genvar, 218 genvar, in looping generate, 216 hard macro, defined, 78 hierarchy, in verilog, 211 identifier, ASIC library component, 244 identifier, escaped, 44 identifier, verilog, 44 if, 31, 195 if, expression match, 199 ifdef, 215 ifdef example, 28 ifdef, example, 74 include, example, 73 inertial delay, 109, 119, 303 inertial delay example, 303 inertial delay, simulators, 172 initial, 196 initial block, 11, 24 initial block, example, 2, 12 initial, cautions, 33 initial, scope, 269 inout, 188 instance arrays, 213 instance, configuration keyword, 280, 281 instance, of module, 13 integer, 43 interface, in System Verilog, 270
4 432 Index interface, partitioning, 269 internal scan, 380 IP Block, 183 JTAG, 50, 52, 53, 59, 379 keywords lower case, 11 lane, defined, 392 lane, PCIe, 67 large, charge strength, 253 latch, 47 latch error, examples, 47 latch synthesis, 47 LFSR, 89, 91, 92, 383 LFSR polynomial, 90 Liberty library timing checks, 295 Liberty, library format, 114 LIFO, 151 literal, 43 literal expression, syntax, 13 literal syntax, 26 literal, syntax example, 15 localparam, 227, 259 localparam, conditional example, 357 localparam, example, 275 logic levels in verilog, 12 logical operators, 12 macro (compiler directive), 45 macro, examples, 73 macro, recommended usage, 28 medium, charge strength, 253 memory ECC, 88 Mentor proprietary information, xxi messaging tasks, 34 model checking verification, 425 module, 11 module header, 11, 12 module header formats, 21 module instance, scope, 269 module, ANSI header, 259 module, ANSI header example, 261 module, contents, 2 module, output reg ports, 415 module, scope, 269 module, traditional header, 260 module, traditional header example, 262 modules, for concurrency, 204 MOS, resistive strength rules, 250 MOS, switch-level primitives, 250 mux, schematic, 39 mux, switch-level model, 255 mux, verilog, 39 named block, 129, 130, 147 nand, switch-level model, 256 nmos, 251 nmos primitive, 250 noise estimation problems, 426 none (implied net default), 187 nor, switch-level model, 256 noshowcancelled inertia, 305 noshowcancelled specparam, 305 not, 217 not, switch-level model, 251, 252 notif1, 217 notifier, 297 notifier reg example, 303 notifier, in timing check, 296, 302 observability, 376 operator precedence, verilog, 121 operators, bitwise vs. logical, 128 operators, verilog table, 120 packet, serdes, 131 packet, serdes project, 69 parallel block (fork-join), 149 parallel-path delay, 287 parallel-serial converter, 78 parameter, 22, 27, 44, 80, 188, 227, 259 parameter declaration, 188 parameter override, 188, 189 parameter real, 259 parameter signed, 259 parameter, in ANSI header, 260 parameter, index range, 259 parameter, not in literals, 77 parameter, override by name, 260 parameter, override by position, 261 parameter, real, 73 parameter, signed, 73, 261 parity, memory, 88 partitioning, analog-digital example, 237 pass-switch primitives, 252 path delays, full and parallel, 287 PATHPULSE conflict rules, 304 PATHPULSE example, 304 PATHPULSE specparam, 303 PATHPULSE, inertial delay control, 303 PCI Express (PCIe), 67 PCIe lane, 67 PLL, 61 PLL 1x, 61 PLL comparator, synthesizable, 318 PLL, 1x schematic, 62 PLL, 1x synthesizable, PLL, 32x, 70
5 Index 433 PLL, 32x blocks, 71 PLL, 32x schematic, 72 PLL, clock extraction, 133 PLL, digital lock-in, 64 PLL, synthesizable, 314, 325 pmos, 251 pmos primitive, 250 port connection rules, 187 port map. of instance, 13 power distribution problems, 426 primitive, 243 primitive, scope, 269 procedural, 102 procedural assignment, 14 procedural block, 45 procedural block names, scope, 269 pulldown, 186 pulldown primitive, 252 pullup, 186 pullup primitive, 252 pulse filtering limits, 303 pulsestyle ondetect inertia, 305 pulsestyle ondetect specparam, 305 pulsestyle onevent inertia, 305 pulsestyle onevent specparam, 305 race condition, 49, 116, 117, 173 race condition, defined, 116 race, initial blocks, 118 RAM, bidir wrapper, 98 RAM, Mem1kx32 schematic, 96 RAM, simple verilog, 87 RAM, size issues, 83 rcmos primitive, 252 real variable, 62 realtime reg type, 306 reconvergent fanout, 36 reg, 12, 14 reg, in output port, 23 reg vs trireg, 253 reg, input port illegal, 23 rejection limit, pulse filter, 303 relational expression, of x, 119 repeat, 197 replication, 121 rnmos primitive, 250 rounding of decimals, 73 rpmos primitive, 250 RTL, 104, 132 RTL, defined, 103 rtran primitive, 252 rtranif0 primitive, 252 rtranif1 primitive, 252 scan chain, 56, 57 scan, boundary, 52, 379 scan, internal, 50, 380 scheduled conflicts, 172 SDC, Synopsys Design Constraint format, 415 SDF file, 18 SDF summary, 407 SDF syntax, 406, 407 SDF, delay override, 406 SDF, in verilog flow, 405 SDF, net delays, 406 SDF, path delays, 406 SDF, use with simulator, 406 serdes FIFO, 68 serdes project block diagram, 361 serdes, class project, 69 serdes, packet, 81 serdes, project block diagram, 312 serdes, project to full-duplex, 392 serial-parallel converter, 231 Serializer, project schematic, 363 shift register, 35 shift register, example, 234, 356 shift register, RTL, 40 shift register, schematic, 36, 38, 40 showcancelled inertia, 305 showcancelled specparam, 305 simulators, strength spotty, 123 small, charge strength, 253 soft errors, hardware, 375, 383 source switch-level models, 252 specify block, 285 specify block summary, 285 specify block, 6-value delays, 287 specify, scope, 269 specparam, 285, 286 specparam example, 286 specparam, with timing triplets, 286 SPEF, 406 SPICE, 251 SR latch, 5, 189, 190 state machine, design, 150 state machine, verilog, 151 statement, defined, 46 static serial clock synchronization, 141 strength, assigning, 115 strength, charge, 114 strength, charge values, 253 strength, drive, 113 strength, resistive MOS rules, 250 strength, table, 114 strength, with delay, 247 string, verilog, 44 strings, verilog storage, 33
6 434 Index structural, supply0 (net type), 187 supply1 (net type), 187 switch level, 114 switch-level model, 249 switch-level primitive logic, 185 Synopsys proprietary information, xxi system function, 45 system task, 45 System Verilog, 270, 415 System Verilog summary, 427 SystemC, 415 T flip-flop, 105, 143 table, in UDP, TAP, 423 TAP controller, 52, 379, 383 task, 146 task data sharing, 147 task declaration, 146 task, automatic, 206 task, concurrency example, 203 task, example, 233 task, exercise, 164 task, for concurrency., 202 task, scope, 269 testbench, Intro Top example, 2 three-state buffer, 122, 124 time reg type, 305 timescale, 16, 216 timescale macro, 13 timescale specifier, 4 timing arc, defined, 281 timing arc, examples, 282 timing check, 45 timing check as assertion, 295 timing check feature summary, 296 timing check negative limits, timing check notifier, 296, 302 timing check, conditional event, 302 timing check, data event, 296 timing check, limits must be constant, 297 timing check, reference event, 296 timing check, table of all 12, 297 timing check, time limits, 296 timing check, timecheck event, 296 timing check, timestamp event, 296 timing checks vs system tasks, 295 timing checks, in QuestaSim, 297 timing path and arcs, 281 timing path, causality, 282 timing triplet, example, 285 timing triplets, 249 toggle flip-flop, 105 tran primitive, 252 tranif0 primitive, 252, 255 tranif1 primitive, 252, 255 transfer-gate primitives, 252 tri (net type), 186 tri0 (net type), 186 tri1 (net type), 186 triand (net type), 186 trior (net type), 186 trireg (net type), 186 trireg switch-level net, 253 trireg vs tran primitive, 252 trireg, example, 253 TSMC proprietary information, xxi UDP, 243 UDP, combinational example, 244 UDP, sequential example, 245 UDP, summary, 246 use, configuration keyword, 280 VCD file, 17 vector, 13, 25 vector index syntax, 14 vector, bit significance, 15 vector, example, 16 vector, logical operator, 26 vector, negative index, 30 vector, select, 86 vector, sign bit, 25 vector, width (type) conversion, 26 verification, forrnal, 425 verification, functional, 424 verification, timing, 425 verilog tutorial, from Aldec, xxiii verilog, 1995 vs 2001, 413 verilog, ACC C routines, 418 verilog, arrayed instance, 213 verilog, attributes, 414 verilog, clocked block, 178 verilog, coding rules, 177, 178 verilog, comment directives, 414 verilog, compiler directives, 414, 417 verilog, conditional compile, 215 verilog, configuration, 279 verilog, declaration ordering, 205 verilog, declaration regions, 205 verilog, hierarchical names, 212, 213, 268 verilog, hierarchy path, 211 verilog, keywords, 414 verilog, named block, 129 verilog, PLI, 45, 415, 417 verilog, primitive gates, 185 verilog, scope of names, 269
7 Index 435 verilog, simulator file I/O, 414 verilog, synthesizable, 50 verilog, synthesizable summary, 413 verilog, system tasks and functions, verilog, TF C routines, 418 verilog, UDP (primitive), 243 verilog, variable, 43 verilog, VPI C routines, 418 VFO, project FastClock oscillator, 315 VFO, synthesizable, 315, 316 VHDL, 415 wand (net type), 186 watch-dog device, 208 while, 197, 198 while, examples, 198 width specifier, literals, 4 wire, 12 wire (net type), 186 wire, implied names, 186 wire, implied types, 186 wire, other net types, 186 wor (net type), 186 wrapper module methodology, 322
Index. B Back-annotation, 507 SDF, 508
$display, 57, 206 example, 69, 225 $fatal, SystemVerilog, 538 $finish, 206, 245 $fullskew timing check, 366 $hold timing check, 366 $info, SystemVerilog, 538 $monitor, 217 $monitor, 57 $nochange timing
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