2. (a) Compare the characteristics of a floppy disk and a hard disk. (b) Discuss in detail memory interleaving. [8+7]
|
|
- Brian Weaver
- 5 years ago
- Views:
Transcription
1 Code No: A R09 Set No (a) Explain the purpose of the following registers: i. IR ii. PC iii. MDR iv. MAR. (b) Explain with an example the steps in subtraction of two n-digit unsigned numbers. [8+7] 2. (a) Compare the characteristics of a floppy disk and a hard disk. (b) Discuss in detail memory interleaving. [8+7] 3. (a) Draw the logic diagram of a 2-to-4 line decoder using NOR gates only. Include an enable input and explain its functioning. (b) What is PAL? Explain the internal structure of PAL. [8+7] 4. (a) Formulate a hardware procedure for detecting an overflow by comparing the sign of the sum with the signs of the augend and addend. The numbers are in signed-2 s complement representation. (b) Design an array multiplier that multiplies two 2-bit numbers. [8+7] 5. (a) Give note on the registers in keyboard and display interfaces. (b) Explain the sequence of events involved in handshake scheme for an input data transfer. [8+7] 6. Simplify the following functions, and implement them with two-input NOR gates: (a) F = wx + y z + w yz (b) F(w,x,y,z) = Σ (5,6,9,10). [7+8] 7. (a) What is straight-line sequencing? Explain with an example. (b) Consider a computer that has a byte-addressable memory organized in 32-bit words according to the little-endian scheme. A program reads ASCII characters entered at a keyboard and stores them in the successive byte locations, starting at location Show the contents of the two memory words at locations 1000 and 1004 after the name Johnson has been entered. [7+8] 8. (a) Define the following terms: 1
2 Code No: A R09 Set No. 2 i. datapath ii. processor clock iii. multiphase clocking. (b) Give the timing diagram of a memory write operation and explain. [6+9] 2
3 Code No: A R09 Set No (a) Draw the truth table of 3 input NAND gate and write the Boolean Equation for a two-input NAND gate. (b) Simplify the Boolean function: F(W,X,Y,Z) = Σ (1,3,7,11,15) and the don t care conditions d(w,x,y,z) = Σ (0,2,5). [6+9] 2. (a) Perform the following arithmetic operation below with binary numbers and with negative numbers in signed-2 s complement representation. Use seven bits to accommodate each number together with its sign. i. (+35) + (+40) ii. (-35) + (-40). (b) Write the Booth s algorithm for multiplication of signed-2 s complement numbers. [8+7] 3. (a) Obtain the 1 s and 2 s complements of the following numbers: i ii iii iv (b) Mention the features of the following: i. Desktop computers ii. Workstations iii. Mainframes iv. Super computers. [8+7] 4. (a) Explain the organization of the control unit to allow conditional branching in the microprogram. (b) Discuss in detail the three-bus architecture. [7+8] 5. (a) Illustrate programmed-i/o with an example. (b) Draw the input interface circuit and explain. [8+7] 6. (a) Discuss the memory management requirements. (b) Explain the use of an associative-mapped TLB. [5+10] 3
4 Code No: A R09 Set No (a) Explain with an example how decoders with enable inputs can be connected to form a larger decoder. (b) Draw a 4-bit binary ripple counter and explain its way of functioning. [5+10] 8. (a) How strings are stored in memory? What are the two ways of indicating the length of the string? (b) Write an IA-32 routine to pack two BCD digits into a Byte and explain. [7+8] 4
5 Code No: A R09 Set No What is the need for bus arbitration? Explain the two approaches to bus arbitration. [15] 2. (a) What is meant by memory? Briefly explain micro-computer memories. (b) Draw and explain set associative cache organization. [7+8] 3. (a) Differentiate between RISC and CISC. (b) What are weighted codes? Explain with examples. (c) Convert the hexadecimal number F3A7C2 to binary and octal. [6+5+4] 4. (a) Find the complement of the functions F=A BC +A B C and G=A(B C +BC) by taking their duals and complementing each literal. (b) Minimize F(A,B,C,D) = Σ (3,6,8,11,13,14) and don t cares Σ (4,10,15).[8+7] 5. (a) Give the control sequence for a conditional branch instruction and explain. (b) Compare the two approaches for implementing the control unit of a processor. [8+7] 6. (a) Write the algorithm for adding and subtracting numbers in signed-2 s complement representation. (b) Show that adding B after the operation A+B +1 restores the original value of A. What should be done with the end carry? [7+8] 7. (a) Design an excess-3-to-binary decoder using the unused combinations of the code as don t-care conditions. (b) What is meant by combinational PLD? List and describe the major types of combinational PLDs. [9+6] 8. (a) IA-32 architecture has a large and flexible set of addressing modes. Justify the statement. (b) Which of the following IA-32 instructions would cause the assembler to issue a syntax error message? Why? i. ADD [EAX], [EBX + 4] ii. SUB EAX,[EBX + ESI*4 + 20] iii. MOV 20,EAX [9+6] 5
6 Code No: A R09 Set No Draw the flowchart for multiplication of two fixed point numbers when negative numbers are in signed-2 s complement representation and explain with an example. [15] 2. (a) Memory hierarchy design is based on the principle of Locality of Reference. Explain the principle. (b) Explain in detail various cache memory organizations. [5+10] 3. (a) How many address bit are needed to create an address space of 4G? (b) Give a note on the following: i. Condition codes ii. Big-endian and little-endian assignments iii. Straight line sequencing [3+12] 4. (a) What is a bus? Draw the figure to show how functional units are interconnected using a bus in a computer and explain. (b) Perform the subtraction with the following unsigned decimal numbers by taking 10 s complement of the subtrahend. i ii iii iv [7+8] 5. (a) Explain the operation of 3-to-8 decoder with circuit diagram. (b) Design a 4-bit synchronous binary based on JK flip-flops. [5+10] 6. (a) With a neat diagram explain the implementation of interrupt priority using individual interruptrequest and acknowledgment lines. (b) Summarize the bus signals of SCSI bus. [8+7] 7. (a) Draw the truth table for a three-input OR gate. (b) Explain the operation of a JK flip-flop using its block diagram and truth table. What are its limitations? [4+11] 8. (a) Explain how a word is fetched from memory. 6
7 Code No: A R09 Set No. 3 (b) Show the control steps for the Branch-on-Negative instruction for a processor that has the three-bus structure. [6+9] 7
SIDDHARTH GROUP OF INSTITUTIONS :: PUTTUR Siddharth Nagar, Narayanavanam Road QUESTION BANK (DESCRIPTIVE)
SIDDHARTH GROUP OF INSTITUTIONS :: PUTTUR Siddharth Nagar, Narayanavanam Road 517583 QUESTION BANK (DESCRIPTIVE) Subject with Code : STLD(16EC402) Year & Sem: II-B.Tech & I-Sem Course & Branch: B.Tech
More informationB.Tech II Year I Semester (R13) Regular Examinations December 2014 DIGITAL LOGIC DESIGN
B.Tech II Year I Semester () Regular Examinations December 2014 (Common to IT and CSE) (a) If 1010 2 + 10 2 = X 10, then X is ----- Write the first 9 decimal digits in base 3. (c) What is meant by don
More informationJNTUWORLD. 1. Discuss in detail inter processor arbitration logics and procedures with necessary diagrams? [15]
Code No: 09A50402 R09 Set No. 2 1. Discuss in detail inter processor arbitration logics and procedures with necessary diagrams? [15] 2. (a) Discuss asynchronous serial transfer concept? (b) Explain in
More informationMaanavaN.Com CS1202 COMPUTER ARCHITECHTURE
DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING QUESTION BANK SUB CODE / SUBJECT: CS1202/COMPUTER ARCHITECHTURE YEAR / SEM: II / III UNIT I BASIC STRUCTURE OF COMPUTER 1. What is meant by the stored program
More informationEND-TERM EXAMINATION
(Please Write your Exam Roll No. immediately) END-TERM EXAMINATION DECEMBER 2006 Exam. Roll No... Exam Series code: 100919DEC06200963 Paper Code: MCA-103 Subject: Digital Electronics Time: 3 Hours Maximum
More informationR10. II B. Tech I Semester, Supplementary Examinations, May
SET - 1 1. a) Convert the following decimal numbers into an equivalent binary numbers. i) 53.625 ii) 4097.188 iii) 167 iv) 0.4475 b) Add the following numbers using 2 s complement method. i) -48 and +31
More informationR a) Simplify the logic functions from binary to seven segment display code converter (8M) b) Simplify the following using Tabular method
SET - 1 1. a) Convert the decimal number 250.5 to base 3, base 4 b) Write and prove de-morgan laws c) Implement two input EX-OR gate from 2 to 1 multiplexer (3M) d) Write the demerits of PROM (3M) e) What
More informationPART A (22 Marks) 2. a) Briefly write about r's complement and (r-1)'s complement. [8] b) Explain any two ways of adding decimal numbers.
Set No. 1 IV B.Tech I Semester Supplementary Examinations, March - 2017 COMPUTER ARCHITECTURE & ORGANIZATION (Common to Electronics & Communication Engineering and Electronics & Time: 3 hours Max. Marks:
More informationCode No: R Set No. 1
Code No: R059210504 Set No. 1 II B.Tech I Semester Regular Examinations, November 2007 DIGITAL LOGIC DESIGN ( Common to Computer Science & Engineering, Information Technology and Computer Science & Systems
More informationUNIT I BASIC STRUCTURE OF COMPUTERS Part A( 2Marks) 1. What is meant by the stored program concept? 2. What are the basic functional units of a
UNIT I BASIC STRUCTURE OF COMPUTERS Part A( 2Marks) 1. What is meant by the stored program concept? 2. What are the basic functional units of a computer? 3. What is the use of buffer register? 4. Define
More informationINTELLIGENCE PLUS CHARACTER - THAT IS THE GOAL OF TRUE EDUCATION UNIT-I
UNIT-I 1. List and explain the functional units of a computer with a neat diagram 2. Explain the computer levels of programming languages 3. a) Explain about instruction formats b) Evaluate the arithmetic
More informationInjntu.com Injntu.com Injntu.com R16
1. a) What are the three methods of obtaining the 2 s complement of a given binary (3M) number? b) What do you mean by K-map? Name it advantages and disadvantages. (3M) c) Distinguish between a half-adder
More informationSIDDHARTH GROUP OF INSTITUTIONS :: PUTTUR Siddharth Nagar, Narayanavanam Road QUESTION BANK (DESCRIPTIVE) UNIT-I
SIDDHARTH GROUP OF INSTITUTIONS :: PUTTUR Siddharth Nagar, Narayanavanam Road 517583 QUESTION BANK (DESCRIPTIVE) Subject with Code : CO (16MC802) Year & Sem: I-MCA & I-Sem Course & Branch: MCA Regulation:
More informationCode No: R Set No. 1
Code No: R059210504 Set No. 1 II B.Tech I Semester Supplementary Examinations, February 2007 DIGITAL LOGIC DESIGN ( Common to Computer Science & Engineering, Information Technology and Computer Science
More informationQuestion Total Possible Test Score Total 100
Computer Engineering 2210 Final Name 11 problems, 100 points. Closed books, closed notes, no calculators. You would be wise to read all problems before beginning, note point values and difficulty of problems,
More informationDigital logic fundamentals. Question Bank. Unit I
Digital logic fundamentals Question Bank Subject Name : Digital Logic Fundamentals Subject code: CA102T Staff Name: R.Roseline Unit I 1. What is Number system? 2. Define binary logic. 3. Show how negative
More informationVALLIAMMAI ENGINEERING COLLEGE
VALLIAMMAI ENGINEERING COLLEGE SRM Nagar, Kattankulathur 603 203 DEPARTMENT OF INFORMATION TECHNOLOGY & COMPUTER SCIENCE AND ENGINEERING QUESTION BANK II SEMESTER CS6201- DIGITAL PRINCIPLE AND SYSTEM DESIGN
More informationR07. Code No: V0423. II B. Tech II Semester, Supplementary Examinations, April
SET - 1 II B. Tech II Semester, Supplementary Examinations, April - 2012 SWITCHING THEORY AND LOGIC DESIGN (Electronics and Communications Engineering) Time: 3 hours Max Marks: 80 Answer any FIVE Questions
More informationDC57 COMPUTER ORGANIZATION JUNE 2013
Q2 (a) How do various factors like Hardware design, Instruction set, Compiler related to the performance of a computer? The most important measure of a computer is how quickly it can execute programs.
More informationECE 341 Midterm Exam
ECE 341 Midterm Exam Time allowed: 75 minutes Total Points: 75 Points Scored: Name: Problem No. 1 (8 points) For each of the following statements, indicate whether the statement is TRUE or FALSE: (a) A
More informationArab Open University. Computer Organization and Architecture - T103
Arab Open University Computer Organization and Architecture - T103 Reference Book: Linda Null, Julia Lobur, The essentials of Computer Organization and Architecture, Jones & Bartlett, Third Edition, 2012.
More informationCourse Description: This course includes concepts of instruction set architecture,
Computer Architecture Course Title: Computer Architecture Full Marks: 60+ 20+20 Course No: CSC208 Pass Marks: 24+8+8 Nature of the Course: Theory + Lab Credit Hrs: 3 Course Description: This course includes
More informationSUBJECT CODE: IT T35 DIGITAL SYSTEM DESIGN YEAR / SEM : 2 / 3
UNIT - I PART A (2 Marks) 1. Using Demorgan s theorem convert the following Boolean expression to an equivalent expression that has only OR and complement operations. Show the function can be implemented
More informationCode No: R Set No. 1
Code No: R059210504 Set No. 1 II B.Tech I Semester Regular Examinations, November 2006 DIGITAL LOGIC DESIGN ( Common to Computer Science & Engineering, Information Technology and Computer Science & Systems
More informationCode No: 07A3EC03 Set No. 1
Code No: 07A3EC03 Set No. 1 II B.Tech I Semester Regular Examinations, November 2008 SWITCHING THEORY AND LOGIC DESIGN ( Common to Electrical & Electronic Engineering, Electronics & Instrumentation Engineering,
More informationVALLIAMMAI ENGINEERING COLLEGE
VALLIAMMAI ENGINEERING COLLEGE SRM Nagar, Kattankulathur 603 203 DEPARTMENT OF INFORMATION TECHNOLOGY QUESTION BANK Academic Year 2018 19 III SEMESTER CS8351-DIGITAL PRINCIPLES AND SYSTEM DESIGN Regulation
More informationDE Solution Set QP Code : 00904
DE Solution Set QP Code : 00904 1. Attempt any three of the following: 15 a. Define digital signal. (1M) With respect to digital signal explain the terms digits and bits.(2m) Also discuss active high and
More informationwww.vidyarthiplus.com Question Paper Code : 31298 B.E./B.Tech. DEGREE EXAMINATION, NOVEMBER/DECEMBER 2013. Third Semester Computer Science and Engineering CS 2202/CS 34/EC 1206 A/10144 CS 303/080230012--DIGITAL
More informationChapter 4. Combinational Logic
Chapter 4. Combinational Logic Tong In Oh 1 4.1 Introduction Combinational logic: Logic gates Output determined from only the present combination of inputs Specified by a set of Boolean functions Sequential
More information1. Draw general diagram of computer showing different logical components (3)
Tutorial 1 1. Draw general diagram of computer showing different logical components (3) 2. List at least three input devices (1.5) 3. List any three output devices (1.5) 4. Fill the blank cells of the
More informationCHETTINAD COLLEGE OF ENGINEERING AND TECHNOLOGY COMPUTER ARCHITECURE- III YEAR EEE-6 TH SEMESTER 16 MARKS QUESTION BANK UNIT-1
CHETTINAD COLLEGE OF ENGINEERING AND TECHNOLOGY COMPUTER ARCHITECURE- III YEAR EEE-6 TH SEMESTER 16 MARKS QUESTION BANK UNIT-1 Data representation: (CHAPTER-3) 1. Discuss in brief about Data types, (8marks)
More informationScheme G. Sample Test Paper-I
Sample Test Paper-I Marks : 25 Times:1 Hour 1. All questions are compulsory. 2. Illustrate your answers with neat sketches wherever necessary. 3. Figures to the right indicate full marks. 4. Assume suitable
More informationII/IV B.Tech (Regular/Supplementary) DEGREE EXAMINATION. Answer ONE question from each unit.
Hall Ticket Number: 14CS IT303 November, 2017 Third Semester Time: Three Hours Answer Question No.1 compulsorily. II/IV B.Tech (Regular/Supplementary) DEGREE EXAMINATION Common for CSE & IT Digital Logic
More informationSHRI ANGALAMMAN COLLEGE OF ENGINEERING. (An ISO 9001:2008 Certified Institution) SIRUGANOOR, TIRUCHIRAPPALLI
SHRI ANGALAMMAN COLLEGE OF ENGINEERING AND TECHNOLOGY (An ISO 9001:2008 Certified Institution) SIRUGANOOR, TIRUCHIRAPPALLI 621 105 DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING EC1201 DIGITAL
More informationHANSABA COLLEGE OF ENGINEERING & TECHNOLOGY (098) SUBJECT: DIGITAL ELECTRONICS ( ) Assignment
Assignment 1. What is multiplexer? With logic circuit and function table explain the working of 4 to 1 line multiplexer. 2. Implement following Boolean function using 8: 1 multiplexer. F(A,B,C,D) = (2,3,5,7,8,9,12,13,14,15)
More informationCO Computer Architecture and Programming Languages CAPL. Lecture 9
CO20-320241 Computer Architecture and Programming Languages CAPL Lecture 9 Dr. Kinga Lipskoch Fall 2017 A Four-bit Number Circle CAPL Fall 2017 2 / 38 Functional Parts of an ALU CAPL Fall 2017 3 / 38 Addition
More informationComputer Organization
Computer Organization It describes the function and design of the various units of digital computers that store and process information. It also deals with the units of computer that receive information
More informationVALLIAMMAI ENGINEERING COLLEGE. SRM Nagar, Kattankulathur DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING EC6302 DIGITAL ELECTRONICS
VALLIAMMAI ENGINEERING COLLEGE SRM Nagar, Kattankulathur-603 203 DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING EC6302 DIGITAL ELECTRONICS YEAR / SEMESTER: II / III ACADEMIC YEAR: 2015-2016 (ODD
More informationCS6303-COMPUTER ARCHITECTURE UNIT I OVERVIEW AND INSTRUCTIONS PART A
CS6303-COMPUTER ARCHITECTURE UNIT I OVERVIEW AND INSTRUCTIONS 1. Define Computer Architecture 2. Define Computer H/W 3. What are the functions of control unit? 4. 4.Define Interrupt 5. What are the uses
More informationINSTITUTE OF AERONAUTICAL ENGINEERING (Autonomous) Dundigal, Hyderabad
INSTITUTE OF AERONAUTICAL ENGINEERING (Autonomous) Dundigal, Hyderabad - 500043 Course Name : DIGITAL LOGIC DESISN Course Code : AEC020 Class : B Tech III Semester Branch : CSE Academic Year : 2018 2019
More informationSwitching Theory & Logic Design/Digital Logic Design Question Bank
Switching Theory & Logic Design/Digital Logic Design Question Bank UNIT I NUMBER SYSTEMS AND CODES 1. A 12-bit Hamming code word containing 8-bits of data and 4 parity bits is read from memory. What was
More informationCombinational Circuits
Combinational Circuits Combinational circuit consists of an interconnection of logic gates They react to their inputs and produce their outputs by transforming binary information n input binary variables
More information10EC33: DIGITAL ELECTRONICS QUESTION BANK
10EC33: DIGITAL ELECTRONICS Faculty: Dr.Bajarangbali E Examination QuestionS QUESTION BANK 1. Discuss canonical & standard forms of Boolean functions with an example. 2. Convert the following Boolean function
More informationINSTITUTE OF AERONAUTICAL ENGINEERING (Autonomous) Dundigal, Hyderabad
INSTITUTE OF AERONAUTICAL ENGINEERING (Autonomous) Dundigal, Hyderabad - 500 043 COMPUTER SCIENCE AND ENGINEERING TUTORIAL QUESTION BANK Name : DIGITAL LOGIC DESISN Code : AEC020 Class : B Tech III Semester
More informationHours / 100 Marks Seat No.
17333 13141 3 Hours / 100 Seat No. Instructions (1) All Questions are Compulsory. (2) Answer each next main Question on a new page. (3) Illustrate your answers with neat sketches wherever necessary. (4)
More informationDHANALAKSHMI SRINIVASAN COLLEGE OF ENGINEERING AND TECHNOLOGY
DHANALAKSHMI SRINIVASAN COLLEGE OF ENGINEERING AND TECHNOLOGY Dept/Sem: II CSE/03 DEPARTMENT OF ECE CS8351 DIGITAL PRINCIPLES AND SYSTEM DESIGN UNIT I BOOLEAN ALGEBRA AND LOGIC GATES PART A 1. How many
More informationDIGITAL ELECTRONICS. P41l 3 HOURS
UNIVERSITY OF SWAZILAND FACUL TY OF SCIENCE AND ENGINEERING DEPARTMENT OF PHYSICS MAIN EXAMINATION 2015/16 TITLE OF PAPER: COURSE NUMBER: TIME ALLOWED: INSTRUCTIONS: DIGITAL ELECTRONICS P41l 3 HOURS ANSWER
More informationPESIT Bangalore South Campus
INTERNAL ASSESSMENT TEST III Date : 21/11/2017 Max Marks : 40 Subject & Code : Computer Organization (15CS34) Semester : III (A & B) Name of the faculty: Mrs. Sharmila Banu Time : 11.30 am 1.00 pm Answer
More informationR07
www..com www..com SET - 1 II B. Tech I Semester Supplementary Examinations May 2013 SWITCHING THEORY AND LOGIC DESIGN (Com. to EEE, EIE, BME, ECC) Time: 3 hours Max. Marks: 80 Answer any FIVE Questions
More informationUPY14602-DIGITAL ELECTRONICS AND MICROPROCESSORS Lesson Plan
UPY14602-DIGITAL ELECTRONICS AND MICROPROCESSORS Lesson Plan UNIT I - NUMBER SYSTEMS AND LOGIC GATES Introduction to decimal- Binary- Octal- Hexadecimal number systems-inter conversions-bcd code- Excess
More informationNADAR SARASWATHI COLLEGE OF ENGINEERING AND TECHNOLOGY Vadapudupatti, Theni
NADAR SARASWATHI COLLEGE OF ENGINEERING AND TECHNOLOGY Vadapudupatti, Theni-625531 Question Bank for the Units I to V SEMESTER BRANCH SUB CODE 3rd Semester B.E. / B.Tech. Electrical and Electronics Engineering
More informationSimplification of Boolean Functions
Simplification of Boolean Functions Contents: Why simplification? The Map Method Two, Three, Four and Five variable Maps. Simplification of two, three, four and five variable Boolean function by Map method.
More informationUNIT - I: COMPUTER ARITHMETIC, REGISTER TRANSFER LANGUAGE & MICROOPERATIONS
UNIT - I: COMPUTER ARITHMETIC, REGISTER TRANSFER LANGUAGE & MICROOPERATIONS (09 periods) Computer Arithmetic: Data Representation, Fixed Point Representation, Floating Point Representation, Addition and
More informationECE 341 Midterm Exam
ECE 341 Midterm Exam Time allowed: 90 minutes Total Points: 75 Points Scored: Name: Problem No. 1 (10 points) For each of the following statements, indicate whether the statement is TRUE or FALSE: (a)
More informationPART B. 3. Minimize the following function using K-map and also verify through tabulation method. F (A, B, C, D) = +d (0, 3, 6, 10).
II B. Tech II Semester Regular Examinations, May/June 2015 SWITCHING THEORY AND LOGIC DESIGN (Com. to EEE, ECE, ECC, EIE.) Time: 3 hours Max. Marks: 70 Note: 1. Question Paper consists of two parts (Part-A
More informationCS2253 COMPUTER ORGANIZATION AND ARCHITECTURE 1 KINGS COLLEGE OF ENGINEERING DEPARTMENT OF INFORMATION TECHNOLOGY
CS2253 COMPUTER ORGANIZATION AND ARCHITECTURE 1 KINGS COLLEGE OF ENGINEERING DEPARTMENT OF INFORMATION TECHNOLOGY QUESTION BANK Sub. Code & Name: CS2253 Computer organization and architecture Year/Sem
More informationCOMPUTER ORGANIZATION AND ARCHITECTURE
Page 1 1. Which register store the address of next instruction to be executed? A) PC B) AC C) SP D) NONE 2. How many bits are required to address the 128 words of memory? A) 7 B) 8 C) 9 D) NONE 3. is the
More informationQUESTION BANK UNIT-I. 4. With a neat diagram explain Von Neumann computer architecture
UNIT-I 1. Write the basic functional units of computer? (Nov/Dec 2014) 2. What is a bus? What are the different buses in a CPU? 3. Define multiprogramming? 4.List the basic functional units of a computer?
More informationSIR C.R.REDDY COLLEGE OF ENGINEERING, ELURU DEPARTMENT OF INFORMATION TECHNOLOGY LESSON PLAN
SIR C.R.REDDY COLLEGE OF ENGINEERING, ELURU DEPARTMENT OF INFORMATION TECHNOLOGY LESSON PLAN SUBJECT: CSE 2.1.6 DIGITAL LOGIC DESIGN CLASS: 2/4 B.Tech., I SEMESTER, A.Y.2017-18 INSTRUCTOR: Sri A.M.K.KANNA
More informationCOLLEGE OF ENGINEERING DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING QUESTION BANK SUBJECT CODE & NAME: EC 1312 DIGITAL LOGIC CIRCUITS UNIT I
KINGS COLLEGE OF ENGINEERING DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING QUESTION BANK SUBJECT CODE & NAME: EC 1312 DIGITAL LOGIC CIRCUITS YEAR / SEM: III / V UNIT I NUMBER SYSTEM & BOOLEAN ALGEBRA
More informationCSCI 2121 Computer Organization and Assembly Language PRACTICE QUESTION BANK
CSCI 2121 Computer Organization and Assembly Language PRACTICE QUESTION BANK Question 1: Choose the most appropriate answer 1. In which of the following gates the output is 1 if and only if all the inputs
More informationComputer Organisation CS303
Computer Organisation CS303 Module Period Assignments 1 Day 1 to Day 6 1. Write a program to evaluate the arithmetic statement: X=(A-B + C * (D * E-F))/G + H*K a. Using a general register computer with
More informationKorea University of Technology and Education
MEC52 디지털공학 Binary Systems Jee-Hwan Ryu School of Mechanical Engineering Binary Numbers a 5 a 4 a 3 a 2 a a.a - a -2 a -3 base or radix = a n r n a n- r n-...a 2 r 2 a ra a - r - a -2 r -2...a -m r -m
More informationECE 2030B 1:00pm Computer Engineering Spring problems, 5 pages Exam Two 10 March 2010
Instructions: This is a closed book, closed note exam. Calculators are not permitted. If you have a question, raise your hand and I will come to you. Please work the exam in pencil and do not separate
More informationLOGIC DESIGN. Dr. Mahmoud Abo_elfetouh
LOGIC DESIGN Dr. Mahmoud Abo_elfetouh Course objectives This course provides you with a basic understanding of what digital devices are, how they operate, and how they can be designed to perform useful
More informationPrinciples of Digital Techniques PDT (17320) Assignment No State advantages of digital system over analog system.
Assignment No. 1 1. State advantages of digital system over analog system. 2. Convert following numbers a. (138.56) 10 = (?) 2 = (?) 8 = (?) 16 b. (1110011.011) 2 = (?) 10 = (?) 8 = (?) 16 c. (3004.06)
More information1. Mark the correct statement(s)
1. Mark the correct statement(s) 1.1 A theorem in Boolean algebra: a) Can easily be proved by e.g. logic induction b) Is a logical statement that is assumed to be true, c) Can be contradicted by another
More informationDepartment of Electrical and Computer Engineering University of Wisconsin - Madison. ECE/CS 352 Digital System Fundamentals.
Department of Electrical and Computer Engineering University of Wisconsin - Madison ECE/C 352 Digital ystem Fundamentals Quiz #2 Thursday, March 7, 22, 7:15--8:3PM 1. (15 points) (a) (5 points) NAND, NOR
More informationMULTIMEDIA COLLEGE JALAN GURNEY KIRI KUALA LUMPUR
STUDENT IDENTIFICATION NO MULTIMEDIA COLLEGE JALAN GURNEY KIRI 54100 KUALA LUMPUR SECOND SEMESTER FINAL EXAMINATION, 2013/2014 SESSION ITC2223 COMPUTER ORGANIZATION & ARCHITECTURE DSEW-E-F 1/13 18 FEBRUARY
More informationComputer organization and architecture UNIT-I 2 MARKS
Computer organization and architecture UNIT-I 1. What are the functional units? 2. what is meant by input unit? 3. What is meant by memory unit? 4. What are the operations in ALU? 5. What is meant by output
More informationDarshan Institute of Engineering & Technology for Diploma Studies Unit - 1
Darshan Institute of Engineering & Technology for Diploma Studies Unit - 1 1. Draw and explain 4 bit binary arithmetic or adder circuit diagram. A binary parallel adder is digital function that produces
More informationLOGIC CIRCUITS. Kirti P_Didital Design 1
LOGIC CIRCUITS Kirti P_Didital Design 1 Introduction The digital system consists of two types of circuits, namely (i) Combinational circuits and (ii) Sequential circuit A combinational circuit consists
More informationCOPYRIGHTED MATERIAL INDEX
INDEX Absorption law, 31, 38 Acyclic graph, 35 tree, 36 Addition operators, in VHDL (VHSIC hardware description language), 192 Algebraic division, 105 AND gate, 48 49 Antisymmetric, 34 Applicable input
More informationQUESTION BANK FOR TEST
CSCI 2121 Computer Organization and Assembly Language PRACTICE QUESTION BANK FOR TEST 1 Note: This represents a sample set. Please study all the topics from the lecture notes. Question 1. Multiple Choice
More informationChap.3 3. Chap reduces the complexity required to represent the schematic diagram of a circuit Library
3.1 Combinational Circuits 2 Chap 3. logic circuits for digital systems: combinational vs sequential Combinational Logic Design Combinational Circuit (Chap 3) outputs are determined by the present applied
More informationChapter Three. Digital Components
Chapter Three 3.1. Combinational Circuit A combinational circuit is a connected arrangement of logic gates with a set of inputs and outputs. The binary values of the outputs are a function of the binary
More informationComputer Architecture
Computer Architecture Lecture 1: Digital logic circuits The digital computer is a digital system that performs various computational tasks. Digital computers use the binary number system, which has two
More informationDIGITAL ARITHMETIC: OPERATIONS AND CIRCUITS
C H A P T E R 6 DIGITAL ARITHMETIC: OPERATIONS AND CIRCUITS OUTLINE 6- Binary Addition 6-2 Representing Signed Numbers 6-3 Addition in the 2 s- Complement System 6-4 Subtraction in the 2 s- Complement
More informationUNIT I DATA REPRESENTATION, MICRO-OPERATIONS, ORGANIZATION AND DESIGN
UNIT I DATA REPRESENTATION, MICRO-OPERATIONS, ORGANIZATION AND DESIGN Data representation: Data types, complements, fixed point representation, floating-point representation, other binary codes, error
More informationCOMP2121: Microprocessors and Interfacing. Instruction Set Architecture (ISA)
COMP2121: Microprocessors and Interfacing Instruction Set Architecture (ISA) http://www.cse.unsw.edu.au/~cs2121 Lecturer: Hui Wu Session 2, 2017 1 Contents Memory models Registers Data types Instructions
More informationHonorary Professor Supercomputer Education and Research Centre Indian Institute of Science, Bangalore
COMPUTER ORGANIZATION AND ARCHITECTURE V. Rajaraman Honorary Professor Supercomputer Education and Research Centre Indian Institute of Science, Bangalore T. Radhakrishnan Professor of Computer Science
More informationCombinational Logic II
Combinational Logic II Ranga Rodrigo July 26, 2009 1 Binary Adder-Subtractor Digital computers perform variety of information processing tasks. Among the functions encountered are the various arithmetic
More informationChapter 1. Digital Systems and Binary Numbers
Chapter 1. Digital Systems and Binary Numbers Tong In Oh 1 1.1 Digital Systems Digital age Characteristic of digital system Generality and flexibility Represent and manipulate discrete elements of information
More informationDepartment of Computer Science and Engineering CS6303-COMPUTER ARCHITECTURE UNIT-I OVERVIEW AND INSTRUCTIONS PART A
Department of Computer Science and Engineering CS6303-COMPUTER ARCHITECTURE UNIT-I OVERVIEW AND INSTRUCTIONS PART A 1.Define Computer Architecture Computer Architecture Is Defined As The Functional Operation
More informationBHARATHIDASAN ENGINEERING COLLEGE Degree / Branch : B.E./ECE Year / Sem : II/ III Sub.Code / Name : EC6302/DIGITAL ELECTRONICS
BHARATHIDASAN ENGINEERING COLLEGE Degree / Branch : B.E./ECE Year / Sem : II/ III Sub.Code / Name : EC6302/DIGITAL ELECTRONICS FREQUENTLY ASKED QUESTIONS UNIT I MINIMIZATION TECHNIQUES AND LOGIC GATES
More informationHours / 100 Marks Seat No.
17320 21718 3 Hours / 100 Seat No. Instructions (1) All Questions are Compulsory. (2) Answer each next main Question on a new page. (3) Figures to the right indicate full marks. (4) Assume suitable data,
More informationThe Institution of Engineers - Sri Lanka
/ The Institution of Engineers - Sri Lanka PART III- EXAMINATION 2012 311- COMPUTER SYSTEMS ENGINEERING Time Allowed: 3 hours INSTRUCTIONS TO CANDIDATES 1. This paper contains 8 questions in 5 pages 2.
More informationMicrocomputers. Outline. Number Systems and Digital Logic Review
Microcomputers Number Systems and Digital Logic Review Lecture 1-1 Outline Number systems and formats Common number systems Base Conversion Integer representation Signed integer representation Binary coded
More informationCombinational Logic. Prof. Wangrok Oh. Dept. of Information Communications Eng. Chungnam National University. Prof. Wangrok Oh(CNU) 1 / 93
Combinational Logic Prof. Wangrok Oh Dept. of Information Communications Eng. Chungnam National University Prof. Wangrok Oh(CNU) / 93 Overview Introduction 2 Combinational Circuits 3 Analysis Procedure
More information5. (a) What is secondary storage? How does it differ from a primary storage? (b) Explain the functions of (i) cache memory (ii) Register
General Concepts 1. (a) What are combinational circuits? (b) Perform the following: (i) Convert (0.5625) 10 = ( ) 2 (ii) (010010) 2 (100011) 2 = ( ) 2 2. (a) Using truth table prove that A B= A+ B (b)
More informationEE 8351 Digital Logic Circuits Ms.J.Jayaudhaya, ASP/EEE
EE 8351 Digital Logic Circuits Ms.J.Jayaudhaya, ASP/EEE 1 Logic circuits for digital systems may be combinational or sequential. A combinational circuit consists of input variables, logic gates, and output
More informationCOMPUTER ARCHITECTURE AND ORGANIZATION Register Transfer and Micro-operations 1. Introduction A digital system is an interconnection of digital
Register Transfer and Micro-operations 1. Introduction A digital system is an interconnection of digital hardware modules that accomplish a specific information-processing task. Digital systems vary in
More informationDigital Fundamentals. CHAPTER 2 Number Systems, Operations, and Codes
Digital Fundamentals CHAPTER 2 Number Systems, Operations, and Codes Decimal Numbers The decimal number system has ten digits: 0, 1, 2, 3, 4, 5, 6, 7, 8, and 9 The decimal numbering system has a base of
More informationBinary Addition. Add the binary numbers and and show the equivalent decimal addition.
Binary Addition The rules for binary addition are 0 + 0 = 0 Sum = 0, carry = 0 0 + 1 = 0 Sum = 1, carry = 0 1 + 0 = 0 Sum = 1, carry = 0 1 + 1 = 10 Sum = 0, carry = 1 When an input carry = 1 due to a previous
More information(ii) Simplify and implement the following SOP function using NOR gates:
DHANALAKSHMI COLLEGE OF ENGINEERING DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING EE6301 DIGITAL LOGIC CIRCUITS UNIT I NUMBER SYSTEMS AND DIGITAL LOGIC FAMILIES PART A 1. How can an OR gate be
More informationUNIT - V MEMORY P.VIDYA SAGAR ( ASSOCIATE PROFESSOR) Department of Electronics and Communication Engineering, VBIT
UNIT - V MEMORY P.VIDYA SAGAR ( ASSOCIATE PROFESSOR) contents Memory: Introduction, Random-Access memory, Memory decoding, ROM, Programmable Logic Array, Programmable Array Logic, Sequential programmable
More informationD I G I T A L C I R C U I T S E E
D I G I T A L C I R C U I T S E E Digital Circuits Basic Scope and Introduction This book covers theory solved examples and previous year gate question for following topics: Number system, Boolean algebra,
More informationKING FAHD UNIVERSITY OF PETROLEUM & MINERALS COMPUTER ENGINEERING DEPARTMENT
KING FAHD UNIVERSITY OF PETROLEUM & MINERALS COMPUTER ENGINEERING DEPARTMENT COE 202: Digital Logic Design Term 162 (Spring 2017) Instructor: Dr. Abdulaziz Barnawi Class time: U.T.R.: 11:00-11:50AM Class
More informationII/IV B.Tech (Regular/Supplementary) DEGREE EXAMINATION. Discrete Mathematical Structures. Answer ONE question from each unit.
14CS IT302 November,2016 II/IV B.Tech (Regular/Supplementary) DEGREE EXAMINATION Common for CSE & IT Discrete Mathematical Structures (4X12=48 Marks) 1. Answer all questions (1X12=12 Marks) a (Pv~P) is
More informationthat system. weighted value associated with it. numbers. a number. the absence of a signal. MECH 1500 Quiz 2 Review Name: Class: Date:
Name: Class: Date: MECH 1500 Quiz 2 Review True/False Indicate whether the statement is true or false. 1. The decimal system uses the number 9 as its base. 2. All digital computing devices perform operations
More information