The Instruction Set. Chapter 5

Transcription

1 The Instruction Set Architecture Level(ISA) Chapter 5 1

2 ISA Level The ISA level l is the interface between the compilers and the hardware. (ISA level code is what a compiler outputs) 2

3 Memory Models An 8-byte word in a little-endian memory. (a) Aligned. (b) Not aligned. Some machines require that words in memory be aligned. 3

4 Overview of the Pentium 4 ISA Level The Pentium 4 s primary registers. P4 fetches 8bytes at a time from the memory is 32-bit, all called IA-32. 4

5 1. Special purpose register 2. General purpose register Registers SPR : program counter, stack pointer. GPR : hold local variable, intermediate results of calculations. P4 has three operating modes: real mode: behaves like 8088, any wrong in the program crash. Virtual 8086 mode: operating system control the whole machine. Protected mode: behaves like P4. 5

6 Registers a) Use 8-bit name, 16-bit name, or 32-bit name b) Applies to EAX, EBX, ECX, and EDX 8 AH 8 AL 8 bits + 8 bits AX 16 bits EAX 32 bits 6

7 General-Purpose Registers a) EAX Accumulator for operands and results data, div&mul b) EBX Pointer to data in the DS segment (Memory address) c) ECX Counter for string and loop operations d) EDX I/O pointer e) ESI (Source index) Pointer to data in the segment pointed to by the DS register; source pointer for string operations f) EDI (Destination index) Pointer to data (or destination) in the segment pointed to by the ES register; destination pointer for string operations g) ESP (Stack pointer) Stack pointer (in the SS segment) h) EBP (Base pointer )Pointer to data on the stack (in the SS segment) point to the base of the current stack. 7

8 Register a) Segment CS code segment DS data segment SS stack segment ES, FS, GS - additional segments b) EIP instruction pointer c) EFLAGS control flags (control CPU s operation, e.g. break, interrupt, enter 8086/protected mode) Status flag each flag is a single binary bit (set or clear) 8

9 Status Flags Carry (CF) unsigned arithmetic out of range Overflow (OF) signed arithmetic out of range Sign (SF) result is negative Zero (ZF) result is zero Auxiliary Carry (AC) carry from bit 3 to bit 4 in 8-bit operand Parity (PF) sum of 1 bits in least-significant byte is an even number 9

10 Segment Registers 10

11 Overview of the 8051 ISA Level (a) On chip memory organization for the 8051 (a) On-chip memory organization for the (b) Major 8051 registers. 11

12 8051 Summary of features of the standard K bytes internal ROM (program) 128 bytes internal RAM (data) Four 8-bit I/O ports Two 16-bit timers Serial interface 64K external code memory space 64K external data memory space 210 bit-addressable bl locations 12

13 implements a separate memory space for programs (code) and data. Both code and data may be internal, however, both expand using external components to a maximum of 64K code memory and 64K data memory. Internal memory consists of on-chip ROM and on-chip data RAM. On-chip RAM contains a rich arrangement of general purpose p storage, bit addressable storage, register banks, and special function registers. In the 8051, the registers and input/output ports are memory mapped and accessible like any other memory location. In the 8051, the stack resides within the internal RAM, rather than in external RAM. 13

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18 Data Types on the Pentium 4 The Pentium 4 numeric data types. Supported types are marked with. 18

19 Data Types on the 8051 The 8051 numeric data types. Supported types are marked with. 19

20 Instruction Formats (1) Four common instruction formats: (a) Zero-address instruction. (b) One-address instruction (c) Two-address instruction. (d) Three-address instruction. 20

21 Instruction Formats (2) Some possible relationships between instruction and word length. 21

22 Expanding Opcodes (1) An instruction ti with a 4-bit opcode and three 4-bit address fields. 22

23 Expanding Opcodes (2) An expanding opcode allowing 15 three-address instructions, 14 two-address instructions, 31 one-address instructions, and 16 zero-address instructions. ti The fields marked xxxx, yyyy, and zzzz are 4-bit address fields. 23

24 The Pentium 4 Instruction Formats The Pentium 4 instruction ti formats. 24

25 The 8051 Instruction Formats The 8051 instruction ti formats. 25

26 Addressing Modes a) Immediate b) Direct c) Indirect d) Register e) Register Indirect f) Displacement (Indexed) g) Stack 26

27 Immediate Addressing a) Operand is part of instruction b) Operand = address field c) e.g. ADD 5 Add 5 to contents of accumulator 5 is operand d) No memory reference to fetch data e) Fast f) Limited range Opcode Operand 27

28 Direct Addressing a) Address field contains address of operand b) Effective address (EA) = address field (A) c) e.g. ADD A Add contents of cell A to accumulator Look in memory at address A for operand d) Single memory reference to access data e) No additional calculations to work out effective address f) Limited address space 28

29 Direct Addressing Diagram Instruction ti Opcode Address A Memory Operand 29

30 Indirect Addressing (1) a) Memory cell pointed to by address field contains the address of (pointer to) the operand b) EA = (A) Look in A, find address (A) and look there for operand c) e.g. ADD (A) Add contents of cell pointed to by contents of A to accumulator 30

31 Indirect Addressing (2) a) Large address space b) 2 n where n = word length c) Multiple memory accesses to find operand d) Hence slower 31

32 Indirect Addressing Diagram Instruction Opcode Address A Memory Pointer to operand Operand 32

33 Register Addressing (1) a) Operand is held in register named in address filed b) EA = R c) Limited number of registers d) Very small address field needed Shorter instructions Faster instruction fetch 33

34 Register Addressing (2) a) No memory access b) Very fast execution c) Very limited address space d) Multiple registers helps performance e) Direct addressing 34

35 Register Addressing Diagram Instruction ti Opcode Register Address R Registers s Operand 35

36 Register Indirect Addressing a) indirect addressing b) EA = (R) c) Operand is in memory cell pointed to by contents of register R d) Large address space (2 n ) e) One fewer memory access than indirect addressing 36

37 Register Indirect Addressing Diagram Instruction Opcode Register Address R Memory Registers Pointer to Operand Operand 37

38 Displacement Addressing a) EA = A + (R) b) Address field hold two values A = base value R = register that holds displacement or vice versa 38

39 Displacement Addressing Diagram Instruction Opcode Register R Address A Memory Registers Pointer to Operand + Operand 39

40 Relative Addressing a) A version of displacement addressing b) R = Program counter, PC c) EA = A + (PC) d) i.e. get operand from A cells from current location pointed to by PC e) locality of reference & cache usage

41 Base-Register Addressing a) A holds displacement b) R holds pointer to base address c) R may be explicit or implicit d) e.g. segment registers in 80x8686

42 Indexed Addressing a) A = base b) R = displacement c) EA = A + R d) Good for accessing arrays EA = A + R R++

43 Indexed Addressing (1) A generic assembly program for computing the OR of Ai AND Bi for two 1024-element arrays.

44 Indexed Addressing (2) A possible representation of MOV R4,A(R2).

45 Combinations a) Post index b) EA = (A) + (R) c) Pre index d) EA = (A+(R))

46 Pentium Addressing Modes a) Virtual or effective address is offset into segment Starting address plus offset gives linear address This goes through page translation if paging enabled b) 12 addressing modes available Immediate Register operand Displacement Base Base with displacement Scaled index with displacement Base with index and displacement Base scaled index with displacement

47 he Pentium 4 Addressing Modes (1) The Pentium 4 32-bit addressing modes. M[x]

48 he Pentium 4 Addressing Modes (2) Access to a[i].

49 Loop Control (a) Test-at-the-end loop. (b) Test-at-the-beginning loop.

50 Input/Output (1) Three different I/O schemes are in current use in personal computers Programmed I/O with busy waiting. Interrupt-driven I/O. DMA I/O.

51 Input/Output (1) Device registers for a simple terminal (Status & Data). 4, each is 1 Byte, two for (In) and two for (out). Memory mapped I/O, part of the memory, Ordinary instructions. Otherwise use IN, OUT. Bit 7 sits by the hardware whenever a character arrives. If the software has previously set bit 6, an interrupt is generated In programmed I/O, CPU sits a tight loop repeatedly reading the keyboard status register then the software read the buffer. To write a character to the screen, the software first reads the display status t register to see if the READY bit is 1.

52 Input/Output (2) An example of programmed I/O.

53 Input/Output (2) Disadvantage of programmed I/O. CPU spends most of the time waiting the device to be ready (called busy waiting) The way to get rid of busy waiting is to have the CPU start the I/O device and tell it to generate an interrupt when it is done. Disadvantage is that, interrupt is required for every character transmitted.

54 Input/Output (3) DMA (Direct Memory Access) chip has at least four registers. The first one contains the memory address to be read. The second one contains the count, how many bytes (or word ) are to be transferred. The third one specifies the device number or I/O space address to use. Thus specifying i which h I/O device is desired. d The fourth one tells whether data are to be read from or writing to the I/O device. To write a block of 32 bytes from memory address 100 to terminal 4, the CPU writes 32, 100, 4, and 1 for write. DMA controller makes a bus request to read from memory, the another request to write to the terminal. When the count reach 0, DMA controller asserts the interrupt line on the CPU chip.

55 Input/Output t t (3) A system with a DMA controller.

56 The Pentium 4 Instructions (1) A selection of the Pentium 4 integer instructions.

57 The Pentium 4 Instructions (2) A selection of the Pentium 4 integer instructions.

58 The Pentium 4 Instructions (3) A selection of the Pentium 4 integer instructions.

59 The Pentium 4 Instructions (4) A selection of the Pentium 4 integer instructions.

60 8051 Instructions (1) The 8051 Instruction set.

61 8051 Instructions (2) The 8051 Instruction set.

62 8051 Instructions (3) The 8051 Instruction set.

63 8051 Instructions (4) The 8051 Instruction set.

64 8051 Instructions (5) The 8051 Instruction set.