Math 230 Assembly Programming (AKA Computer Organization) Spring 2008

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1 Math 230 Assembly Programming (AKA Computer Organization) Spring 2008 MIPS Intro II Lect 10 Feb 15, 2008 Adapted from slides developed for: Mary J. Irwin PSU CSE331 Dave Patterson s UCB CS152 M230 L10.1 Smith Spring 2008

2 MIPS Data Types Bit: 0, 1 Bit String: sequence of bits of a particular length 4 bits is a nibble 8 bits is a byte 16 bits is a half-word 32 bits (4 bytes) is a word 64 bits is a double-word Character: ASCII 7 bit code Decimal: digits 0-9 encoded as 0000b thru 1001b two decimal digits packed per 8 bit byte Integers: 2's complement Floating Point M230 L10.2 Smith Spring 2008

3 Review: MIPS R3000 Instruction Set Architecture Instruction Categories Load/Store Computational Jump and Branch Floating Point - coprocessor Memory Management Special Registers R0 - R31 PC HI LO 3 Instruction Formats: all 32 bits wide OP OP OP rs rt rd sa funct rs rt immediate jump target M230 L10.3 Smith Spring 2008

4 MIPS Instructions, so far Category Instr Op Code Example Meaning Arithmetic (R format) add subtract 0 and 32 0 and 34 add $s1, $s2, $s3 sub $s1, $s2, $s3 $s1 = $s2 + $s3 $s1 = $s2 - $s3 Data transfer (I format) load word store word lw $s1, 100($s2) sw $s1, 100($s2) $s1 = Memory($s2+100) Memory($s2+100) = $s1 M230 L10.4 Smith Spring 2008

5 Processor Memory Interconnections Memory is viewed as a large, single-dimension array, with an address A memory address is an index into the array read addr/ write addr Processor read data Memory? # of words? write data 32 bits M230 L10.6 Smith Spring 2008

6 Processor Memory Interconnections Memory is viewed as a large, single-dimension array, with an address A memory address is an index into the array read addr/ write addr 32 Processor read data Memory? # of words? write data 32 bits M230 L10.6 Smith Spring 2008

7 Processor Memory Interconnections Memory is viewed as a large, single-dimension array, with an address A memory address is an index into the array read addr/ write addr 32 Processor read data 32 Memory? # of words? write data 32 bits M230 L10.6 Smith Spring 2008

8 Processor Memory Interconnections Memory is viewed as a large, single-dimension array, with an address A memory address is an index into the array read addr/ write addr 32 Processor read data 32 Memory? # of words? 32 write data 32 bits M230 L10.6 Smith Spring 2008

9 Processor Memory Interconnections Memory is viewed as a large, single-dimension array, with an address A memory address is an index into the array read addr/ write addr 32 Processor read data 32 Memory? words # of words? 32 write data 32 bits M230 L10.6 Smith Spring 2008

10 Review: Naming Conventions for Registers 0 $zero constant 0 (Hdware) 1 $at reserved for assembler 2 $v0 expression evaluation & 3 $v1 function results 4 $a0 arguments 5 $a1 6 $a2 7 $a3 8 $t0 temporary: caller saves... (callee can clobber) 15 $t7 16 $s0 callee saves... (caller can clobber) 23 $s7 24 $t8 temporary (cont d) 25 $t9 26 $k0 reserved for OS kernel 27 $k1 28 $gp pointer to global area 29 $sp stack pointer 30 $fp frame pointer 31 $ra return address (Hdware) M230 L10.7 Smith Spring 2008

11 Byte Addresses Since 8-bit bytes are so useful, most architectures address individual bytes in memory Therefore, the memory address of a word must be a multiple of 4 (alignment restriction) Big Endian: leftmost byte is word address IBM 360/370, Motorola 68k, MIPS, Sparc, HP PA Little Endian: rightmost byte is word address Intel 80x86, DEC Vax, DEC Alpha (Windows NT) M230 L10.8 Smith Spring 2008

12 M230 L10.9 Smith Spring 2008

13 Addressing Objects: Endianess and Alignment Big Endian: Little Endian: leftmost byte is word address rightmost byte is word address msb lsb Aligned Alignment restriction: requires that objects fall on address that is multiple of their size. Not Aligned M230 L10.11 Smith Spring 2008

14 Addressing Objects: Endianess and Alignment Big Endian: Little Endian: leftmost byte is word address rightmost byte is word address little endian byte 0 msb lsb Aligned Alignment restriction: requires that objects fall on address that is multiple of their size. Not Aligned M230 L10.11 Smith Spring 2008

15 Addressing Objects: Endianess and Alignment Big Endian: Little Endian: leftmost byte is word address rightmost byte is word address little endian byte 0 msb lsb big endian byte 0 Aligned Alignment restriction: requires that objects fall on address that is multiple of their size. Not Aligned M230 L10.11 Smith Spring 2008

16 Addressing Objects: Endianess and Alignment Big Endian: Little Endian: leftmost byte is word address rightmost byte is word address little endian byte 0 msb lsb big endian byte 0 Aligned Alignment restriction: requires that objects fall on address that is multiple of their size. Not Aligned M230 L10.11 Smith Spring 2008

17 MIPS Memory Addressing The memory address is formed by summing the constant portion of the instruction and the contents of the second (base) register $s3 holds 8 Memory Data Word Address lw $t0, 4($s3) #what? is loaded into $t0 sw $t0, 8($s3) #$t0 is stored where? M230 L10.14 Smith Spring 2008

18 MIPS Memory Addressing The memory address is formed by summing the constant portion of the instruction and the contents of the second (base) register $s3 holds 8 Memory Data 0 Word Address lw $t0, 4($s3) #what? is loaded into $t0 sw $t0, 8($s3) #$t0 is stored where? M230 L10.14 Smith Spring 2008

19 MIPS Memory Addressing The memory address is formed by summing the constant portion of the instruction and the contents of the second (base) register $s3 holds 8 Memory Data 0 Word Address lw $t0, 4($s3) #what? is loaded into $t0 sw $t0, 8($s3) #$t0 is stored where? in location 16 M230 L10.14 Smith Spring

20 MIPS Memory Addressing The memory address is formed by summing the constant portion of the instruction and the contents of the second (base) register $s3 holds Memory Data 0 Word Address lw $t0, 4($s3) #what? is loaded into $t0 sw $t0, 8($s3) #$t0 is stored where? in location 16 M230 L10.14 Smith Spring

21 Compiling with Loads and Stores Assuming variable b is stored in $s2 and that the base address of array A is in $s3, what is the MIPS assembly code for the C statement A[8] = A[2] - b... A[3] A[2] A[1] A[0]... $s3+12 $s3+8 $s3+4 $s3 M230 L10.16 Smith Spring 2008

22 Compiling with Loads and Stores Assuming variable b is stored in $s2 and that the base address of array A is in $s3, what is the MIPS assembly code for the C statement A[8] = A[2] - b... A[3] A[2] A[1] A[0]... $s3+12 $s3+8 $s3+4 $s3 lw $t0, 8($s3) sub $t0, $t0, $s2 sw $t0, 32($s3) M230 L10.16 Smith Spring 2008

23 Compiling with a Variable Array Index Assuming A is an array of 50 elements whose base is in register $s4, and variables b, c, and i are in $s1, $s2, and $s3, respectively, what is the MIPS assembly code for the C statement c = A[i] - b add $t1, $s3, $s3 #array index i is in $s3 add $t1, $t1, $t1 #temp reg $t1 holds 4*i M230 L10.18 Smith Spring 2008

24 Compiling with a Variable Array Index Assuming A is an array of 50 elements whose base is in register $s4, and variables b, c, and i are in $s1, $s2, and $s3, respectively, what is the MIPS assembly code for the C statement c = A[i] - b add $t1, $s3, $s3 #array index i is in $s3 add $t1, $t1, $t1 #temp reg $t1 holds 4*i add $t1, $t1, $s4 #addr of A[i] lw $t0, 0($t1) sub $s2, $t0, $s1 M230 L10.18 Smith Spring 2008

25 Review: Unsigned Binary Representation Hex Binary Decimal 0x x bit weight 0x x x bit position bit 0x x x x x xFFFFFFFC 0xFFFFFFFD xFFFFFFFE 0xFFFFFFFF M230 L10.19 Smith Spring 2008

26 Review: Signed Binary Representation 2 sc binary decimal -2 3 = (2 3-1) = = M230 L10.20 Smith Spring 2008

27 Review: Signed Binary Representation 1010 complement all the bits 2 sc binary decimal -2 3 = (2 3-1) = = M230 L10.20 Smith Spring 2008

28 Review: Signed Binary Representation 1011 and add a complement all the bits 2 sc binary decimal -2 3 = (2 3-1) = = M230 L10.20 Smith Spring 2008

29 Machine Language - Arithmetic Instruction Instructions, like registers and words of data, are also 32 bits long Example: add $t0, $s1, $s2 registers have numbers $t0=$8, $s1=$17, $s2=$18 Instruction Format: op rs rt rd shamt funct Can you guess what the field names stand for? M230 L10.22 Smith Spring 2008

30 Machine Language - Arithmetic Instruction Instructions, like registers and words of data, are also 32 bits long Example: add $t0, $s1, $s2 registers have numbers $t0=$8, $s1=$17, $s2=$18 Instruction Format: op rs rt rd shamt funct Can you guess what the field names stand for? M230 L10.22 Smith Spring 2008

31 Machine Language - Arithmetic Instruction Instructions, like registers and words of data, are also 32 bits long Example: add $t0, $s1, $s2 registers have numbers $t0=$8, $s1=$17, $s2=$18 Instruction Format: op rs rt rd shamt funct Can you guess what the field names stand for? M230 L10.22 Smith Spring 2008

32 Machine Language - Arithmetic Instruction Instructions, like registers and words of data, are also 32 bits long Example: add $t0, $s1, $s2 registers have numbers $t0=$8, $s1=$17, $s2=$18 Instruction Format: op rs rt rd shamt funct Can you guess what the field names stand for? M230 L10.22 Smith Spring 2008

33 Machine Language - Arithmetic Instruction Instructions, like registers and words of data, are also 32 bits long Example: add $t0, $s1, $s2 registers have numbers $t0=$8, $s1=$17, $s2=$18 Instruction Format: op rs rt rd shamt funct Can you guess what the field names stand for? M230 L10.22 Smith Spring 2008

34 MIPS Instruction Fields op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits = 32 bits op rs rt rd shamt funct M230 L10.24 Smith Spring 2008

35 MIPS Instruction Fields op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits = 32 bits op opcode indicating operation to be performed rs rt rd shamt funct M230 L10.24 Smith Spring 2008

36 MIPS Instruction Fields op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits = 32 bits op rs rt opcode indicating operation to be performed address of the first register source operand rd shamt funct M230 L10.24 Smith Spring 2008

37 MIPS Instruction Fields op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits = 32 bits op rs rt opcode indicating operation to be performed address of the first register source operand address of the second register source operand rd shamt funct M230 L10.24 Smith Spring 2008

38 MIPS Instruction Fields op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits = 32 bits op rs rt rd opcode indicating operation to be performed address of the first register source operand address of the second register source operand the register destination address shamt funct M230 L10.24 Smith Spring 2008

39 MIPS Instruction Fields op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits = 32 bits op rs rt rd shamt funct opcode indicating operation to be performed address of the first register source operand address of the second register source operand the register destination address shift amount (for shift instructions) M230 L10.24 Smith Spring 2008

40 MIPS Instruction Fields op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits = 32 bits op rs rt rd shamt funct opcode indicating operation to be performed address of the first register source operand address of the second register source operand the register destination address shift amount (for shift instructions) function code that selects the specific variant of the operation specified in the opcode field M230 L10.24 Smith Spring 2008

41 Machine Language - Load Instruction Consider the load-word and store-word instructions, What would the regularity principle have us do? New principle: Good design demands a compromise Introduce a new type of instruction format I-type for data transfer instructions previous format was R-type for register Example: lw $t0, 24($s2) op rs rt 16 bit number Where's the compromise? M230 L10.26 Smith Spring 2008

42 Machine Language - Load Instruction Consider the load-word and store-word instructions, What would the regularity principle have us do? New principle: Good design demands a compromise Introduce a new type of instruction format I-type for data transfer instructions previous format was R-type for register Example: lw $t0, 24($s2) op rs rt 16 bit number Where's the compromise? M230 L10.26 Smith Spring 2008

43 Machine Language - Load Instruction Consider the load-word and store-word instructions, What would the regularity principle have us do? New principle: Good design demands a compromise Introduce a new type of instruction format I-type for data transfer instructions previous format was R-type for register Example: lw $t0, 24($s2) op rs rt 16 bit number Where's the compromise? M230 L10.26 Smith Spring 2008

44 Machine Language - Load Instruction Consider the load-word and store-word instructions, What would the regularity principle have us do? New principle: Good design demands a compromise Introduce a new type of instruction format I-type for data transfer instructions previous format was R-type for register Example: lw $t0, 24($s2) op rs rt 16 bit number Where's the compromise? M230 L10.26 Smith Spring 2008

45 Machine Language - Load Instruction Consider the load-word and store-word instructions, What would the regularity principle have us do? New principle: Good design demands a compromise Introduce a new type of instruction format I-type for data transfer instructions previous format was R-type for register Example: lw $t0, 24($s2) op rs rt 16 bit number Where's the compromise? M230 L10.26 Smith Spring 2008

46 Memory Address Location Example: lw $t0, 24($s2) $s2 = Memory 0xf f f f f f f f 0x $s2 0x Note that the offset can be positive or negative data 0x c 0x x x word address (hex) M230 L10.28 Smith Spring 2008

47 Memory Address Location Example: lw $t0, 24($s2) $s2 = Memory 0xf f f f f f f f = 0x120040ac 0x $s2 0x Note that the offset can be positive or negative data 0x c 0x x x word address (hex) M230 L10.28 Smith Spring 2008

48 Machine Language - Store Instruction Example: sw $t0, 24($s2) op rs rt 16 bit number A 16-bit address means access is limited to memory locations within a region of ±2 13 or 8,192 words (±2 15 or 32,768 bytes) of the address in the base register $s2 M230 L10.30 Smith Spring 2008

49 Machine Language - Store Instruction Example: sw $t0, 24($s2) op rs rt 16 bit number A 16-bit address means access is limited to memory locations within a region of ±2 13 or 8,192 words (±2 15 or 32,768 bytes) of the address in the base register $s2 M230 L10.30 Smith Spring 2008

50 Machine Language - Store Instruction Example: sw $t0, 24($s2) op rs rt 16 bit number A 16-bit address means access is limited to memory locations within a region of ±2 13 or 8,192 words (±2 15 or 32,768 bytes) of the address in the base register $s2 M230 L10.30 Smith Spring 2008

51 Machine Language - Store Instruction Example: sw $t0, 24($s2) op rs rt 16 bit number A 16-bit address means access is limited to memory locations within a region of ±2 13 or 8,192 words (±2 15 or 32,768 bytes) of the address in the base register $s2 M230 L10.30 Smith Spring 2008

52 Machine Language - Store Instruction Example: sw $t0, 24($s2) op rs rt 16 bit number A 16-bit address means access is limited to memory locations within a region of ±2 13 or 8,192 words (±2 15 or 32,768 bytes) of the address in the base register $s2 M230 L10.30 Smith Spring 2008

53 Review: MIPS Organization Arithmetic instructions to/from the register file Load/store word and byte instructions from/to memory Processor Memory src1 addr src2 addr dst addr write data Exec Fetch Register File 32 registers ($zero - $ra) Decode 32 bits src1 data src2 data read/write addr 32 read data 32 write data ALU byte address (big Endian) 32 bits words word address (binary) M230 L10.31 Smith Spring 2008

Announcements HW1 is due on this Friday (Sept 12th) Appendix A is very helpful to HW1. Check out system calls

Announcements HW1 is due on this Friday (Sept 12 th ) Appendix A is very helpful to HW1. Check out system calls on Page A-48. Ask TA (Liquan chen: liquan@ece.rutgers.edu) about homework related questions.