Announcements. Midterm 2 next Thursday, 6-7:30pm, 277 Cory Review session on Tuesday, 6-7:30pm, 277 Cory Homework 8 due next Tuesday Labs: project

Transcription

1 - Fall 2002 Lecture 20 Synthesis Sequential Logic Announcements Midterm 2 next Thursday, 6-7:30pm, 277 Cory Review session on Tuesday, 6-7:30pm, 277 Cory Homework 8 due next Tuesday Labs: project» Teams (of 2) should sign up in the next lab session» Should also select the adder tree and circuit style by this week. 1

2 Today s Lecture esign flows HLs and synthesis Sequential logic Hardware escription Languages 2

3 Implementation Approaches igital Circuit Implementation Approaches Custom Semicustom Cell-based Array-based Standard Cells Compiled Cells Macro Cells Pre-diffused (Gate Arrays) Pre-wired (FPGA's) Productivity Trends 10,000,000 10,000 1,000,000 1, , , , Logic Tr./Chip Tr./Staff Month. x x x x x x x x 58%/Yr. compounded Complexity growth rate 21%/Yr. compound Productivity growth rate 100,000,000 10,000,000 1,000, ,000 10,000 1, Complexity Logic Transistor per Chip (M) Productivity (K) Trans./Staff - Mo. Source: Sematech Complexity outpaces design productivity 3

4 Levels of Abstraction Moving the level of abstraction:» Materials and devices» Transistor-level circuits» Logic gates» Logic blocks The design and simulation followed:» 1-, 2-, 3- Poisson solvers» SPICE» Gate-level delay models Moving Levels of Abstraction esign so far was bottom-up Logic blocks can be also designed top-down Hardware escription Languages (HL)» VHL» Verilog Levels of description» Gate-level functionality» Logic/function level» Behavior-level 4

5 Synthesis Tasks Architectural Level Logic Level Circuit Level Structural View Behavioral View (i: 1..16) :: sum 5 sum*z -1 + coeff[i]*ln*z -1 mem * fsm Architecture Synthesis a b state > c Logic Synthesis x a b A A t c p B 2 2 B 2 2 x Circuit Synthesis F Hardware escription Languages VHL» Originated by ARPA in early 1980s» IEEE standard in 1987 Verilog» Created by Gateway esign Automation in 1985» Later bought by Cadence» IEEE standard in 1995 We will use Verilog for compatibility with EECS 150 5

6 Verilog Similarity to C: Verilog variables parameters procedures control (if, case) C wires/regs ports modules control (if, case) Simple Example AOI gate // AOI gate module AOI (A, B, C, F); input A, B, C; output F; assign F = ~((A & B) C); endmodule module module declaration input, output ports assign concurrent assignment 6

7 Wires vs. Ports module AOI (A, B, C, F); input A, B, C; output F; wire F; wire, E; assign AB = A & B; assign E = AB C; assign F = ~E; endmodule Combinational Logic Examples:» Boolean: assign g = ~(a & b);» Arithmetic:assign sum[32:0] = a[31:0] + b[31:0];» Relational:assign gt = (a > b); Assign statements are evaluated on changes of any operands 7

8 Sequential Logic Implemented using reg and always Example: reg Q; wire ; clk) Q = Executes on every rising edge of the clock Use of HL escribing digital systems:» atapaths» Finite-state machines This description can be:» Simulated» Used to verify some other design» Synthesized 8

9 esign Synthesis ASIC flow: esign Capture Behavioral Pre-Layout Simulation HL Logic Synthesis Structural esign Iteration Post-Layout Simulation Floorplanning Placement Physical Circuit Extraction Routing Tape-out esign Synthesis Logic synthesis ( front end )» Mapping into logic gates Physical design ( back end )» Placement and routing Requires a library of standard cells» Each cell has a logical, physical, timing information esign constraints 9

10 Synthesized esign 8x8 multiplier in standard cell technology Custom and Semi-Custom esigns Synthesis does not always produce perfect results Place and route tools do not know designer s intention» They see a list of logic gates, not an adder or memory structure Placement is determined based on some algorithm, and it is usually suboptimal Results in increased wiring: loss of performance, extra power, area. 10

11 Custom esigns Appropriate for memories, arrays and datapaths atapaths are bit sliced ata flows horizontally, control flows vertically Sequential Logic 11

12 Sequential Logic Inputs Current State COMBINATIONAL LOGIC Registers Q Outputs Next state 2 storage mechanisms positive feedback charge-based Positive Feedback: Bi-Stability V i1 V o1 = V i2 V o2 V o1 V i2 5 V o1 V o2 = V i1 V i1 V o2 V i2 5 V o1 A C B V i1 5 V o2 12

13 Meta-Stability V i2 5 V o1 A V i2 5 V o1 A C C B B V d i1 5 V o2 V d i1 5 V o2 Gain should be larger than 1 in the transition region Mux-Based Latches Negative latch (transparent when = 0) Positive latch (transparent when = 1) 1 Q 0 Q 0 1 Q = Clk Q + Clk I n Q = Clk Q + Clk I n 13

14 Mux-Based Latch Q Mux-Based Latch Q M Q M NMOS only Non-overlapping clocks 14

15 Storage Mechanisms Static ynamic Q Q Pseudo-Static Latch 15