Job Posting (Aug. 19) ECE 425. ARM7 Block Diagram. ARM Programming. Assembly Language Programming. ARM Architecture 9/7/2017. Microprocessor Systems

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Hubert Lane
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Must know how to do C- level and ASM level programming/debug. Must have basic understanding of electrical interfacing of microcontroller into system level environment.

1 Job Posting (Aug. 19) ECE 425 Microprocessor Systems TECHNICAL SKILLS: Use software development tools for microcontrollers. Must have experience with verification test languages such as Vera, Specman, and their extensions. Must know VHDL or Verilog language and using synthesis tools. Must know how to do C- level and ASM level programming/debug. Must have basic understanding of electrical interfacing of microcontroller into system level environment. 1 2 ARM Programming ARM7 Block Diagram Programming Model ARM Assembly Language Instruction Execution Cycle 3 4 ARM Architecture Assembly Language Programming Why assembly language? Because it s better than machine language. Computers only work in binary. People find that difficult

2 Machine Language Try it in Hex Snipped of an ARM machine language program for adding the contents of memory locations h8094 and h8098, placing the result in location h809c. E59F1010 E59f0008 E E58F Still pretty much incomprehensible. Humans just don t think the way computers calculate. 7 8 Now in Assembly Language LDR R1, num1 LDR R0, num2 ADD R5, R1, R0 STR R5, num3 Still cryptic, but a huge improvement over machine code. Assembly Language Applications Limited data processing. Real-time control applications. Short to moderate sized programs. Applications where memory size and cost is critical. Applications involving more input/output or control than computing Common Assembly Tasks writing the code generator for a compiler booting the computer interrupts low-level locking code for multi-threaded programs writing code for machines where no compiler exists More Assembly Tasks the compiler cannot generate code that is efficient enough, or optimal the computer has very limited memory and the compiler cannot generate code that is small enough low-level access to architectural and processor features Modern Assembly Language Programming with the ARM Processor, Larry D. Pyeatt 2

3 Still More debugging writing the operating system SIMD instructions deeper understanding of the machine foundation for advanced topics such as microcode pipelining cache issues security 13 High Level Language Applications Long programs. Portable (able to run on more than one type of processor) programs. Programs that are expected to undergo many revisions. Applications where memory requirements are already large. Applications involving more computations than input/output functions or controls. 14 Practical Assembly Language Compilers Large PC applications are not done in assembler. Neither are smartphone aps, etc. Some routines in those aps may be in assembler. Great for control over I/O. Real time controls (embedded systems) are even now sometimes done in assembler. All computer engineers are expected to understand microprocessors at the register/assembler level. 15 Compilers translate high level languages to executable code. This means generating assembly code. Who writes compilers? Probably someone who knows assembly language really really well. 16 Last Week What: assembly language programming, processor architecture Why: useful in & of itself, gives deep understanding of machines How: This week and the rest of the semester. First 2/3 of semester will cover textbook material. If organization doesn t always seem to make sense, blame Hohl. 17 How Well Do You Need to Know it? A passing grade is earned when I m comfortable having you design my pacemaker. 18 3

4 Programming Model 30 general purpose registers Each 32 bits wide Only half are visible at any time Two banks, both are addressed as r0 r14 Switched automatically depending on operating mode Six status registers Only one used at a time A program counter (also called r15) 19 General Purpose Registers Well, mostly. R13 is the stack pointer. R14 is the link register (used for subroutine return address) Program Status Registers Jazelle State N Z C V Q JU n d e f i n e d f s x c Condition code flags N = Negative result from ALU Z = Zero result from ALU C = ALU operation Carried out V = ALU operation overflowed Sticky Overflow flag - Q flag Architecture 5TE/J only Indicates if saturation has occurred J bit Architecture 5TEJ only J = 1: Processor in Jazelle state I F T mode Interrupt Disable bits. I = 1: Disables the IRQ. F = 1: Disables the FIQ. T Bit Architecture xt only T = 0: Processor in ARM state T = 1: Processor in Thumb state Mode bits Specify the processor mode A mode in which some ARM processors natively execute Java byte code. No implications for this class. Does not apply to ARM7. Similar for Q flag. ARM7 has only standard, not sticky, overflow bit. 22 Programming Status Registers 32 bits, but only 12 are used. The rest are all zeros, can not be changed. 23 Basic Terminology Smallest unit used is a bit. Values of 1 or 0 Stored in a flipflop, latch, capacitor Four bits form a nibble (nybble). Two nibbles form a byte. Two bytes form a halfword. Two halfwords form a word. A register is an n-bit wide group of flipflops addressed as one unit. 24 4

5 Register Enable Registers, Accumulators Data In Enable Clock 2:1 Mux D Flip flop Data Out Earlier processors had only a small number of accumulators. Maybe only one ARM allows all machine registers to act as accumulators. Small RISC instruction set and load/store architecture means there is less that an accumulator has to be able to do What s an Accumulator, anyhow? Data Input Input Why Bother With It? ALU ALU Clock Accumulator Output Output 27 What would this do? 28 Shift Register Combinational Feedback FF1 FF2 FF3 FF4 CLK Data In A B C D E F G FF1 X A B C D E F FF2 X X A B C D E Time 29 Suppose the operation is A + Accumulator. But accumulator isn t latched: it s just the output of the ALU. Then, instead of adding A to whatever was already there, it performs a new add as soon as the old one propagates through the ALU. So time base and register enables are needed. 30 5

6 Index Registers ARM does not have dedicated registers for tracking data addresses. Any machine register can be indexed (incremented or decremented) automatically as part of list processing. ARM has only a few, simple addressing modes. Program Counter R15 is the Program Counter Standard 32 bit register dedicated to tracking position in program. Points to the location of the next instruction to fetched from memory. Contents of Program Counter is an address in memory, not an instruction. PC is automatically initialized to 0 at power on. After fetching an instruction, PC is automatically incremented or loaded with next address Stack Pointer Stack is an area in memory (RAM) for temporary storage of variables. Most common stack use: context switch Subroutines, interrupt service routines, switching user/task ARM uses R13 to keep track of stack position. ARM stack is flexible, user determines configuration. More on this later 33 Program Status Registers ARM has six, but only one is active at any given time. Others are for use by the inactive modes, become active when mode switches. Allows for faster switching between modes, reference a different register rather than load and store data. PSR has some bits that user sets, some bits the processor sets and the user reads. 34 Program Status Register Machine Sets, User Sets N Z C V No Write/Read As Zeros I F T M 4 M 3 M 2 M 1 M 0 Machine Sets: N Flag Z Flag C Flag V Flag T Bit User Sets: I bit F bit Mode bits* 35 *Mode bits can only be changed when already operating in a privileged mode. Executing certain instructions will automatically change the mode, as will the triggering of an interrupt. 36 6

7 Program Status Register Top four bits are used for program flow control. Bit 31: N bit, is set if result of previous op was a negative number. Bit 30: Z bit, set if result of previous op was 0. Bit 29: C bit, set if previous op had a carry out. Bit 28: V bit, set if previous op resulted in overflow. 37 Condition Code Flags These four bits are the Condition Code Flags. Almost all program flow decisions are made based on their status. Not all instructions can change them. Examples: Add instruction can set/reset all four bits Boolean ops never change V bit Data store does not change any flags Flags only change when an S is appended to the instruction. 38 S Bit Instructions will only update the CPSR flags if the S bit (bit 20) is set. You set this in your assembly language code by adding an S to the instruction. Example: ADD r0, r1, r2; no flag change ADDS r0, r1, r2; set flags according to result Flag Condition Flags Logical Instruction Arithmetic Instruction N No Meaning Bit 31 has been set Z Result is all zeros Result of operation was zero C After shift, 1 was left in Carry Flag Result was greater than 32 bits V No Meaning Result was greater than 31 bits: possible sign corruption Conditional Execution ARM processors have an addition trick using conditional codes. Instructions may include them for provisional execution when time permits Out of order execution keeps pipelines and functional units busy, increases performance To be covered later. I, F Bits I and F bits enable, disable external interrupts. ARM has two: FIQ, Fast interrupt request Higher priority than IRQ IRQ, Interrupt request

8 T bit Used to tell processor that instructions are in T (Thumb) mode. T = 1 means Thumb mode. 16-bit instruction set, allows for more compact assembled code. Some limitations, not all ARM instructions can be run in Thumb mode. Used to minimize system cost, for cheap embedded applications. 43 Set/Reset T Bit T bit set or cleared when a special Branch Exchange (BX) instruction is run. T bit takes status of LSB of the register that holds branch address. If it is one, operation will be in Thumb mode. If it is zero, operation will be in normal ARM mode. Rest of register (bits 31:1) hold address of branch routine. 44 Mode Bits Five bits, but only seven modes are currently implemented. Processor Modes The ARM has seven basic operating modes: User : unprivileged mode under which most tasks run FIQ : entered when a high priority (fast) interrupt is raised PSR Bits [4:0] Mode User Mode FIQ Mode IRQ Mode Supervisor Mode Abort Undefined mode System Mode 45 IRQ : entered when a low priority (normal) interrupt is raised Supervisor : entered on reset and when a Software Interrupt instruction is executed Abort : used to handle memory access violations Undef : used to handle undefined instructions System : privileged mode using the same registers as user mode ARM Assembly Language Assembly vs. C Label Op-Code Destination Operands(s) start ADD R0, R1,R2 ; comment Label: name for a memory location Op-Code: mnemonic, action part of instruction Destination: machine register were result will be stored Operand: source of data Comment: ; indicates comment follows can also be used at the beginning of a line C: more readable Top-Down Design more efficient programming do not need to know HW details Assembly Faster Smaller Better for hardware control

9 Instruction Execution Cycle ARM Pipeline fetch execute decode Stage Bottleneck ARM7 uses a three-stage pipeline. This leads to a memory access bottleneck. Many instructions need to access memory. Read or write operand in addition to instruction fetch. Higher performance machines increase pipeline depth and separate data and instruction memories. Substantially increases hardware complexity, adds data forwarding paths, etc. 51 Deeper Pipelines ARM7 has three stage pipeline. Deeper pipelines allow faster clock cycle. ARM9 has five deep pipeline. Instruction fetch Decode Execute Data fetch (buffer if not needed) Write back 52 Homework 1 Homework 1 is on the web site Due a week from now Program Run Time Fundamental performance equation: T prog = N inst x CPI f clk Time to execute a program is the number of instructions in the program times the average number of clock cycles per instruction divided by the clock frequency

Pipeline Operation Instruction Pipeline 55 56 Pipelines Speed Operation Pipelining allows operations to overlap.

With pipelining, the sequence can be completed in five. 57 It Gets Complicated Pipelining works great as long as all instructions are in order.

10 Pipeline Operation Instruction Pipeline Pipelines Speed Operation Pipelining allows operations to overlap. Suppose Fetch Decode and Execute each take one clock cycle (unrealistically optimistic). Without pipelining, three instructions would take nine cycles. With pipelining, the sequence can be completed in five. 57 It Gets Complicated Pipelining works great as long as all instructions are in order. But what if one instruction says to go one place if the result of an operation is 0, someplace else if it is 1, etc? Then the wrong instruction may have been fetched and decoded. Leads to pipeline flush, which slows things down

William Stallings Computer Organization and Architecture 8 th Edition. Chapter 12 Processor Structure and Function

William Stallings Computer Organization and Architecture 8 th Edition Chapter 12 Processor Structure and Function CPU Structure CPU must: Fetch instructions Interpret instructions Fetch data Process data