! Replace maxterm OR gates with NOR gates! Place compensating inversion at inputs of AND gate

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Bruce Matthews
6 years ago
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1 Two-level logic using NN gates (cont d) ELE 4 igital Electronics Week : ombinational Logic Implementation! OR gate with inverted inputs is a NN gate " de Morgan's: ' ' = ( )'! Two-level NN-NN network " inverted inputs are not counted " in a typical circuit, inversion is done once and signal distributed Saeid Nooshabadi ELE4 - ombinational Implementation - ELE4 - ombinational Implementation - ombinational logic implementation Two-level logic using gates! Two-level logic " implementations of two-level logic " NN/! Multi-level logic " factored forms " and-or-invert gates! Time behavior " gate delays " hazards! Regular logic " multiplexors " decoders " PL/PLs " ROMs! Replace maxterm OR gates with gates! Place compensating inversion at inputs of N gate ELE4 - ombinational Implementation - ELE4 - ombinational Implementation - Implementations of two-level logic Two-level logic using gates (cont d)! Sum-of-products " N gates to form product terms (minterms) " OR gate to form sum! N gate with inverted inputs is a gate " de Morgan's: ' ' = ( )'! Two-level - network " inverted inputs are not counted " in a typical circuit, inversion is done once and signal distributed! Product-of-sums " OR gates to form sum terms (maxterms) " N gates to form product ELE4 - ombinational Implementation - ELE4 - ombinational Implementation - Two-level logic using NN gates Two-level logic using NN and gates! Replace minterm N gates with NN gates! Place compensating inversion at inputs of OR gate! NN-NN and - networks " de Morgan's law: ( )' = ' ' ( )' = ' ' " written differently: = (' ')' ( ) = (' ')'! In other words " OR is the same as NN with complemented inputs " N is the same as with complemented inputs " NN is the same as OR with complemented inputs " is the same as N with complemented inputs OR OR N N NN NN ELE4 - ombinational Implementation - 4 ELE4 - ombinational Implementation - 8

2 onversion between forms Multi-level logic! onvert from networks of Ns and ORs to networks of NNs and s " introduce appropriate inversions ("bubbles")! Each introduced "bubble" must be matched by a corresponding "bubble" " conservation of inversions " do not alter logic function! Example: N/OR to NN/NN! x = E E E G " reduced sum-of-products form already simplified " x -input N gates x -input OR gate (that may not even exist!) " wires (9 literals plus internal wires)! x = ( ) ( E) G " factored form not written as two-level S-o-P " x -input OR gate, x -input OR gates, x -input N gate " wires ( literals plus internal wires) NN NN NN E G ELE4 - ombinational Implementation - 9 ELE4 - ombinational Implementation - onversion between forms (cont d) onversion of multi-level logic to NN gates! Example: verify equivalence of two forms NN NN NN! = ( ) ' original N-OR network introduction and conservation of bubbles \ \ Level Level Level Level 4 = [ ( )' ( )' ]' = [ (' ') (' ') ]' = [ (' ')' (' ')' ] = ( ) ( ) # redrawn in terms of conventional NN gates \ \ ELE4 - ombinational Implementation - ELE4 - ombinational Implementation - 4 onversion between forms (cont d) onversion of multi-level logic to s! Example: map N/OR network to / network conserve "bubbles" Step \ \ \ \ Step conserve "bubbles"! = ( ) ' introduction and conservation of bubbles original N-OR network \ redrawn in terms of conventional gates \ \ \ \ \ Level Level Level Level 4 ELE4 - ombinational Implementation - ELE4 - ombinational Implementation - onversion between forms (cont d) onversion between forms! Example: verify equivalence of two forms! Example \ \ \ \ = { [ (' ')' (' ')' ]' }' = { (' ') (' ') }' = (' ')' (' ')' = ( ) ( ) # (a) (c) \ original circuit \ distribute bubbles some mismatches \ add double bubbles at inputs \ insert inverters to fix mismatches (b) (d) ELE4 - ombinational Implementation - ELE4 - ombinational Implementation -

3 N-OR-invert gates Summary for multi-level logic! OI function: three stages of logic N, OR, Invert " multiple gates "packaged" as a single circuit block logical concept possible implementation! dvantages " circuits may be smaller " gates have smaller fan-in " circuits may be faster! isadvantages " more difficult to design " tools for optimization are not as good as for two-level " analysis is more complex N OR Invert NN NN Invert x OI gate symbol x OI gate symbol ELE4 - ombinational Implementation - ELE4 - ombinational Implementation - onversion to OI forms MINISTRTIVE (/)! General procedure to place in OI form " compute the complement of the function in sum-of-products form " by grouping the s in the Karnaugh map! Example: OR implementation xor = ' ' " OI form: = (' ' )' ' '! istributed Handouts: "irst day Handout "Laboratory Information "Tutorial # "Laboratory #! If you haven t got them get it off the website or from the lab! uture Laboratory handouts can only be collected from the lab/website! Tutorial handouts will be provided in the class. lso available from the website/lab. ELE4 - ombinational Implementation - 8 ELE4 - ombinational Implementation - Examples of using OI gates MINISTRTIVE (/)! Example: " = ' ' " ' = ' ' ' ' " Implemented by -input -stack OI gate " = ( ) ( ') ( ') " ' = (' ) (' ) (' ') " Implemented by -input -stack OI gate! Example: 4-bit equality function " = ( ' ')( ' ')( ' ')( ' ') each implemented in a single x OI gate ELE4 - ombinational Implementation - 9! Lecture Slides are available in "PowerPoint format, "P ( slides a page) "P (4 slides a page) as well! heck website to see your lab allocation! Laboratory starts on week # for Odd groups and week #4 for Even groups! o your Lab Enrolment if you haven t done so yet.! You will not be allowed in the lab if you have not enrolled "8 Students are enrolled in the course "8 Students are enrolled in the lab " yet to enroll in the laboratory ELE4 - ombinational Implementation - Examples of using OI gates (cont d) Time behavior of combinational networks! Example: OI implementation of 4-bit equality function high if low if = conservation of bubbles if all inputs are low then i = i, i=,..., output is high! Waveforms " visualization of values carried on signal wires over time " useful in explaining sequences of events (changes in value)! Simulation tools are used to create these waveforms " input to the simulator includes gates and their connections " input stimulus, that is, input signal waveforms! Some terms " gate delay time for change at input to cause change at output min delay typical/nominal delay max delay careful designers design for the worst case " rise time time for output to transition from low to high voltage " fall time time for output to transition from high to low voltage " pulse width time that an output stays high or stays low between changes ELE4 - ombinational Implementation - ELE4 - ombinational Implementation - 4

4 Momentary changes in outputs Static hazards! an be useful pulse shaping circuits! an be a problem incorrect circuit operation (glitches/hazards)! Example: pulse shaping circuit " ' = " delays matter in function! ue to a literal and its complement momentarily taking on the same value " through different paths with different delays and reconverging! May cause an output that should have stayed at the same value to momentarily take on the wrong value! Example: multiplexer S S remains high for three gate delays after changes from low to high is not always pulse gate-delays wide S' static- hazard S' static- hazard hazard ELE4 - ombinational Implementation - ELE4 - ombinational Implementation - 9 Oscillatory behavior ynamic hazards! nother pulse shaping circuit close switch initially undefined open switch open switch resistor! ue to the same versions of a literal taking on opposite values " through different paths with different delays and reconverging! May cause an output that was to change value to change times instead of once! Example: hazard dynamic hazards ELE4 - ombinational Implementation - ELE4 - ombinational Implementation - Hazards/glitches Making connections! Hazards/glitches: unwanted switching at the outputs " occur when different paths through circuit have different propagation delays as in pulse shaping circuits we just analyzed " dangerous if logic causes an action while output is unstable may need to guarantee absence of glitches! Usual solutions " ) wait until signals are stable (by using a clock) preferable (easiest to design when there is a clock synchronous design) " ) design hazard-free circuits sometimes necessary (clock not used asynchronous design)! irect point-to-point connections between gates " wires we've seen so far! Route one of many inputs to a single output --- multiplexer! Route a single input to one of many outputs --- demultiplexer control control multiplexer demultiplexer 4x4 switch ELE4 - ombinational Implementation - ELE4 - ombinational Implementation - Types of hazards Mux and de! Static -hazard " input change causes output to go from to to! Switch implementation of multiplexers and demultiplexers " can be composed to make arbitrary size switching networks " used to implement multiple-source/multiple-destination interconnections! Static -hazard " input change causes output to go from to to Y! ynamic hazards " input change causes a double change from to to to OR from to to to Y ELE4 - ombinational Implementation - 8 ELE4 - ombinational Implementation -

5 Mux and de (cont'd) ascading multiplexers! Uses of multiplexers/demultiplexers in multi-point connections Sa MU MU Sb multiple input sources Sum Ss EMU multiple output destinations S S ELE4 - ombinational Implementation -! Large multiplexers can be implemented by cascading smaller ones I I I I I4 I I I 4: 4: control signals and simultaneously choose one of I, I, I, I and one of I4, I, I, I control signal chooses which of the upper or lower 's output to gate to 8: : I I I I I4 I I I ELE4 - ombinational Implementation - : : : : alternative implementation 4: 8: Multiplexers/selectors Multiplexers as general-purpose logic! Multiplexers/selectors: general concept " n data inputs, n control inputs (called "selects"), output " used to connect n points to a single point " control signal pattern forms binary index of input connected to output = ' I I functional form logical form I I two alternative forms for a : Mux truth table I I! n : multiplexer can implement any function of n variables " with the variables used as control inputs and " the data inputs tied to or " in essence, a lookup table! Example: " (,,) = m m m m = ''' '' ' 4 8: MU S S S ELE4 - ombinational Implementation - 4 ELE4 - ombinational Implementation - 8 Multiplexers/selectors (cont'd) Multiplexers as general-purpose logic (cont d)! : : = ' I I! 4: : = ' ' I ' I ' I I! 8: : = ' ' ' I ' ' I ' ' I ' I ' ' I4 ' I ' I I n -! In general, = Σ (m k= k I k ) " in minterm shorthand form for a n : Mux I I : I I I I 4: I I I I I4 I I I 8:! n- : multiplexer can implement any function of n variables " with n- variables used as control inputs and " the data inputs tied to the last variable or its complement! Example: " (,,) = m m m m (' ) = ''' '' ' = ''(') '(') '() () 4 8: MU S S S ' ' ' ' 4: MU S S ELE4 - ombinational Implementation - ELE4 - ombinational Implementation - 9 Gate level implementation of es Multiplexers as general-purpose logic (cont d)! :! 4: n- control variables single data variable I I... I n- I n I n- I n- ' four possible configurations of truth table rows can be expressed as a function of I n ELE4 - ombinational Implementation - choose,, as control variables multiplexer implementation ELE4 - ombinational Implementation : MU S S S

6 emultiplexers/decoders ascading decoders! ecoders/demultiplexers: general concept " single data input, n control inputs, n outputs " control inputs (called selects (S)) represent binary index of output to which the input is connected " data input usually called enable (G) : ecoder: O = G S O = G S :4 ecoder: O = G S S O = G S S O = G S S O = G S S :8 ecoder: O = G S S S O = G S S S O = G S S S O = G S S S O4 = G S S S O = G S S S O = G S S S O = G S S S! : decoder " x:4 decoder " 4x:8 decoders :4 E S S ''''E' :8 E 4 S S S :8 E 4 E S S S E :8 E 4 S S S ''E' '''E' :8 E 4 'E S S S E ELE4 - ombinational Implementation - 4 ELE4 - ombinational Implementation - 4 Gate level implementation of demultiplexers MINISTRTIVE! : decoders! :4 decoders active-high enable G S O O active-low enable \G S O O! Tutorial # handouts is avilable for collection at the end of the lecture.! Tomorrow s Session may be a Lecture Session, or Lecture Tutorial Session. G active-high enable O O \G active-low enable O O O O O O S S S S ELE4 - ombinational Implementation - 4 ELE4 - ombinational Implementation - 4 emultiplexers as general-purpose logic Programmable logic arrays! n: n decoder can implement any function of n variables " with the variables used as control inputs " the enable inputs tied to and " the appropriate minterms summed to form the function! Pre-fabricated building block of many N/OR gates " actually or NN " "personalized" by making or breaking connections among the gates " programmable array block diagram for sum of products form :8 E 4 S S S ''' '' '' ' '' ' ' demultiplexer generates appropriate minterm based on control signals (it "decodes" control signals) inputs N array product terms OR array outputs ELE4 - ombinational Implementation - 4 ELE4 - ombinational Implementation - 4 emultiplexers as general-purpose logic (cont d) Enabling concept! = ' ' ' '! = '! = ' ( ) =! = (' ' ' ')! = ( )' Enable 4: E '''' ''' ''' '' 4 ''' '' '' ' 8 ''' 9 '' '' ' '' ' 4 '! Shared product terms among outputs example: personality matrix = ' ' = ' = ' ' = ' product inputs outputs term ' ' '' input side: = uncomplemented in term = complemented in term = does not participate output side: = term connected to output = no connection to output reuse of terms ELE4 - ombinational Implementation - 44 ELE4 - ombinational Implementation - 48

7 efore programming PLs and PLs! ll possible connections are available before "programming" " in reality, all N and OR gates are NNs! Programmable logic array (PL) " what we've seen so far " unconstrained fully-general N and OR arrays! Programmable array logic (PL) " constrained topology of the OR array " innovation by Monolithic Memories " faster and smaller OR plane a given column of the OR array has access to only a subset of the possible product terms ELE4 - ombinational Implementation - 49 ELE4 - ombinational Implementation - fter programming PLs and PLs: design example! Unwanted connections are "blown" " fuse (normally connected, break unwanted ones) " anti-fuse (normally disconnected, make wanted connections) ' ' ''! to Gray code converter W Y minimized functions: W = = ' Y = = ''' ' ' ' K-map for W K-map for Y K-map for K-map for ELE4 - ombinational Implementation - ELE4 - ombinational Implementation - 4 lternate representation for high fan-in structures PLs and PLs: design example (cont d)! Short-hand notation so we don't have to draw all the wires " signifies a connection is present and perpendicular signal is an input to gate ELE4 - ombinational Implementation - notation for implementing = ' ' = ' ' '' '' '' ' '! ode converter: programmed PL W Y ' ''' ' ' ELE4 - ombinational Implementation - minimized functions: W = = ' Y = = ''' ' ' ' not a particularly good candidate for PL/PL implementation since no terms are shared among outputs however, much more compact and regular implementation when compared with discrete N and OR gates Programmable logic array example PLs and PLs: design example (cont d)! Multiple functions of,, " = " = " = ' ' ' " 4 = ' ' ' " = xor xor " = xnor xnor 4 ELE4 - ombinational Implementation - full decoder as for memory address bits stored in memory 4 ''' '' '' ' '' ' '! ode converter: programmed PL 4 product terms per each OR gate ELE4 - ombinational Implementation - W Y ' ''' ' ''

8 PLs and PLs: design example (cont d) ROM structure! ode converter: NN gate implementation " loss or regularity, harder to understand " harder to make changes! Similar to a PL structure but with a fully decoded N array " completely flexible OR array (unlike PL) W \ \ \ n address lines inputs decoder n word lines memory array ( n words by m bits) outputs Y m data lines ELE4 - ombinational Implementation - ELE4 - ombinational Implementation - PLs and PLs: another design example ROM vs. PL! Magnitude comparator K-map for EQ K-map for NE '''' '' '' ' ' ' ' '' ' ''! ROM approach advantageous when " design time is short (no need to minimize output functions) " most input combinations are needed (e.g., code converters) " little sharing of product terms among output functions! ROM problems " size doubles for each additional input " can't exploit don't cares! PL approach advantageous when " design tools are available for multi-output minimization " there are relatively few unique minterm combinations " many minterms are shared among the output functions! PL problems " constrained fan-ins on OR plane K-map for LT K-map for GT ELE4 - ombinational Implementation - 8 EQ NE LT GT ELE4 - ombinational Implementation - Read-only memories Regular logic structures for two-level logic! Two dimensional array of s and s " entry (row) is called a "word" " width of row = word-size " index is called an "address" " address is input " selected word is output n - internal organization decoder n- ddress i j word lines (only one is active decoder is just right for this) word[i] = word[j] = bit lines (normally pulled to through resistor selectively connected to by word line controlled switches)! ROM full N plane, general OR plane " cheap (high-volume component) " can implement any function of n inputs " medium speed! PL programmable N plane, fixed OR plane " intermediate cost " can implement functions limited by number of terms " high speed (only one programmable plane that is much smaller than ROM's decoder)! PL programmable N and OR planes " most expensive (most complex in design, need more sophisticated tools) " can implement any function up to a product term limit " slow (two programmable planes) ELE4 - ombinational Implementation - 9 ELE4 - ombinational Implementation - ROMs and combinational logic Regular logic structures for multi-level logic! ombinational logic implementation (two-level canonical form) using a ROM truth table = ' ' ' ' ' = ' ' ' ' = ' ' ' ' ' ' ' = ' ' ' ' ROM 8 words x 4 bits/word address outputs block diagram! ifficult to devise a regular structure for arbitrary connections between a large set of different types of gates " efficiency/speed concerns for such a structure " in 4 you'll learn about field programmable gate arrays (PGs) that are just such programmable multi-level structures programmable multiplexers for wiring lookup tables for logic functions (programming fills in the table) multi-purpose cells (utilization is the big issue)! Use multiple levels of PLs/PLs/ROMs " output intermediate result " make it an input to be used in further logic ELE4 - ombinational Implementation - ELE4 - ombinational Implementation - 4

9 ombinational logic implementation summary! Multi-level logic " conversion to NN-NN and - networks " transition from simple gates to more complex gate building blocks " reduced gate count, fan-ins, potentially faster " more levels, harder to design! Time response in combinational networks " gate delays and timing waveforms " hazards/glitches (what they are and why they happen)! Regular logic " multiplexers/decoders " ROMs " PLs/PLs " advantages/disadvantages of each ELE4 - ombinational Implementation -

Chapter 3 working with combinational logic

Chapter 3 working with combinational logic hapter 3 working with combinational logic ombinational Logic opyright 24, Gaetano orriello and Randy H. Katz Working with combinational logic Simplification two-level simplification exploiting don t cares