ECE UMass, Amherst. Verilog tutorial

Transcription

1 ECE UMass, Amherst Verilog tutorial 1. In this tutorial, we are going to design and implement a 2-bit comparator in Verilog and simulate it using the service provided on In the following, you could find the step by step description of the design, implementation and simulation: (a) Design of a single bit comparator The comparator we are designing here, is a simple equality comparator. It has 2 inputs: a and b and 1 output: eq. The output is asserted (gets the value of 1) when a is equal to b. Otherwise, it is 0. As you recall, the functionality of 2- input XOR gate is very similar but with different polarity (the output is 0 when inputs are equal and it is 1 when inputs are not equal). So if using an Inverter gate we change the polarity of the output, it would work exactly the same way as the comparator does. The gate level design of such comparator is shown in Fig.??. Since we are going to describe this design in Verilog, we need to name every single entity in the design. That is why, we have named the XOR gate as g1 and the Inverter gate as g2. Another point worth mentioning is that since we need to connect the input of the Inverter to the output of the XOR, we need a connection. That s why we also named the connection between them (here w). Now, we are ready to describe this module int Verilog. (b) Implementation of the comparator in Verilog For this part, you need to go to the website, The layout of the website is shown in Fig.??. On the right hand side of the page, we could enter the Verilog code of our comparator. On the first line, we should describe the way our module looks like from outside world. Using module keyword,

2 Figure 1: Design of a single bit comparator Figure 2: Verilog code describing the comparator Figure 3: Layout of the page 2

3 we name our module (here we name it CMP) and in a pair of parentheses, we name the ports of the module (here, a, b, and eq). After that, we should define the direction of each port which has been done on lines 3 and 4. After that, we need to define the intermediate signals if needed (here we need to define w). If those signals get assigned in concurrent body of the module, they should be defined as wire, otherwise, they should be defined as reg. After defining the intermediate signals, it s time to instantiate our gates or other building blocks of our design. Here, we just used XOR and NOT primitive gates of Verilog. After specifying the type of each gate, we named them and in a pair of parentheses we defined their port connections. In all Verilog primitive gates, the first port is assigned to the output of the gate and the rest are assigned to the inputs. Finally, we finish the description of our module by using endmodule keyword. The Verilog code describing the comparator is shown if Fig.?? (c) Development of the testbench When we are done with the design, it s time to test it in a simulation environment. To do so, we need to develop a testbench. A testbench is also a module which has no ports. It just instantiates other modules inside it and applies the stimulus to their inputs to observe their behavior in terms of their outputs. In the testbench, we need to define 3 signals to connect to the ports of our comparator. Since we are going to change the value of the inputs of the instantiated module in a sequential manner inside a sequential block, we need to define the signals connected to the inputs of the instantiated module as reg. For the output ports of the module, since the signals are just carrying the values, they need to be defined as wire. After defining the signals, we have to instantiate the module we want to test. Instantiating a user defined module is exactly the same as instantiating a Verilog primitive gate except for the port ordering which is as it is defined in the module definition 3

4 for user defined ones. Finally, it s time to apply the stimulus and check the outputs. We assign and change the values of the inputs in a sequential manner inside an initial block. Before applying the stimulus, we need to make the simulator to show the values of the signals in a visual form. In order to do so, we use $dumpfile ( dump.vcd ); and $dumpvars(1);. In order to assign a value to a signal, we use equal sign (=). After applying a set of test values (also known as test vector) we should wait for some time to see the outputs. Waiting is done using # followed by the time needed to wait. Here, after applying a new test vector to the inputs, we wait for 10ns before applying the next test vector. When dealing we edaplayground simulator, it draws the waveform until when the last assignment takes place which leaves us no time to see the outputs resulted from that input assignment. To address this issue, we always finish the testing by assigning some dummy values to the inputs. The Verilog code testing the comparator is shown in Fig.??. (d) Checking the waveform Now by clicking on the run button, we could see the simulation waveform and make sure our system is working as it is intended. The waveform extracted from simulation of the comparator is shown in Fig.??. As it can be seen, the output is equal to 1 whenever the inputs are equal and it is 0 otherwise. (e) Implementation of a 2-bit comparator Design of a 2-bit comparator is shown in Fig.??. As it can be seen, we instantiated two instances of the comparator developed in the previous parts. The inputs here are not single bits anymore. Instead they are 2-bit buses. Each comparator is checking the equality of a pair of bits from the inputs. The two numbers are equal if both pairs are equal. Hence, the output is generated by using an AND gate fed by the output of each comparator. (f) Verilog code for the 2-bit comparator The Verilog code, describing the 2-bit comparator in shown in 4

5 Figure 4: Testbench for testing the comparator module Figure 5: Testbench for testing the comparator module 5

6 Figure 6: Design of a 2-bit comparator Fig.??. Since it s instantiating the CMP module, it has to be defined in the same file as CMP is defined (this is not a restriction imposed by Verilog. It s imposed by edaplayground). Please note how we defined x and y. Having that [1:0] next to the wire keyword means that these signals are buses where the leftmost bit is indexed as 1 and the rightmost one is indexed as 0 (the width would be (left index - right index)+1) which is 2 in this case. (g) Simulation of the 2-bit comparator Testing the 2-bit comparator is the same as single bit one except for the stimulus. In the latter case, the stimulus should be defined as 2-bit buses. The testbench for the 2-bit comparator is shown in Fig.?? and the waveform of it is shown in Fig.??. 6

7 Figure 7: Verilog code for 2-bit comparator 7

8 Figure 8: Testbench for 2-bit comparator Figure 9: Waveform of 2-bit comparator s simulation 8