Review. LIBRARY list of library names; USE library.package.object; ENTITY entity_name IS generic declarations PORT ( signal_name(s): mode signal_type;
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1 LIBRARY list of library names; USE library.package.object; Review ENTITY entity_name IS generic declarations PORT ( signal_name(s): mode signal_type; signal_name(s) : mode signal_type); END ENTITY entity_name; ARCHITECTURE architecture_name OF entity_name IS type declarations signal declarations constant declarations function definitions procedure definitions component declarations BEGIN concurrent statement; concurrent statement; END ARCHITECTURE architecture_name;
2 Examples simple adders Half Adder in1 in1 in2 Cout sum + in Cout sum
3 Half Adder LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY half_adder is PORT (in1, in2 : IN STD_LOGIC; Sum, Cout : OUT STD_LOGIC); END ENTITY half_adder; ARCHITECTURE func OF half_adder IS BEGIN Cout <= in1 in2; Sum <= in1 in2; END ARCHITECTURE func;
4 Full Adder half adder plus carry in in1 in2 Cin Cout sum
5 Full Adder LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY fulladder IS PORT(in1, in2, Cin : IN STD_LOGIC; Sum, Cout : OUT STD_LOGIC); END ENTITY fulladder; ARCHITECTURE logicfunc OF fulladder IS BEGIN Sum <= Cout <= END ARCHITECTURE logicfunc;
6 Full Adder same library, same entity ARCHITECTURE logicfunc2 OF fulladder IS SIGNAL Cout1, Sum1, Cout2 : STD_LOGIC; BEGIN Cout1 <= in1 and in2; Sum1 <= in1 xor in2; Cout2 <= Sum1 and Cin; Sum <= Sum1 xor Cin; Cout <= Cout1 or Cout1; END ARCHITECTURE logicfunc2;
7 Components allow entity reuse Component declaration - defines component - placed in declaration section of architecture COMPONENT component_name IS PORT ( signal_name(s) : mode type; signal_name(s) : mode type); END COMPONENT component_name; to create a specific instance of the component label: component_name PORT MAP (s1,, sn);
8 - LIBRARY ieee; -- Full Adder from half adders USE ieee.std_logic_1164.all; ENTITY fulladder2 IS PORT( A, B, Cin : IN STD_LOGIC; Sum, Cout : OUT STD_LOGIC); END ENTITY fulladder2; ARCHITECTURE func3 OF fulladder2 IS SIGNAL Cout1, Cout2, Sum1 : STD_LOGIC; COMPONENT half_adder IS PORT( in1, in2 : IN STD_LOGIC; Sum, Cout : OUT STD_LOGIC); END COMPONENT half_adder; BEGIN ha1: half_adder PORT MAP (A, B, Sum1, Cout1); ha2: half_adder PORT MAP (Sum1, Cin, Sum, Cout2); Cout <= Cout1 OR Cout2; END ARCHITECTURE func3;
9 Components where are they stored? Simplest file structure options: 1. fulladder2.vhd and half_adder.vhd in the same directory and included in the same project (Quartus will find even if not included in the project warning). 2. fulladder2 and half_adder source code in the same file.
10 Four bit adder variation 1 FA FA FA FA
11 Vectors grouping bits/lines in VHDL, items can be grouped BIT BIT_VECTOR STD_LOGIC STD_LOGIC_VECTOR CHARACTER STRING vector range defined in one of two ways: BIT_VECTOR ( 7 DOWNTO 0 ) BIT_VECTOR ( 0 TO 7)
12 -- Four bit ripple carry adder with full adder (page 1/2) library IEEE; use IEEE.std_logic_1164.all; ENTITY fulladder IS PORT( A, B, Cin : IN STD_LOGIC; Sum, Cout : OUT STD_LOGIC); END ENTITY fulladder; ARCHITECTURE logicfunc OF fulladder IS BEGIN Sum <= A xor B xor Cin; Cout <= (A and B) or (( A xor B) and Cin); END ARCHITECTURE logicfunc;
13 -- Four bit ripple carry adder with full adder (page 2/2) library ieee; use ieee.std_logic_1164.all; entity adder4_combin is port( X, Y : in std_logic_vector (3 downto 0); Ci : in std_logic; S : out std_logic_vector (3 downto 0); Co : out std_logic); end entity adder4_combin; architecture structure of adder4_combin is signal C : std_logic_vector (0 to 2); component fulladder is port ( A, B, Cin : in std_logic; Sum, Cout : out std_logic); end component fulladder; begin FA_0: fulladder port map (X(0), Y(0), Ci, S(0), C(0)); FA_1: fulladder port map (X(1), Y(1), C(0), S(1), C(1)); FA_2: fulladder port map (X(2), Y(2), C(1), S(2), C(2)); FA_3: fulladder port map (X(3), Y(3), C(2), S(3), Co); end architecture structure;
14 Four bit adder variation 2 want to put the full adder into a user library Step 1: Define a package in a separate file. or Include the package definition at the end of the file that defines the full adder entity.
15 -- Full adder and full adder package LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY fulladder IS PORT( A, B, Cin : IN STD_LOGIC; Sum, Cout : OUT STD_LOGIC); END ENTITY fulladder; ARCHITECTURE logicfunc OF fulladder IS BEGIN Sum <= A xor B xor Cin; Cout <= (A and B) or (( A xor B) and Cin); END ARCHITECTURE logicfunc; LIBRARY ieee; USE ieee.std_logic_1164.all; PACKAGE fa_p IS COMPONENT fulladder IS PORT( A, B, Cin : IN STD_LOGIC; Sum, Cout : OUT STD_LOGIC); END COMPONENT fulladder; END PACKAGE fa_p;
16 Four bit adder variation 2 want to put the full adder into a user library Step 2: Program calls the library containing the package. *** When using a library, the component declaration is not required.
17 -- Four bit ripple carry adder using a full adder package library IEEE; use IEEE.std_logic_1164.all; use work.fa_p.fulladder; entity adder4 is port(x, Y : in std_logic_vector (3 downto 0); Ci : in std_logic; S : out std_logic_vector (3 downto 0); Co : out std_logic); end entity adder4; architecture structure of adder4 is signal C : std_logic_vector (0 to 2); begin FA_0: fulladder port map (X(0), Y(0), Ci, S(0), C(0)); FA_1: fulladder port map (X(1), Y(1), C(0), S(1), C(1)); FA_2: fulladder port map (X(2), Y(2), C(1), S(2), C(2)); FA_3: fulladder port map (X(3), Y(3), C(2), S(3), Co); end architecture structure;
18 Sixteen bit adder general case If we want to expand the previous program to 16, 32, or 64 bits, it would be painful. Generalize by using: generic to specify the number of bits once in the entity the remainder of the code is written in terms of the generic variable for-generate loop to create all the required instances of the component
19 -- Sixteen bit ripple carry adder using generic and generate library ieee; use ieee.std_logic_1164.all; use work.fa_p.fulladder; entity addern is generic (n : integer := 16); port(x, Y : in std_logic_vector ( downto 0); Ci : in std_logic; S : out std_logic_vector ( downto 0); Co : out std_logic); end entity addern; architecture structure of addern is signal C : std_logic_vector (0 to ); begin FA_0 : fulladder port map (X(0), Y(0), Ci, S(0), C(0)); FA_n : for i in 1 to n-2 generate FA: fulladder port map (X( ), Y( ), C( ), S( ), C( )); end generate; FA_msb : fulladder port map (X( ), Y( ), C( ), S( ),Co); end architecture structure;
20 -- Sixteen bit ripple carry adder --> improving the general case library ieee; use ieee.std_logic_1164.all; use work.fa_p.fulladder; entity addern is generic (n : integer := 16); port(x, Y : in std_logic_vector ( downto 0); Ci : in std_logic; S : out std_logic_vector ( downto 0); Co : out std_logic); end entity addern; architecture structure of addern is signal C : std_logic_vector (0 to ); begin FA_0 : fulladder port map (X(0), Y(0), Ci, S(0), C(0)); FA_n : for i in 1 to n-2 generate FA: fulladder port map (X( ), Y( ), C( ), S( ), C( )); end generate; FA_msb : fulladder port map (X( ), Y( ), C( ), S( ),Co); end architecture structure;
21 Four bit adder using arithmetic Note: Package ieee.std_logic_unsigned.all allows use of binary numbers in arithmetic circuits.
22 -- Four bit adder using binary arithmetic library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity adderb is port (X, Y : in std_logic_vector (3 downto 0); Cin : in std_logic; S : out std_logic_vector (3 downto 0); Cout : out std_logic); end entity adderb; architecture behaviour of adderb is signal Sum : std_logic_vector (4 downto 0); begin Sum <= ('0' & X) + Y + Cin; S <= Sum(3 downto 0); Cout <= Sum(4); end architecture behaviour;
23 Constant Declaration for readability CONSTANT constant_name : type := value; e.g. constant bus_size : integer := 32; constant msb : integer := bus_size - 1;
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COVER SHEET: Total: Regrade Info: 5 (5 points) 2 (8 points) 6 (10 points) 7b (13 points) 7c (13 points) 7d (13 points)
EEL 4712 Midterm 2 Spring 2011 VERSION 1 Name: UFID: Sign your name here if you would like for your test to be returned in class: IMPORTANT: Please be neat and write (or draw) carefully. If we cannot read
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Sign here to give permission to return your test in class, where other students might see your score:
EEL 4712 Midterm 1 Spring 2017 VERSION 1 Name: UFID: Sign here to give permission to return your test in class, where other students might see your score: IMPORTANT: Please be neat and write (or draw)
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COVER SHEET: Total: Regrade Info: 2 (6 points) 3 (8 points) 4 (10 points) 8 (12 points) 6 (6 points) 7 (6 points) 9 (30 points) 10 (4 points)
EEL 4712 Midterm 2 Spring 2010 VERSION 1 Name: UFID: Sign your name here if you would like for your test to be returned in class: IMPORTANT: Please be neat and write (or draw) carefully. If we cannot read
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COVER SHEET: Total: Regrade Info: 5 (14 points) 7 (15 points) Midterm 1 Spring 2012 VERSION 1 UFID:
EEL 4712 Midterm 1 Spring 2012 VERSION 1 Name: UFID: IMPORTANT: Please be neat and write (or draw) carefully. If we cannot read it with a reasonable effort, it is assumed wrong. As always, the best answer