CPU Design John D. Carpinelli, All Rights Reserved 1

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1 CPU Design 1997 John D. Carpinelli, All Rights Reserved 1

2 Outline Register organization ALU design Stacks Instruction formats and types Addressing modes 1997 John D. Carpinelli, All Rights Reserved 2 We begin this module by examining the organization of registers within a CPU. We see how data is routed to and from registers and how this routing is controlled by the CPU. Next, we examine how the ALU processes data received from the registers and how it stores data to the registers. We look at some ALU operations and the internal design of the ALU. This encompasses processing of both arithmetic and logical instructions. We also design and implement a simple 4-instruction CPU and its associated ALU. Stacks are used in computers for managing memory and for performing arithmetic and logical operations. We examine the structore of stacks and the operations performed on data in the stacks. We see how stacks are used to manage subroutine return addresses. We also look at how to use the stack to perform computations. Different CPU and ALU designs necessitate different instruction formats. We will review these formats and how they affect system design and performance. We will also review different addressing modes used within CPUs. Finally, concluding remarks are presented.

3 CPU components Registers Control ALU 1997 John D. Carpinelli, All Rights Reserved 3 This figure shows the general design of a CPU. Data is made available to the ALU from the registers; the ALU makes its results available for storage in the registers. The control section supplies the signals to cause the correct data transfers and ALU functions to occur.

4 Register organization See figure 8.2(a), p. 243 of the textbook John D. Carpinelli, All Rights Reserved 4 This figure shows how data can be routed between the ALU and the registers. The ALU has two inputs, the A bus and the B bus, each of which can receive data from any register R1 through R7, or from an external input. The SELA and SELB signals are the control inputs to the multiplexers; they determine which data is passed into the ALU. The ALU performs one of a number of functions depending on the value of the OPR inputs. Just as SELA and SELB select the data to be input to the ALU, OPR selects the function to be performed by the ALU. Internally, the ALU inputs the OPR control signals and converts them to the signals it needs to perform the proper function. We ll look at this in more detail later in this module. Finally, the SELD signals are used to select the destination register in the same way as SELA and SELB select the inputs. The only difference is that SELD is decoded to generate one of eight outputs (seven used and one unused).

5 Control word SEL A SEL B SEL D OPR 1997 John D. Carpinelli, All Rights Reserved 5 A control word is used to group the signals which select the registers and the ALU operation. For the configuration shown previously, we need four fields. One field selects the source of the A operand; another selects the source of the B operand. A third field tells the ALU which function to perform. The final field selects the destination register in which to store the result.

6 Register selection fields Binary Code SEL A SEL B SEL D 000 Input Input None 001 R1 R1 R1 010 R2 R2 R2 011 R3 R3 R3 100 R4 R4 R4 101 R5 R5 R5 110 R6 R6 R6 111 R7 R7 R John D. Carpinelli, All Rights Reserved 6 Here are some sample codes which may be used to select source and destination registers. Note that SELA and SELB can select any of the seven registers or an external input. SELD can select any of the seven registers as the destination register. As we saw in the last module, the ALU consists of combinatorial logic, so it always outputs a value, even when you don t want an ALU result, such as during an opcode fetch. Therefore, SELD must have an option of not storing the ALU result at all; this is the None option for binary code 000.

7 ALU operations OPR OPERATION OPR OPERATION Transfer A OR A and B Increment A XOR A and B Add A+B Complement A Subtract A-B Shift right A Decrement A Shift left A AND A and B 1997 John D. Carpinelli, All Rights Reserved 7 Here is a sample of some of the operations which can be performed by the ALU. It includes both arithmetic and logical operations. Recall the ALU design example in the previous module. In that design, a few control bits were input to the ALU, which used them to perform its internal operations. The operation (OPR) bits are those inputs to the ALU. It will decode the bits to generate the correct function.

8 General ALU design I 1 I 2 I 1 A I 2 A I 1 B I 2 B C o PARALLEL ADDER C i LOGIC SECTION 2-1 MUX OUTPUT 1997 John D. Carpinelli, All Rights Reserved 8 As its name implies, the arithmetic/logic unit handles both arithmetic and logical operations. This also describes its internal design. We have an arithmetic section, a logic section, and a section which selects whether the arithmetic or logic section s results are output from the ALU. The arithemetic section receives two inputs from outside the ALU, I 1 and I 2, and performs the necessary data transformations. The transformed data is sent into a parallel adder, which, along with the input carry, generate the correct arithmetic result. We ll look at this section, along with the logic section and output arbitration, in more detail shortly.

9 Parallel adder INSTR. I 1 A I 2 A C i OPCODE ADD I 1 I SSS ADC I 1 I 2 CY 10001SSS SUB I 1 I SSS SBB I 1 I 2 CY 10011SSS INR 0 I DDD100 DCR -1 I DDD101 MOV 0 I DDDSSS 1997 John D. Carpinelli, All Rights Reserved 9 Before designing the internal components of the CPU, we must know the instructions set it is to realize. For example, consider this instruction set. (These are the arithmetic instructions only; there are also logical instructions which we will see when we design the logic section.) The values of I 1 A, I 2 A and C i are determined such that the parallel adder generates the correct functions. For example, the subtract instruction performs I 1 - I 2 as a 2 s-complement addition, I 1 + / I The MOV instruction generates I 2 as 0 + I 2, and so on. A few notes: CY is the carry flag of this CPU. It is contained within the CPU but is external to the ALU. I 1 A can be I 1, 0 or -1, which is implemented in 2 s complement notation as all 1 s. I 2 A can be I 2 or /I 2. C i can be 0, 1, CY or /CY.

10 Design of I 1 A and I 2 A I MUX I 1 A I 2 (O 7 O 6 O 5 O 4 ) + I 2 A GND 3 S 1 S 0 (O 7 O 6 ) (O( 7 O 6 O 2 O 1 O 0 ) (O 7 O 6 O 2 O 1 O 0 ) 1997 John D. Carpinelli, All Rights Reserved 10 To design the internal components of the ALU, we need to know two things: what they can do and when they do what they can do. For I 1 A, we know that this component inputs I 1 and outputs either I 1, 0 or -1 (implemented as all 1 s). From the previous table of arithmetic instructions, we know which opcodes require each output. We implement I 1 A as an n-bit 4-1 mux. (We actually only need a 3-1 mux, but these things are usually designed for 2^x inputs.) We assign the inputs of the mux and determine the proper control logic to generate the correct value of I 1 A. There is one other thing of note in this design. I noted that I 1 is used by most of the arithmetic instructions. By assigning it to input 0 of the mux, we can effectively ignore these instructions in generating the control inputs to the mux, since they require values of zero to pass I 1 through. This minimizes the control logic to the mux. The design of the logic to generate I 2 A follows the same process. Here the only possible outputs are I 2 and / I 2, so we use a bank of exclusive or gates to generate these values. This is the same design used to generate B and /B in the adder/subtractor example in a previous module.

11 Design of C i CY MUX C i CY 3 S 1 S 0 (O 7 O 6 O 5 O 4 ) (O( 7 O 6 O 2 O 1 O 0 ) (O 7 O 6 O 5 O 3 ) 1997 John D. Carpinelli, All Rights Reserved 11 C i can take on one of four values: 0, 1, CY or /CY. We follow the same procedure as before, determining which opcodes require which outputs in order to generate the mux control signals.

12 Logic section INSTR. OPCODE ANA 10100SSS ORA 10110SSS XRA 10101SSS CMA John D. Carpinelli, All Rights Reserved 12 There are four logic instructions in this CPU: AND, OR, exclusive-or and complement. We will once again use opcodes to generate control signals to produce the correct logical output.

13 Logic section I 1 B I 2 B ' ) + - (O 6 O 5 O 4 O 3 ) (O 7 O 2 O 1 O 0 ) MUX 3 S 1 S 0 (O 7 O 6 O 5 O 4 ) 1997 John D. Carpinelli, All Rights Reserved 13 Since all logical operations in this CPU are bitwise, we do not need a parallel adder; a multiplexer with gated inputs to realize the correct functions will do. We make the logical and, or, exclusive or and complement operations available to the logic section. We generate the mux control signals just as before, based on the opcodes.

14 Output multiplexer control From P.A MUX Output From MUX 1 S (O 7 O 6 O 5 )(O 4 O 3 ) (O 6 O 5 O 4 O 3 O 2 O 1 O 0 ) 1997 John D. Carpinelli, All Rights Reserved 14 Finally, we choose from the parallel adder output and the logic mux output to generate the ALU output. Again, since there are fewer logic instructions than arithmetic instructions, we connect the logic mux to input 1 to minimize control logic.

15 Shift unit (single stage) Shift right No shift Shift left D i+1 D i D i-1' ' ' ) Shift left = (O 7 O 6 O 5 O 3 O 2 O 1 O 0 ) Shift right = (O 7 O 6 O 5 O 3 O 2 O 1 O 0 ) D i No shift = Shift left ^ Shift right 1997 John D. Carpinelli, All Rights Reserved 15 The output of the Arithmetic/Logic selection mux is then passed to a shift uit which either shifts the data one position to the left, passes it through unchanged or shifts it one position to the right. As with the previous components, these control signals are derived from the opcodes of the instruction. For the shift left, D 0 is replaced by I L, which is the most significant bit, D n-1, for the left circular shift, or the carry bit, CY, for the rotate left through carry instruction. Similarly, D n-1 is replaced by I R for the right circular shift (D 0 ) and the rotate right through carry (CY).

16 Example: CPU design Instruction set: Instruction Code Operation ADD 00XXYY X X+Y MOV 01XXYY X Y (X 0+Y) AND 10XXYY X X^Y NOT 11XX-- X X 1997 John D. Carpinelli, All Rights Reserved 16 To illustrate these concepts, we will design a CPU which realizes this instruction set. This CPU is meant to illustrate CPU design concepts, and is not meant to be a useful CPU. For instance, there is no way to load data from memory into any register, nor is there any way to make the results of any CPU operation available to the outside world! This CPU has four instructions, each with a 6-bit instruction code. The code s first two bits select the instruction to be performed. The next four bits select the operand registers X and Y. Note that we will implement the MOV instruction by performing an addition of 0 and Y.

17 Example: Register Definitions Registers: A 00 B 01 C 10 D John D. Carpinelli, All Rights Reserved 17 This CPU has four registers. The codes are the same whether they are X or Y.

18 Example: Micro-operations T 0 : AR PC T 1 : DR M, PC PC+1 T 2 : IR DR O 5 O 4 T 3 : X X+Y O 5 O 4 T 3 : X Y O 5 O 4 T 3 : X X^Y O 5 O 4 T 3 : X X 1997 John D. Carpinelli, All Rights Reserved 18 Given these specifications, we determine the micro-operations necessary to realize the instruction set. T 0, T 1 and T 2 implement the opcode fetch, just as in the Basic Computer. During T 0, the address is copied from the program counter to the address register. The instruction is read in from memory to the data register during T 1 ; the program counter is also incremented during this cycle. During T 2, the instruction code is copied into the instruction register. In this design, this is really overkill. These components are included to illustrate how the design works. In reality, AR and IR and not essential to this design. Each instruction is executed during a single clock cycle. The actual registers X and Y are selected by the instruction code. Note that we have not explicitly generated D 0 -D 3 in this design. This function is essentially performed by the different values of O 5 and O 4 in the triggering conditions of the micro-operations.

19 Example: General design Input Section ALU Output Section 1997 John D. Carpinelli, All Rights Reserved 19 The design of the CPU breaks down into several sections. The first, the control unit, is not shown here. The input section is responsible for routing the correct data to the ALU. The ALU will perform the proper operation. The output section will store the result in the appropriate register. There is also the register section for non-data processing registers, specifically AR, PC, DR and IR.

20 Example: Input section design A B C D A B C D O 3 O S 1 S 4-1 MUX MUX S 1 S 0 O 1 O 0 X Y 1997 John D. Carpinelli, All Rights Reserved 20 This is the design of the input section. Bits 3 and 2 of the opcode select the X register and bits 1 and 0 select the Y register. They are equivalent to I 1 and I 2 in the previous ALU design.

21 'O4 Example: ALU design X Y X Y X - ' PARALLEL ADDER GND O 4 S MUX O 5 S MUX OUTPUT 1997 John D. Carpinelli, All Rights Reserved 21 Once the data is made available to the ALU, it is processed accordingly. The ADD and MOV instructions are implemented as arithmetic instructions; the MOV is realized as 0 + Y. In either case, Y is one of the two inputs and the carry in is zero. For the ADD instruction, the other operand is X and for the MOV instruction it is 0. We want it to be zero when O 4 = 1, so we AND it with /O 4. When O 4 = 0, as for the ADD instruction, /O 4 = 1 and X ^ 1 = X. When O 4 = 1, as for the MOV instruction, / O 4 = 0 and X ^ 0 = 0. The logic instructions are processed as before. O 4 = 0 for the AND instruction and O 4 = 1 for the NOT instruction. Finally, the output mux selects from the output of the parallel adder and the output of the logic mux. The arithmetic instructions both have O 5 = 0 and the logic instructions both have O 5 = 1, (This is why we didn t have to worry about O 5 above.) This CPU does not perform shift operations, so no shift unit is included in this CPU.

22 Example: Output section design OUTPUT FROM ALU A B C D clk clk clk clk O 3 S 1 O 2-4 DEC E T 3 2 S John D. Carpinelli, All Rights Reserved 22 Once the output is available from the ALU, it must be stored in one of the four registers, A, B, C or D, as selected by bits 3 and 2 of the opcode. A 2-4 decoder selects the appropriate register. The decoder is only enabled during T 3, since this is the only cycle in which an ALU result is stored. Since every instruction stores a value during T 3, this signal is sufficient.

23 Control signals SC UP D E C O D E R T 0 T 1 T 2 T 3 CLK 1997 John D. Carpinelli, All Rights Reserved 23 This circuit generates the constant sequence T 0, T 1, T 2, T 3, T 0, etc. Since every instruction takes exactly four T-states, no clear is needed.

24 Other registers PC AR M DR INC LD LD T 1 T 1 T 0 O(5..0) IR LD T John D. Carpinelli, All Rights Reserved 24 This circuit implements the remaining hardware for the CPU. The program counter is a 6-bit counter. It is incremented during T 1, but is never loaded. The address register is loaded during T 0. DR always receives its data from memory during T 1, and IR loads its data from DR during T 2. The outputs of IR are the bits O(5..0) of the opcode.

25 Stacks Stack: Last In First Out (LIFO); used for storing return addresses, saving data or performing computations. Stack pointer: contains the address of the top element of the stack John D. Carpinelli, All Rights Reserved 25 Stacks are usually constructed by using part of a computer system s RAM. Since programs usually start in low memory and grow upward, stacks often start in high memory and grow downward. This makes the best use of available memory, by growing both program and stack data into the same available space.

26 PUSH OPERATION Example: SP = 1234H; B = 09H; PUSH B BEFORE: AFTER: SP=1234H SP=1233H B=09H B=09H M[1233H]=XX M[1233H]=09H 1997 John D. Carpinelli, All Rights Reserved 26 Note that the contents of B are unchanged.

27 POP OPERATION Example: SP = 1233H; M[1233H] = 09H; B=55H; POP B BEFORE: AFTER: SP=1233H SP=1234H B=55H B=09H M[1233H]=09 M[1233H]=09H 1997 John D. Carpinelli, All Rights Reserved 27 Note that popping data from the stack does not remove it from memory. By incrementing the stack pointer, location 1233H is removed from the stack. The next time data is pushed onto the stack, it will overwrite the value 09H in this location. This is similar to how PC s delete files from disks. They do not overwrite the actual file; instead, they mark the directory entry as open. This is how undelete programs can recover files. The push and pop operations can be used not only for data, but also for addresses. Unlike the Basic Computer, most CPUs use a stack when handling subroutine return addresses. A call statement pushes the return address onto the stack and a return statement pops the return address off of the stack and into the program counter. Using a stack allows a CPU to implement recursion, which could not be done in the Basic Computer.

28 Performing computations using stacks Stacks perform computations using Reverse Polish Notation (RPN). Operands are pushed onto the stack; operations pop the operands off the stack, perform their operations and push the result back onto the stack John D. Carpinelli, All Rights Reserved 28 Performing computations using stacks is familiar to anyone who has used an HP calculator. The operands are pushed onto the stack, then the operation to be performed pops these operands off the stack, performs its computation and pushes the result onto the stack. This is an efficient architecture because the ALU has only one place to access its operands, as opposed to the multiple registers in previous examples. This results in a reduced propagation delay and a faster clock cycle.

29 Example: X=(A*B)+(C*D) OPERATION PUSH A STACK PUSH B B A * (A*B) PUSH C PUSH D 1997 John D. Carpinelli, All Rights Reserved 29 A C (A*B) D C (A*B) * (C*D) (A*B) + (A*B)+(C*D) POP X EMPTY The RPN notation for this equation is AB*CD*+. This slide shows how this would be implemented on a stack-oriented machine. Stacks can be used to process logical expressions as well as arithmetic expressions. The mechanics is similar in both cases.

30 Instruction formats 3 address: ADD A, B, C A B+C 2 address: ADD A, B A A+B 1 address: ADD AACC ACC+B 0 address: ADD TOS TOS+SOS 1997 John D. Carpinelli, All Rights Reserved 30 There are several instruction formats, depending on the number of operands. Here are some examples using 3, 2, 1 and 0 addresses. Note that having more addresses allows you to perform more complex instructions, but requires more complex hardware.

31 Example: X=(A+B)*(C+D) 3 address: ADD T, A, B ADD U, C, D MUL X, T, U T A+B U C+D X (A+B)*(C+D) 1997 John D. Carpinelli, All Rights Reserved 31 Here is how you would implement the previous function using 3-, 2-, 1- and 0- address instructions. The 3-address instructions require three instructions to generate the result. Note that temporary registers T and U are used to store partial results. It is important not to modify A, B, C nor D as part of the instruction execution.

32 Example: X=(A+B)*(C+D) 2 address: MOV T, A ADD T, B MOV U, C ADD U, D MUL T, U MOV X, T T A T A+B U C U C+D T (A+B)*(C+D) X (A+B)*(C+D) 1997 John D. Carpinelli, All Rights Reserved 32 The 2-address mode requires six instructions. Again, temporary registers are used so as not to modify other registers.

33 Example: X=(A+B)*(C+D) 1 address: LOAD A ADD B STORE T LOAD C ADD D MUL T STORE X AC A AC A+B T A+B AC C AC C+D AC (A+B)*(C+D) X (A+B)*(C+D) 1997 John D. Carpinelli, All Rights Reserved 33 One address format requires seven instructions. Note that AC acts as a temporary register; it also always receives the results of all ALU operations.

34 Example: X=(A+B)*(C+D) 0 address: PUSH A TOS A PUSH D TOS D PUSH B TOS B ADD TOS C+D ADD TOS A+B MUL TOS * PUSH C TOS C POP X X TOS *: (A+B)*(C+D) 1997 John D. Carpinelli, All Rights Reserved 34 Finally, we require eight 0-address instructions to implement this equation. After we are done, the stack contains exactly the same data as before the operations. If we didn t do this, we would have something called stack creep, in which extra data left on the stack eventually causes it to overflow.

35 Addressing modes Implied Immediate Register Register-Indirect Autoincrement Autodecrement Direct Indirect Relative Indexed Base Register 1997 John D. Carpinelli, All Rights Reserved 35 These addressing modes are described on the following slides.

36 Addressing modes (continued) Implied: Instruction implicitly specifies operands; e.g. CMA, all 0-address instructions Immediate: Operand specified by the instruction; e.g. MVI A, 27H 1997 John D. Carpinelli, All Rights Reserved 36 CMA = complement register A MVI A, 27H = register A gets 27H

37 Addressing modes (continued) Register: Instruction specifies the register which contains the operand; e.g. INR B Register Indirect: Instruction specifies the register which contains the address of the operand; e.g. LDAX B 1997 John D. Carpinelli, All Rights Reserved 37 INR B = increment register B LDAX B = load A indirect with the data whose address is stored in register pair BC

38 Addressing modes (continued) Autoincrement: Same as registerindirect mode, except the register is incremented before (or after) accessing values in memory. Autodecrement: Same as autoincrement, except decrement instead of increment the register value John D. Carpinelli, All Rights Reserved 38 These addressing modes are useful for implement PUSH and POP operations.

39 Addressing modes (continued) Direct: The instruction specifies the addres; e.g. BUN 200H Indirect: The instruction specifies the address of a memory location which contains the actual address; e.g. BUN I 200H 1997 John D. Carpinelli, All Rights Reserved 39 Direct is used for loading specific memory locations or absolute jumps. Indirect is used when a memory location points to a data structure to be accessed. This is important for relocatable code.

40 Addressing modes (continued) Relative: Instruction specifies the offest from the Program Counter; e.g. LD $ADR: AC M[PC+ADR] Indexed: Address is specified by instruction + contents of the index register. Base Register: Acts the same as indexed John D. Carpinelli, All Rights Reserved 40 Relative mode is useful for short jumps. Indexed mode is useful for programs which maintain large stack frames, such as hierarchical graphics systems.

41 Summary CPU components Register organization ALU design CPU design example Stacks Instruction formats/addressing modes Next module: Microprogramming 1997 John D. Carpinelli, All Rights Reserved 41 This module has introduced the CPU components in more detail. We have examined the internal register organization within the CPU and the internal design of the ALU. We reviewed a comprehensive, simple CPU design. We also examined stacks, instruction formats and various addressing modes. The CPUs we have seen so far have all been hard-wired, that is, the control signals were generated using combinatorial logic. In the next module, we will examine microprogramming, the other popular alternative for control unit design.

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