Architecture I. Computer Systems Laboratory Sungkyunkwan University

Transcription

1 MIPS Instruction ti Set Architecture I Jin-Soo Kim (jinsookim@skku.edu) Computer Systems Laboratory Sungkyunkwan University

2 Architecture (1) the attributes of a system as seen by the programmer, ie i.e., the conceptual structure and functional behavior, as distinct from the organization of the data flow and controls, the logical design, and the physical implementation Amdahl, Blaauw, and Brooks, Architecture of the IBM System/360, IBM Journal of Research and Development, April The visible ibl interface between software and hardware What the user (OS, compiler, ) needs to know to reason about how the machine behaves Abstracted from the details of how it may accomplish its task 2

3 Architecture (2) Computer Architecture defines Instruction set architecture (ISA) Instruction set Operand types Data types (integers, FPs, ) Memory addressing modes, Registers and other state The interrupt/exception t/ ti model Memory management and protection Virtual and physical address layout I/O model... 3

4 Architecture (3) Microarchitecture Organization of the machine below the visible level Number/location of functional units Pipeline/cache configurations Programmer transparent techniques: prefetching, Must provide same meaning (semantics) as the visible architecture model Implementation Hardware realization Logic circuits, VLSI technology, process,... 4

5 Architecture (4) Architecture Brand Name XScale (IXA) IA 32 Intel 64 (IA 32e, EM64T, x86 64) Itanium (IA 64) Microarchitecture Brand Name Processor Brand Name P5 P6 NetBurst Mobile Core Pentium Pentium MMX Pentium Pro Pentium II Pentium III Pentium 4 Pentium D Pentium M Core Duo/Solo Core 2 Quad/Duo/Solo Processor Code Name P5, P54C, P54CS P55C, Tillamook Pentium Pro Klamath, Deschutes Katmai, Coppermine, Tualatin Willamette, Northwood, Prescott, Cedar Mill Smithfield, Presler Banias, Dothan Yonah Conroe, Allendale, Wolfdale Merom, Penryn Kentsfield, Yorkfield 5

6 Instruction Set (1) Instruction set The repertoire of instructions of a computer Different computers have different instruction sets But with many aspects in common 1400 Early computers had very simple instruction sets Simplified implementation Many modern computers also have simple instruction sets RISC (Reduced Instruction Set Computer) Other SPARC Hitachi SH PowerPC Motorola 68K MIPS IA-32 ARM

7 Instruction Set (2) MIPS instruction set Similar to other architectures developed since 1980 s Stanford MIPS commercialized by MIPS Technologies ( Large share of embedded core market Applications in consumer electronics, network/storage equipment, cameras, printers, Almost 100 million MIPS processors manufactured in 2002 Used by NEC, Nintendo, Cisco, Silicon Graphics, Sony, Typical of many modern ISAs See MIPS Reference Data tear-out card ( green card ), and Appendixes B and E 7

8 Arithmetic Operations (1) Arithmetic operations Add and subtract, three operands Two sources and one destination add a, b, c # a b + c All arithmetic operations have this form Design Principle 1: Simplicity favors regularity Regularity makes implementation simpler Simplicity enables higher performance at lower cost 8

9 Arithmetic Operations (2) Arithmetic example C code: f = (g + h) (i + j); Compiled MIPS code: add t0, g, h # temp t0 = g + h add t1, i, j # temp t1 = i + j sub f, t0, t1 # f = t0 t1 9

10 Operands (1) Register operands Arithmetic instructions use register operands MIPS has a 32 x 32-bit register file Use for frequently accessed data Numbered 0 to bit data called a word Assembler names $t0, $t1,, $t9 for temporary values $s0, $s1,, $s7 for saved variables Design Principle 2: Smaller is faster (cf.) Main memory: millions of locations 10

11 Operands (2) Register operand example C code: f = (g + h) (i + j); f, g, h, i, j in $s0, $s1, $s2, $s3, $s4 Compiled MIPS code: add $t0, $s1, $s2 add $t1, $s3, $s4 sub $s0, $t0, $t1 11

12 Operands (3) MIPS registers # Name Usage 0 $zero The constant value 0 1 $at Assembler temporary 2 $v0 Values for results and 3 $v1 expression evaluation 4 $a0 Arguments 5 $a1 6 $a2 7 $a3 8 $t0 Temporaries 9 $t1 (Caller save registers) 10 $t2 11 $t3 12 $t4 13 $t5 14 $t6 15 $t7 # Name Usage 16 $s0 Saved temporaries 17 $s1 (Callee save registers) 18 $s2 19 $s3 20 $s4 21 $s5 22 $s6 23 $s7 24 $t8 More temporaries 25 $t9 (Caller save registers) 26 $k0 Reserved for OS kernel 27 $k1 28 $gp Global pointer 29 $sp Stack pointer 30 $fp Frame pointer 31 $ra Return address 12

13 Operands (4) Memory operands Main memory used for composite data Arrays, structures, dynamic data To apply arithmetic operations Load values from memory into registers Store result from register to memory Memory is byte addressed Each address identifies ifi an 8-bit byte Words are aligned in memory Address must be a multiple of 4 MIPS is Big Endian Most-significant byte at least address of a word bits of data 32 bits of data 32 bits of data 32 bits of data 13

14 Operands (5) Memory operand example 1 C code: g = h + A[8]; g in $s1, h in $s2, base address of A in $s3 Compiled MIPS code: 4 bytes per word Index 8 requires offset of 32 lw $t0, 32($s3) # load word add $s1, $s2, $t0 offset base register 14

15 Operands (6) Memory operand example 2 C code: A[12] = h + A[8]; h in $s2, base address of A in $s3 Compiled MIPS code: Index 8 requires offset of 32 lw $t0, 32($s3) # load word add $t0, $s2, $t0 sw $t0, 48($s3) # store word 15

16 Operands (7) Register vs. Memory Registers are faster to access than memory Operating on memory data requires loads and stores More instructions to be executed Compiler must use registers for variables as much as possible Only spill to memory for less frequently used variables Register optimization i i is important 16

17 Operands (8) Immediate operands Constant data specified in an instruction addi $s3, $s3, 4 No subtract immediate instruction Just use a negative constant addi $s2, $s1, 11 Design Principle 3: Make the common case fast Small constants are common Immediate operand avoids a load instruction 17

18 Operands (9) The constant zero MIPS register 0 ($zero) is the constant 0 Cannot be overwritten Useful for common operations E.g., move between registers add $t2, $s1, $zero 18

19 Representing Data (1) Unsigned binary integers Given an n-bit number x + n 1 n = xn xn L + x1 2 x0 2 Range: 0 to +2 n 1 Example = = = Using 32 bits 0 to +4,294,967,295 19

20 Representing Data (2) 2 s-complement signed integers Given an n-bit number x + n 1 n = xn xn L + x1 2 x0 2 Range: 2 n 1 to +2 n 1 1 Example = = 2,147,483, ,147,483,644 = 4 10 Using 32 bits 2,147,483,648 to +2,147,483,647 20

21 Representing Data (3) 2 s-complement signed integers (cont d) Bit 31 is sign bit 1 for negative numbers 0 for non-negative numbers ( 2 n 1 ) can t be represented Non-negative numbers have the same unsigned and 2 s-complement representation Some specific numbers: 0: : Most negative: Most positive:

22 Representing Data (4) Signed negation Complement and add 1 Complement means 1 0, 0 1 x + x = = 1 x + 1= x Example: negate = = =

23 Representing Data (5) Sign extension Representing a number using more bits Preserve the numeric value In MIPS instruction set addi: extend immediate value lb, lh: extend loaded byte/halfword beq, bne: extend the displacement Replicate the sign bit to the left (cf.) unsigned values: extend with 0s Examples: 8-bit to 16-bit +2: :

24 Representing Instructions (1) Representing instructions in MIPS Instructions are encoded in binary Called machine code MIPS instructions Encoded as 32-bit instruction words Small number of formats encoding operation code (opcode), register numbers,... Regularity! Register numbers $t0 $t7 are registers 8 15 $t8 $t9 are registers $s0 $s7 are registers

25 Representing Instructions (2) MIPS R-format instructions op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits Instruction fields op: operation code (opcode) rs: first source register number rt: second source register number rd: destination register number shamt: shift amount (00000 for now) funct: function code (extends opcode) 25

26 Representing Instructions (3) MIPS R-format example op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits add $t0, $s1, $s2 special $s1 $s2 $t0 0 add =

27 Representing Instructions (4) MIPS I-format instructions op rs rt constant or address 6 bits 5 bits 5 bits 16 bits Immediate arithmetic and load/store instructions rt: destination or source register number Constant: 2 15 to Address: offset added to base address in rs Design Principle 4: Good design demands good compromises Different formats complicate decoding, but allow 32-bit instructions uniformly Keep formats as similar as possible 27

28 Representing Instructions (5) MIPS J-format instructions op address 6 bits 26 bits Jump instructions (j and jal) Address: encodes 26-bit target address 28

29 Representing Instructions (6) Stored program computers Instructions represented in binary, just like data Instructions and data stored in memory Programs can operate on programs e.g., compilers, linkers,... Binary compatibility allows compiled programs to work on different computers Standardized Sa dad ISAs 29

30 Logical Operations (1) Logical operations Instructions for bitwise manipulation Operation C Java MIPS Shift left << << sll Shift hf right >> >>> srl Bitwise AND & & and, andi Bitwise OR or, ori Bitwise NOT ~ ~ nor Useful for extracting and inserting groups of bits in a word 30

31 Logical Operations (2) Shift operations op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits shamt: how many positions to shift Shift left logical Shift left and fill with 0 bits sll by i bits multiples by 2 i Shift right logical Shift right and fill with 0 bits srl by i bits divides by 2 i (unsigned only) 31

32 Logical Operations (3) AND operations Useful to mask bits in a word Select some bits, clear others to 0 and $t0, $t1, $t2 $t2 $t $t

33 Logical Operations (4) OR operations Useful to include bits in a word Set some bits to 1, leave others unchanged or $t0, $t1, $t2 $t2 $t $t

34 Logical Operations (5) NOT operations Useful to invert bits in a word Change 0 to 1, and 1 to 0 MIPS has NOR 3-operand instruction a NOR b == NOT (a OR b) nor $t0, $t1, $zero $t1 $t