Objectives: 1. Design procedure. 2. Fundamental circuits. 1. Design procedure


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1 Objectives: 1. Design procedure. 2. undamental circuits. 1. Design procedure Design procedure has five steps: o Specification. o ormulation. o Optimization. o Technology mapping. o Verification. Specification: The design of a combinational circuit starts with the specification of the problem: Write a specification for the given circuit (text or HDL description (hardware description language)) with symbols for inputs and outputs. ormulation: Derive the truth table or initial oolean expressions (that define the required relationships between inputs and outputs). ormulation converts the specification into forms that can be optimized (truth table or oolean expression). Optimization: Any available methods to minimize the logic: Algebraic manipulation. Kmap method. Computerbased program. Then, we can use: Twolevel optimization or multiplelevel optimization to get less cost (use NAND and NOR gate technologies). Technology mapping (implementation): Transform the logic diagram to new logic diagram with available implementation. Verification: Verify the correctness of the final design.
2 2. undamental circuits These blocks are useful for designing large digital system, for example: o Code converters. o Adders. o Multiplexers. o Decoders. o Encoders and so on. Code converters Translate information from one binary code to another. o to Excess3 converter. o to sevensegment code converter. o to ray code converter. irst Code Combinational Circuits Second Code Example 1: Design of a toexcess3 code converter Specification: the excess3 code for a decimal digit is binary combination corresponding to the decimal digit plus 3. ormulation: the excess3 code is easily obtained from code by adding binary to it. The truth table relating the input and output values is the following: Input Output Decimal code Excess3 digit A C D W Z Code A C D MSD to Excess3 Convertor LSD W Excess3 Code Z
3 Optimization: Kmap for the outputs (four outputs) are shown, they are plotted to obtain simplified sumofproducts oolean expressions for the outputs. A A W A C D D C C D A A 1 1 C D Z The six don't care minterms, through 15 are marked as. Twolevel optimization (ANDOR) logic diagram for the circuit can be obtained directly from the oolean expressions derived from the maps. "Input gate cost = 26 including inverters" D
4 We can reduce the input gate cost using multiplelevel optimization as a second optimization step. o In this step, we consider the sharing sub expressions between the four output expressions. o Sharing expression: o The manipulation allows to reduce the gate input cost from 26 to 19. Technology mapping: The logic diagram is the following: A C D D W Sharing Component Logic Diagram for toexcess3 Converter Z Example 2: Design of a tosevensegment Decoder Specification: toseven segment decoder is a combinational circuit that o Accepts a decimal digit in and generates the appropriate output of the decoder: (a, b, c, d, e, f, g) segments. o selects the corresponding segments in the LED display (lightemitting diodes) as shown in figure:
5 f e a g d b c SevenSegment Display (LED) ormulation: The truth table for toseven segment decoder is the following: Input SevenSegment Outputs A C D a b c d e f g All other inputs We must draw for each output Karnaugh map and minimize all maps. The simplified outputs: Twolevel implementation: 27 AND gates and 7 OR gates Multiplelevel implementation: 14 AND gates Using sharing terms: A, and so on
6 Example 3: inarytoray Converter 1. Truth tables for outputs: ray Code 2. Kmaps: Decimal inary input ray outputs number
7 3. Logic Diagram: Logic diagram for binarytogray converter ExclusiveORoperator (OR ate). 3 Truth Table Inputs Output ExclusiveNORoperator (NOR ate). Truth Table Inputs Output 1
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