Chapter 2a: Structural Modeling
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1 Chapter 2a: Structural Modeling Prof. Ming-Bo Lin Department of Electronic Engineering National Taiwan University of Science and Technology Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 2-1
2 Syllabus Objectives Structure modeling Gate modeling Gate delays Hazards Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 2-2
3 Objectives After completing this chapter, you will be able to: Describe what is the structural modeling Describe how to instantiate gate primitives Describe how to model a design in gate primitives Describe inertial and transport delays Describe how to specify delays in gates Describe hazards and their effects in gate networks Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 2-3
4 Syllabus Objectives Structure modeling Structural styles Gate primitives Switch primitives Gate modeling Gate delays Hazards Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 2-4
5 Structural Styles A set of interconnected components Modules/UDPs Gate primitives Switch primitives Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 2-5
6 Syllabus Objectives Structure modeling Structural styles Gate primitives Switch primitives Gate modeling Gate delays Hazards Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 2-6
7 Gate Primitives 12 gate primitives Synthesizable and/or gates One scalar output Multiple scalar inputs Include and or xor nand nor xnor Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 2-7
8 Gate Primitives buf/not Gates One scalar input One or multiple scalar outputs Include buf not bufif0 notif0 bufif1 notif1 Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 2-8
9 Syllabus Objectives Structure modeling Structural styles Gate primitives Switch primitives Gate modeling Gate delays Hazards Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 2-9
10 Switch Primitives 16 switch primitives To model a new logic gate circuit at switch level Not synthesizable, in general Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 2-10
11 Syllabus Objectives Structure modeling Gate modeling and/or gate group buf/not gate group Instantiations of and/or gates Instantiations of buf/not gates Wired logic Gate delays Hazards Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 2-11
12 and/nand Gates Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 2-12
13 or/nor Gates Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 2-13
14 xor/xnor Gates Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 2-14
15 Syllabus Objectives Structure modeling Gate modeling and/or gate group buf/not gate group Instantiations of and/or gates Instantiations of buf/not gates Wired logic Gate delays Hazards Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 2-15
16 buf/not Gates Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 2-16
17 bufif0/notif0 Gates Note that: L represents 0 or z and H represents 1 or z. Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 2-17
18 bufif1/notif1 Gates Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 2-18
19 Syllabus Objectives Structure modeling Gate modeling and/or gate group buf/not gate group Instantiations of and/or gates Instantiations of buf/not gates Wired logic Gate delays Hazards Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 2-19
20 Instantiation of Basic Gates To instantiate and/or gates gatename [instance_name](output, input1, input2,..., inputn); instance_name is optional module basic_gates (x, y, z, f) ; input x, y, z; output f ; wire a, b, c; // Structural modeling nor g1 (b, x, y); not g2 (a, x); and g3 (c, a, z); nor g4 (f, b, c); endmodule Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 2-20
21 Array of Instances Array instantiations may be a synthesizer dependent! Suggestion: check this feature before using the synthesizer wire [3:0] out, in1, in2; // basic array instantiations of nand gate. nand n_gate[3:0] (out, in1, in2); // this is equivalent to the following: nand n_gate0 (out[0], in1[0], in2[0]); nand n_gate1 (out[1], in1[1], in2[1]); nand n_gate2 (out[2], in1[2], in2[2]); nand n_gate3 (out[3], in1[3], in2[3]); Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 2-21
22 An Example --- A 1-Bit Full Adder module full_adder_structural(x, y, c_in, s, c_out); // I/O port declarations input x, y, c_in; output s, c_out; wire s1, c1, c2, c3; // Structural modeling of the 1-bit full adder. xor xor_s1(s1, x, y); // compute sum. xor xor_s2(s, s1, c_in); and and_c1(c1, x, y); // compute carry out. and and_c2(c2, x, c_in); and and_c3(c3, y, c_in); or or_cout(c_out, c1, c2, c3); endmodule Chapter 2: Structural Modeling Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 2-22
23 An Example --- A 4-to-1 Multiplexer Chapter 2: Structural Modeling module mux4_to_1_structural (i0, i1, i2, i3, s1, s0, out); input i0, i1, i2, i3, s1, s0; output out; wire s1n, s0n; // Internal wire wire y0, y1, y2, y3; // Gate instantiations not (s1n, s1); // Create s1n and s0n signals not (s0n, s0); and (y0, i0, s1n, s0n); and (y1, i1, s1n, s0); and (y2, i2, s1, s0n); and (y3, i3, s1, s0); or (out, y0, y1, y2, y3); endmodule Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 2-23
24 An Example --- A 9-Bit Parity Generator Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 2-24
25 An Example --- A 9-Bit Parity Generator module parity_gen_9b_structural(x, ep, op); // I/O port declarations input [8:0] x; output ep, op; wire c, d, e, f, g, h, j; xor xor_11(c, x[0], x[1]); // first level xor xor_12(d, x[2], x[3]); xor xor_13(e, x[4], x[5]); xor xor_14(f, x[6], x[7]); xor xor_21(g, c, d); // second level xor xor_22(h, e, f); xor xor_31(i, g, h); // third level xor xor_ep(ep, i, x[8]); // fourth level xnor xnor_op(op, i, x[8]); endmodule Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 2-25
26 Syllabus Objectives Structure modeling Gate modeling and/or gate group buf/not gate group Instantiations of and/or gates Instantiations of buf/not gates Wired logic Gate delays Hazards Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 2-26
27 Instantiation of Tristate Buffers To instantiate tristate buffers Chapter 2: Structural Modeling buf_name[instance_name](output, input, control); The instance_name is optional // 2-to-1 mux module two_to_one_mux_tristate (x, y, s, f); input x, y, s; output f; tri f; // internal declaration // data selector body bufif0 b1 (f, x, s); bufif1 b2 (f, y, s); endmodule Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 2-27
28 Syllabus Objectives Structure modeling Gate modeling and/or gate group buf/not gate group Instantiations of and/or gates Instantiations of buf/not gates Wired logic Gate delays Hazards Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 2-28
29 wand/triand and wor/trior Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 2-29
30 Wired AND Gates module open_drain (w, x, y, z, f); input w, x, y, z; output f; wand f; // internal declaration // wired AND logic gate nand n1 (f, w, x); nand n2 (f, y, z); endmodule Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 2-30
31 Syllabus Objectives Structure modeling Gate modeling Gate delays Delay models Gate delay specifications Hazards Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 2-31
32 Delay Models Inertial delay model Transport delay model Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 2-32
33 Inertial Delay Model Inertial delay model To model gate delays The default gate delay is 0 The default delay model for HDL (Verilog HDL and VHDL) Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 2-33
34 The Effects of Inertial Delays Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 2-34
35 Transport delay model Transport delay model To model net (i.e. wires) delays The default delay of a net is zero Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 2-35
36 The Effects of Transport and Inertial Delays Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 2-36
37 Syllabus Objectives Structure modeling Gate modeling Gate delays Delay models Gate delay specifications Hazards Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 2-37
38 Gate Delay Specifications Specify propagation delay only gatename #(prop_delay) [instance_name](output, in_1, in_2, ); Specify both rise and fall times gatename #(t_rise, t_fall) [instance_name](output, in_1, in_2, ); Specify rise, fall, and turn-off times (tristate buffers) gatename #(t_rise, t_fall, t_off) [instance_name](output, in_1, in_2, ); Delay specifier: min:typ:max Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 2-38
39 Gate Delays Specifications // Only specify one delay and #(5) a1 (b, x, y); // Only specify one delay using min:typ:max not #(10:12:15) n1 (a, x); // Specify two delays using min:typ:max and #(10:12:15, 12:15:20) a2 (c, a, z); // Specify three delays using min:typ:max bufif0 #(10:12:15, 12:15:20, 12:13:16) buf1 (f, b, c); Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 2-39
40 Syllabus Objectives Structure modeling Gate modeling Gate delays Hazards Static hazards Dynamic hazards Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 2-40
41 Hazards and Their Effects Hazards Unwanted short-width output signals Types Static hazards Dynamic hazards Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 2-41
42 A Static Hazard Example module hazard_static (x, y, z, f); input x, y, z; output f; wire a, b, c; and #5 a1 (a, x, y); not #5 n1 (c, x); and #5 a2 (b, c, z); or #5 o2 (f, b, a); endmodule Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 2-42
43 Syllabus Objectives Structure modeling Gate modeling Gate delays Hazards Static hazards Dynamic hazards Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 2-43
44 A Dynamic Hazard Example Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 2-44
45 A Dynamic Hazard Example // dynamic hazard example module hazard_dynamic(w, x, y, z, f); input w, x, y, z; output f; // internal declaration wire a, b, c, d, e; // logic circuit body nand #5 nand1 (b, x, w); not #5 n1 (a, w); nand #5 nand2 (c, a, y); nand #5 nand3 (d, b, c); nand #5 nand4 (e, w, z); nand #5 nand5 (f, d, e); endmodule Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 2-45
46 A Dynamic Hazard Example `timescale 1ns / 1ns module hazard_dynamic_tb; reg w, x, y, z; wire f; // Unit Under Test port map hazard_dynamic UUT (.w(w),.x(x),.y(y),.z(z),.f(f)); initial begin w = 1'b0; x = 1'b0; y = 1'b0; z = 1'b0; #5 x = 1'b1; y = 1'b1; z = 1'b1; #30 w = 1'b1; #20 w = 1'b0; #190 $finish; end initial $monitor($realtime,,"ns %h %h %h %h %h ",w,x,y,z,f); endmodule Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 2-46
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