Digital Circuit Design and Language. Datapath Design. Chang, Ik Joon Kyunghee University

Size: px
Start display at page:

Download "Digital Circuit Design and Language. Datapath Design. Chang, Ik Joon Kyunghee University"

Transcription

1 Digital Circuit Design and Language Datapath Design Chang, Ik Joon Kyunghee University

2 Typical Synchronous Design + Control Section : Finite State Machine + Data Section: Adder, Multiplier, Shift Register etc.

3 Registers

4 Registers with Parallel Loads

5 Shift Register and Serial Transfer Rotate Register Shift Register Serial Transfer (A B) Input Timing Diagram of Serial Transfer

6 Shift Register and Serial Transfer (Cont.) Example of Serial Transfer Timing pulse Shift register A Shift register B Serial output of B Initial value After T After T2 After T3 After T4

7 Universal Shift Register (Behavioral Description) Input and Output Diagram Function Table Clear: Low Reset the register CLK: the signal to synchronize the operations S, S : Mode Control Signal I_par: parallel inputs (4-bit) A_par: parallel outputs (4-bit)

8 Universal Shift Register (Logic Diagram)

9 Universal Shift Register (HDL Code) <Behavioral Model> <Structural Model> module Shift_Register_4_beh ( output reg [3: ] A_par, // Register output input [3: ] I_par, // Parallel input input s, s, // Select inputs MSB_in, LSB_in, // Serial inputs CLK, Clear // Clock and Clear ); (posedge CLK, negedge Clear) if (~Clear) A_par <= 4'b; else case ({s, s}) 2'b: A_par <= A_par; // No change 2'b: A_par <= {MSB_in, A_par[3: ]}; // Shift right 2'b: A_par <= {A_par[2: ], LSB_in}; // Shift left 2'b: A_par <= I_par; // Parallel load of input endcase endmodule module Shift_Register_4_str ( output [3: ] A_par, // Parallel output input [3: ] I_par, // Parallel input input s, s, // Mode select input MSB_in, LSB_in, CLK, Clear ); // bus for mode control wire [:] select = {s, s}; // Instantiate the four stages stage ST (A_par[], A_par[], LSB_in, I_par[], A_par[], select, CLK, Clear); stage ST (A_par[], A_par[2], A_par[], I_par[],A_par[], select, CLK, Clear); stage ST2 (A_par[2], A_par[3], A_par[], I_par[2], A_par[2], select, CLK, Clear); stage ST3 (A_par[3], MSB_in, A_par[2], I_par[3], A_par[3], select, CLK, Clear); endmodule module stage (i, i, i2, i3, Q, select, CLK, Clr); input i, i, i2, i3; // data from parallel input output Q; input [: ] select; // stage mode control bus input CLK, Clr; // Clock, Clear for flip-flops wire mux_out; Mux_4_x_ M (mux_out, i, i, i2, i3, select); D_flip_flop M (Q, mux_out, CLK, Clr); endmodule

10 Adders + Adds two N-bit binary numbers 2-bit adder: adds two 2-bit numbers, outputs 3-bit result e.g., + = ( + 3 = 4) + Can we design using combinational design process? s s c b b a Inputs Outputs a

11 Why Different Design for Adders?

12 Adders + Adds two N-bit binary numbers 2-bit adder: adds two 2-bit numbers, outputs 3-bit result e.g., + = ( + 3 = 4) + Can we design using combinational design process? s s c b b a Inputs Outputs a

13 Ripple-Carry Adder + Using half-adder and full-adders, we can build adder that adds like we would by hand + Called a Ripple-Carry adder 4-bit adder shown: Adds two 4-bit numbers, generates 5-bit output 5-bit output can be considered 4-bit sum plus -bit carry out Can easily build any size adder a3 b3 a2 b2 a b a b a b FA co ci s a b FA co ci s a b FA co ci s a b HA co s a3 a2 a a b3 b2 b b 4-bit adder co s3 s2 s s co s3 s2 s (a) s (b)

14 Ripple-Carry Adder with C in + Using full-adder instead of half-adder for first bit, we can include a carry in bit in the addition Useful later when we connect smaller adders to form bigger adders a3 b3 a2 b2 a b a b ci a b ci a b ci a b ci a b ci a3 a2 a a b3 b2 b b FA FA FA FA 4-bit adder ci co s co s co s co s co s3 s2 s s co s3 s2 s (a) s (b)

15 Express Sum and Carry as a function of P, G, D Define 3 new variable which ONLY depend on A, B Generate (G) = AB Propagate (P) = A B Delete = A B Can also derive expressions for S and C o based on D and P Note that we will be sometimes using an alternate definition for Propagate (P) = A + B

16 Carry-Bypass Adder C i, P G P G P 2 G 2 P 3 G 3 C o, C o, C o,2 FA FA FA FA C o,3 Also called Carry-Skip P G P G P 2 G 2 P 3 G 3 BP=P o P P 2 P 3 C i, C o, C o, C o,2 FA FA FA FA Multiplexer C o,3 Idea: If (P and P and P2 and P3 = ) then C o3 = C, else kill or generate.

17 Carry-Select Adder Setup P,G "" "" Carry Propagation "" "" Carry Propagation C o,k- Multiplexer C o,k+3 Sum Generation Carry Vector

18 Carry Select Adder: Critical Path Bit 3 Bit 4 7 Bit 8 Bit 2 5 Setup Setup Setup Setup -Carry -Carry -Carry -Carry -Carry -Carry -Carry -Carry Multiplexer Multiplexer Multiplexer Multiplexer C i, C o,3 C o,7 C o, C o,5 Sum Generation Sum Generation Sum Generation Sum Generation S 3 S 4 7 S 8 S 2 5

19 Square Root Carry Select Bit - Bit 2-4 Bit 5-8 Bit 9-3 Bit 4-9 Setup Setup Setup Setup () "" "" Carry "" "" Carry "" "" Carry "" "" Carry () "" "" Carry "" "" Carry "" "" Carry "" "" Carry (3) (3) (4) (5) (6) (4) (5) (6) (7) Multiplexer Multiplexer Multiplexer Multiplexer C i, Sum Generation Sum Generation Sum Generation Sum Generation S - S 2-4 S 5-8 S 9-3 (7) Mux (8) Sum S 4-9 (9)

20 Serial Adder Using a D F-F

21 Signed Binary Numbers + Ex) The number 9 represented in binary with eight bit +9 : -9 : (signed-magnitude representation) (signed- s-complement representation) (signed-2 s-complement representation)

22 Subtraction + Arithmetic Addition - signed-magnitude system follows the rules of ordinary arithmetic. - signed-complement system requires only addition Arithmetic Subtraction (±A)-(+B) = (±A)+(-B) (±A)-(-B) = (±A)+(+B)

23 Subtractor Built with an Adder + Using two s complement A B = A + (-B) A B = A + (two s complement of B) N-bit = A + invert_bits(b) + + So build subtractor using adder by inverting B s bits, and setting carry in to A Adder S B cin

24 Adder/Subtractor + Adder/Subtractor: control input determines whether add or subtract Can use 2x mux sub input passes either B or inverted B Alternatively, can use XOR gates if sub input is, B s bits pass through; if sub input is, XOR inverts B s bits A N-bit 2x A B Adder cin S B N-bit sub b7 b6 adder s B inputs sub

25 Counter: Ripple Counter LSB MSB Ripple Counter: Clock pulses are applied to the input stage

26 `timescale ns / ps // time unit = ns, time precision = ps HDL for Ripple Counter <Design Module> module Ripple_Counter_4bit (A3,A2,A,A, Count, Reset); output A3, A2, A, A; input Count, Reset; //Instantiate complementing flip-flop Comp_D_flip_flop F (A, Count, Reset); Comp_D_flip_flop F (A, A, Reset); Comp_D_flip_flop F2 (A2, A, Reset); Comp_D_flip_flop F3 (A3, A2, Reset); Endmodule //Complementing flip-flop with delay //Input to D flip-flop = Q' module Comp_D_flip_flop (Q, CLK, Reset); output Q; input CLK, Reset; reg Q; (negedge CLK, posedge Reset) if (Reset) Q <= 'b; else Q <= #2 ~Q; endmodule //Stimulus for testing ripple counter module testcounter; reg Count; reg Reset; wire A,A,A2,A3; //Instantiate ripple counter Ripple_Counter_4bit M (A3, A2, A, A, Count, Reset); always #5 Count = ~Count; initial begin Count = 'b; Reset = 'b; #4 Reset = 'b; end initial #2 $finish; endmodule <Test Module>

27 Logic Simulation Results for the previous HDL Code

28 Counter: BCD Ripple Counter State Diagram 3-decimal BCD counter BCD ripple counter

29 HDL for Synchronous Counter <Binary Counter> <Up-Down Binary Counter> module Binary_Counter_4_bit ( output reg [3:] A_count, input Count, // Active high to count CLK, // Positive edge sensitive Clear // Active low ); (posedge CLK, negedge Clear) if (~Clear) A_count <= 4'b; else if (Count) A_count <= A_count + 'b; else A_count <= A_count; // redundant statement endmodule module Binary_Counter_4_bit ( output reg [3:] A_count, input Up, // Active high Down, // Active high CLK, // Positive edge sensitive Clear // Active low ); (posedge CLK, negedge Clear) if (~Clear) A_count <= 4'b; else if (Up == b) A_count <= A_count + 'b; else if (Down == b) A_count <= A_count - 'b; else A_count <= A_count; // redundant statement endmodule

30 Synchronous Counter : Binary Counter with Parallel Load Input and Output Diagram Function Table Logic Diagram

31 HDL Code : Binary Counter with Parallel Load module Binary_Counter_4_Par_Load ( output reg [3:] A_count, // Data output output C_out, // Output carry input [3:] Data_in, // Data input input Count, // Active high to count Load, // Active high to load CLK, // Positive edge sensitive Clear // Active low ); assign C_out = Count & (~Load) & (A_count == 4'b); (posedge CLK, negedge Clear) if (~Clear) A_count <= 4'b; else if (Load) A_count <= Data_in; else if (Count) A_count <= A_count + 'b; else A_count <= A_count; // redundant statement endmodule

Digital Design with FPGAs. By Neeraj Kulkarni

Digital Design with FPGAs. By Neeraj Kulkarni Digital Design with FPGAs By Neeraj Kulkarni Some Basic Electronics Basic Elements: Gates: And, Or, Nor, Nand, Xor.. Memory elements: Flip Flops, Registers.. Techniques to design a circuit using basic

More information

REGISTER TRANSFER LANGUAGE

REGISTER TRANSFER LANGUAGE REGISTER TRANSFER LANGUAGE The operations executed on the data stored in the registers are called micro operations. Classifications of micro operations Register transfer micro operations Arithmetic micro

More information

FPGA Design Challenge :Techkriti 14 Digital Design using Verilog Part 1

FPGA Design Challenge :Techkriti 14 Digital Design using Verilog Part 1 FPGA Design Challenge :Techkriti 14 Digital Design using Verilog Part 1 Anurag Dwivedi Digital Design : Bottom Up Approach Basic Block - Gates Digital Design : Bottom Up Approach Gates -> Flip Flops Digital

More information

Chap 6 Introduction to HDL (d)

Chap 6 Introduction to HDL (d) Design with Verilog Chap 6 Introduction to HDL (d) Credit to: MD Rizal Othman Faculty of Electrical & Electronics Engineering Universiti Malaysia Pahang Ext: 6036 VERILOG HDL Basic Unit A module Module

More information

DIGITAL SYSTEM DESIGN

DIGITAL SYSTEM DESIGN DIGITAL SYSTEM DESIGN Prepared By: Engr. Yousaf Hameed Lab Engineer BASIC ELECTRICAL & DIGITAL SYSTEMS LAB DEPARTMENT OF ELECTRICAL ENGINEERING Digital System Design 1 Name: Registration No: Roll No: Semester:

More information

Microcomputers. Outline. Number Systems and Digital Logic Review

Microcomputers. Outline. Number Systems and Digital Logic Review Microcomputers Number Systems and Digital Logic Review Lecture 1-1 Outline Number systems and formats Common number systems Base Conversion Integer representation Signed integer representation Binary coded

More information

Synthesis of Combinational and Sequential Circuits with Verilog

Synthesis of Combinational and Sequential Circuits with Verilog Synthesis of Combinational and Sequential Circuits with Verilog What is Verilog? Hardware description language: Are used to describe digital system in text form Used for modeling, simulation, design Two

More information

Arithmetic Logic Unit. Digital Computer Design

Arithmetic Logic Unit. Digital Computer Design Arithmetic Logic Unit Digital Computer Design Arithmetic Circuits Arithmetic circuits are the central building blocks of computers. Computers and digital logic perform many arithmetic functions: addition,

More information

Lecture Topics. Announcements. Today: Integer Arithmetic (P&H ) Next: continued. Consulting hours. Introduction to Sim. Milestone #1 (due 1/26)

Lecture Topics. Announcements. Today: Integer Arithmetic (P&H ) Next: continued. Consulting hours. Introduction to Sim. Milestone #1 (due 1/26) Lecture Topics Today: Integer Arithmetic (P&H 3.1-3.4) Next: continued 1 Announcements Consulting hours Introduction to Sim Milestone #1 (due 1/26) 2 1 Overview: Integer Operations Internal representation

More information

Real Digital Problem Set #6

Real Digital Problem Set #6 Real igital Problem et #6. (2 points) ketch a block diagram for a magnitude comparator bit-slice circuit. Create K-maps to define the bit-slice circuit, and use them to find optimal logic equations. ketch

More information

Digital Design (VIMIAA01) Introduction to the Verilog HDL

Digital Design (VIMIAA01) Introduction to the Verilog HDL BUDAPEST UNIVERSITY OF TECHNOLOGY AND ECONOMICS FACULTY OF ELECTRICAL ENGINEERING AND INFORMATICS DEPARTMENT OF MEASUREMENT AND INFORMATION SYSTEMS Digital Design (VIMIAA01) Introduction to the Verilog

More information

a, b sum module add32 sum vector bus sum[31:0] sum[0] sum[31]. sum[7:0] sum sum overflow module add32_carry assign

a, b sum module add32 sum vector bus sum[31:0] sum[0] sum[31]. sum[7:0] sum sum overflow module add32_carry assign I hope you have completed Part 1 of the Experiment. This lecture leads you to Part 2 of the experiment and hopefully helps you with your progress to Part 2. It covers a number of topics: 1. How do we specify

More information

UNIT II - COMBINATIONAL LOGIC Part A 2 Marks. 1. Define Combinational circuit A combinational circuit consist of logic gates whose outputs at anytime are determined directly from the present combination

More information

University of Toronto Faculty of Applied Science and Engineering Edward S. Rogers Sr. Department of Electrical and Computer Engineering

University of Toronto Faculty of Applied Science and Engineering Edward S. Rogers Sr. Department of Electrical and Computer Engineering University of Toronto Faculty of Applied Science and Engineering Edward S. Rogers Sr. Department of Electrical and Computer Engineering Final Examination ECE 241F - Digital Systems Examiners: S. Brown,

More information

RTL Design (Using ASM/SM Chart)

RTL Design (Using ASM/SM Chart) Digital Circuit Design and Language RTL Design (Using ASM/SM Chart) Chang, Ik Joon Kyunghee University Process of Logic Simulation and Synthesis Design Entry HDL Description Logic Simulation Functional

More information

UNIT-III REGISTER TRANSFER LANGUAGE AND DESIGN OF CONTROL UNIT

UNIT-III REGISTER TRANSFER LANGUAGE AND DESIGN OF CONTROL UNIT UNIT-III 1 KNREDDY UNIT-III REGISTER TRANSFER LANGUAGE AND DESIGN OF CONTROL UNIT Register Transfer: Register Transfer Language Register Transfer Bus and Memory Transfers Arithmetic Micro operations Logic

More information

ELCT 501: Digital System Design

ELCT 501: Digital System Design ELCT 501: Digital System Lecture 4: CAD tools (Continued) Dr. Mohamed Abd El Ghany, Basic VHDL Concept Via an Example Problem: write VHDL code for 1-bit adder 4-bit adder 2 1-bit adder Inputs: A (1 bit)

More information

Arithmetic Circuits. Design of Digital Circuits 2014 Srdjan Capkun Frank K. Gürkaynak.

Arithmetic Circuits. Design of Digital Circuits 2014 Srdjan Capkun Frank K. Gürkaynak. Arithmetic Circuits Design of Digital Circuits 2014 Srdjan Capkun Frank K. Gürkaynak http://www.syssec.ethz.ch/education/digitaltechnik_14 Adapted from Digital Design and Computer Architecture, David Money

More information

Department of Computer Science & Engineering. Lab Manual DIGITAL LAB. Class: 2nd yr, 3rd sem SYLLABUS

Department of Computer Science & Engineering. Lab Manual DIGITAL LAB. Class: 2nd yr, 3rd sem SYLLABUS Department of Computer Science & Engineering Lab Manual 435 DIGITAL LAB Class: 2nd yr, 3rd sem SYLLABUS. Verification of Boolean theorems using digital logic gates. 2. Design and implementation of code

More information

Hardware Description Language VHDL (1) Introduction

Hardware Description Language VHDL (1) Introduction Hardware Description Language VHDL (1) Introduction Digital Radiation Measurement and Spectroscopy NE/RHP 537 Introduction Hardware description language (HDL) Intended to describe circuits textually, for

More information

Injntu.com Injntu.com Injntu.com R16

Injntu.com Injntu.com Injntu.com R16 1. a) What are the three methods of obtaining the 2 s complement of a given binary (3M) number? b) What do you mean by K-map? Name it advantages and disadvantages. (3M) c) Distinguish between a half-adder

More information

Digital Logic & Computer Design CS Professor Dan Moldovan Spring 2010

Digital Logic & Computer Design CS Professor Dan Moldovan Spring 2010 Digital Logic & Computer Design CS 434 Professor Dan Moldovan Spring 2 Copyright 27 Elsevier 5- Chapter 5 :: Digital Building Blocks Digital Design and Computer Architecture David Money Harris and Sarah

More information

Federal Urdu University of Arts, Science and Technology, Islamabad VLSI SYSTEM DESIGN. Prepared By: Engr. Yousaf Hameed.

Federal Urdu University of Arts, Science and Technology, Islamabad VLSI SYSTEM DESIGN. Prepared By: Engr. Yousaf Hameed. VLSI SYSTEM DESIGN Prepared By: Engr. Yousaf Hameed Lab Engineer BASIC ELECTRICAL & DIGITAL SYSTEMS LAB DEPARTMENT OF ELECTRICAL ENGINEERING VLSI System Design 1 LAB 01 Schematic Introduction to DSCH and

More information

Chapter 5. Digital Design and Computer Architecture, 2 nd Edition. David Money Harris and Sarah L. Harris. Chapter 5 <1>

Chapter 5. Digital Design and Computer Architecture, 2 nd Edition. David Money Harris and Sarah L. Harris. Chapter 5 <1> Chapter 5 Digital Design and Computer Architecture, 2 nd Edition David Money Harris and Sarah L. Harris Chapter 5 Chapter 5 :: Topics Introduction Arithmetic Circuits umber Systems Sequential Building

More information

Lecture 32: SystemVerilog

Lecture 32: SystemVerilog Lecture 32: SystemVerilog Outline SystemVerilog module adder(input logic [31:0] a, input logic [31:0] b, output logic [31:0] y); assign y = a + b; Note that the inputs and outputs are 32-bit busses. 17:

More information

CO Computer Architecture and Programming Languages CAPL. Lecture 9

CO Computer Architecture and Programming Languages CAPL. Lecture 9 CO20-320241 Computer Architecture and Programming Languages CAPL Lecture 9 Dr. Kinga Lipskoch Fall 2017 A Four-bit Number Circle CAPL Fall 2017 2 / 38 Functional Parts of an ALU CAPL Fall 2017 3 / 38 Addition

More information

Chapter 3: part 3 Binary Subtraction

Chapter 3: part 3 Binary Subtraction Chapter 3: part 3 Binary Subtraction Iterative combinational circuits Binary adders Half and full adders Ripple carry and carry lookahead adders Binary subtraction Binary adder-subtractors Signed binary

More information

Code No: R Set No. 1

Code No: R Set No. 1 Code No: R059210504 Set No. 1 II B.Tech I Semester Regular Examinations, November 2006 DIGITAL LOGIC DESIGN ( Common to Computer Science & Engineering, Information Technology and Computer Science & Systems

More information

EXPERIMENT #8: BINARY ARITHMETIC OPERATIONS

EXPERIMENT #8: BINARY ARITHMETIC OPERATIONS EE 2 Lab Manual, EE Department, KFUPM EXPERIMENT #8: BINARY ARITHMETIC OPERATIONS OBJECTIVES: Design and implement a circuit that performs basic binary arithmetic operations such as addition, subtraction,

More information

Abi Farsoni, Department of Nuclear Engineering and Radiation Health Physics, Oregon State University

Abi Farsoni, Department of Nuclear Engineering and Radiation Health Physics, Oregon State University Hardware description language (HDL) Intended to describe circuits textually, for a computer to read Evolved starting in the 1970s and 1980s Popular languages today include: VHDL Defined in 1980s by U.S.

More information

Introduction to Verilog HDL. Verilog 1

Introduction to Verilog HDL. Verilog 1 Introduction to HDL Hardware Description Language (HDL) High-Level Programming Language Special constructs to model microelectronic circuits Describe the operation of a circuit at various levels of abstraction

More information

Verilog for Synthesis Ing. Pullini Antonio

Verilog for Synthesis Ing. Pullini Antonio Verilog for Synthesis Ing. Pullini Antonio antonio.pullini@epfl.ch Outline Introduction to Verilog HDL Describing combinational logic Inference of basic combinational blocks Describing sequential circuits

More information

Verilog Fundamentals. Shubham Singh. Junior Undergrad. Electrical Engineering

Verilog Fundamentals. Shubham Singh. Junior Undergrad. Electrical Engineering Verilog Fundamentals Shubham Singh Junior Undergrad. Electrical Engineering VERILOG FUNDAMENTALS HDLs HISTORY HOW FPGA & VERILOG ARE RELATED CODING IN VERILOG HDLs HISTORY HDL HARDWARE DESCRIPTION LANGUAGE

More information

Number Systems. Readings: , Problem: Implement simple pocket calculator Need: Display, adders & subtractors, inputs

Number Systems. Readings: , Problem: Implement simple pocket calculator Need: Display, adders & subtractors, inputs Number Systems Readings: 3-3.3.3, 3.3.5 Problem: Implement simple pocket calculator Need: Display, adders & subtractors, inputs Display: Seven segment displays Inputs: Switches Missing: Way to implement

More information

Writing Circuit Descriptions 8

Writing Circuit Descriptions 8 8 Writing Circuit Descriptions 8 You can write many logically equivalent descriptions in Verilog to describe a circuit design. However, some descriptions are more efficient than others in terms of the

More information

R a) Simplify the logic functions from binary to seven segment display code converter (8M) b) Simplify the following using Tabular method

R a) Simplify the logic functions from binary to seven segment display code converter (8M) b) Simplify the following using Tabular method SET - 1 1. a) Convert the decimal number 250.5 to base 3, base 4 b) Write and prove de-morgan laws c) Implement two input EX-OR gate from 2 to 1 multiplexer (3M) d) Write the demerits of PROM (3M) e) What

More information

Combinational Logic II

Combinational Logic II Combinational Logic II Ranga Rodrigo July 26, 2009 1 Binary Adder-Subtractor Digital computers perform variety of information processing tasks. Among the functions encountered are the various arithmetic

More information

Experiment 7 Arithmetic Circuits Design and Implementation

Experiment 7 Arithmetic Circuits Design and Implementation Experiment 7 Arithmetic Circuits Design and Implementation Introduction: Addition is just what you would expect in computers. Digits are added bit by bit from right to left, with carries passed to the

More information

One and a half hours. Section A is COMPULSORY UNIVERSITY OF MANCHESTER SCHOOL OF COMPUTER SCIENCE

One and a half hours. Section A is COMPULSORY UNIVERSITY OF MANCHESTER SCHOOL OF COMPUTER SCIENCE One and a half hours Section A is COMPULSORY UNIVERSITY OF MANCHESTER SCHOOL OF COMPUTER SCIENCE Fundamentals of Computer Engineering Date: Thursday 21st January 2016 Time: 14:00-15:30 Answer BOTH Questions

More information

Combinational Logic Circuits

Combinational Logic Circuits Combinational Logic Circuits By Dr. M. Hebaishy Digital Logic Design Ch- Rem.!) Types of Logic Circuits Combinational Logic Memoryless Outputs determined by current values of inputs Sequential Logic Has

More information

Lecture 15: System Modeling and Verilog

Lecture 15: System Modeling and Verilog Lecture 15: System Modeling and Verilog Slides courtesy of Deming Chen Intro. VLSI System Design Outline Outline Modeling Digital Systems Introduction to Verilog HDL Use of Verilog HDL in Synthesis Reading

More information

N-input EX-NOR gate. N-output inverter. N-input NOR gate

N-input EX-NOR gate. N-output inverter. N-input NOR gate Hardware Description Language HDL Introduction HDL is a hardware description language used to design and document electronic systems. HDL allows designers to design at various levels of abstraction. It

More information

ECE 341 Midterm Exam

ECE 341 Midterm Exam ECE 341 Midterm Exam Time allowed: 75 minutes Total Points: 75 Points Scored: Name: Problem No. 1 (8 points) For each of the following statements, indicate whether the statement is TRUE or FALSE: (a) A

More information

CSE140L: Components and Design Techniques for Digital Systems Lab. Verilog HDL. Instructor: Mohsen Imani UC San Diego. Source: Eric Crabill, Xilinx

CSE140L: Components and Design Techniques for Digital Systems Lab. Verilog HDL. Instructor: Mohsen Imani UC San Diego. Source: Eric Crabill, Xilinx CSE4L: Components and Design Techniques for Digital Systems Lab Verilog HDL Instructor: Mohsen Imani UC San Diego Source: Eric Crabill, Xilinx System Tasks The $ sign denotes Verilog system tasks, there

More information

EE 8351 Digital Logic Circuits Ms.J.Jayaudhaya, ASP/EEE

EE 8351 Digital Logic Circuits Ms.J.Jayaudhaya, ASP/EEE EE 8351 Digital Logic Circuits Ms.J.Jayaudhaya, ASP/EEE 1 Logic circuits for digital systems may be combinational or sequential. A combinational circuit consists of input variables, logic gates, and output

More information

CSE140L: Components and Design Techniques for Digital Systems Lab. Verilog HDL. Instructor: Mohsen Imani UC San Diego. Source: Eric Crabill, Xilinx

CSE140L: Components and Design Techniques for Digital Systems Lab. Verilog HDL. Instructor: Mohsen Imani UC San Diego. Source: Eric Crabill, Xilinx CSE140L: Components and Design Techniques for Digital Systems Lab Verilog HDL Instructor: Mohsen Imani UC San Diego Source: Eric Crabill, Xilinx 1 Hardware description languages Used to describe & model

More information

DIGITAL ELECTRONICS. P41l 3 HOURS

DIGITAL ELECTRONICS. P41l 3 HOURS UNIVERSITY OF SWAZILAND FACUL TY OF SCIENCE AND ENGINEERING DEPARTMENT OF PHYSICS MAIN EXAMINATION 2015/16 TITLE OF PAPER: COURSE NUMBER: TIME ALLOWED: INSTRUCTIONS: DIGITAL ELECTRONICS P41l 3 HOURS ANSWER

More information

EPC6055 Digital Integrated Circuits EXAM 1 Fall Semester 2013

EPC6055 Digital Integrated Circuits EXAM 1 Fall Semester 2013 EPC6055 Digital Integrated Circuits EXAM 1 Fall Semester 2013 Print Here Student ID Signature This is a closed book exam. The exam is to be completed in one-hundred ten (110) minutes. Don t use scratch

More information

Chapter 5 Registers & Counters

Chapter 5 Registers & Counters University of Wisconsin - Madison ECE/Comp Sci 352 Digital Systems Fundamentals Kewal K. Saluja and Yu Hen Hu Spring 2002 Chapter 5 Registers & Counters Originals by: Charles R. Kime Modified for course

More information

Modeling Sequential Circuits in Verilog

Modeling Sequential Circuits in Verilog Modeling Sequential Circuits in Verilog COE 202 Digital Logic Design Dr. Muhamed Mudawar King Fahd University of Petroleum and Minerals Presentation Outline Modeling Latches and Flip-Flops Blocking versus

More information

11.1. Unit 11. Adders & Arithmetic Circuits

11.1. Unit 11. Adders & Arithmetic Circuits . Unit s & Arithmetic Circuits .2 Learning Outcomes I understand what gates are used to design half and full adders I can build larger arithmetic circuits from smaller building blocks ADDER.3 (+) Register.4

More information

Code No: R Set No. 1

Code No: R Set No. 1 Code No: R059210504 Set No. 1 II B.Tech I Semester Regular Examinations, November 2007 DIGITAL LOGIC DESIGN ( Common to Computer Science & Engineering, Information Technology and Computer Science & Systems

More information

*Instruction Matters: Purdue Academic Course Transformation. Introduction to Digital System Design. Module 4 Arithmetic and Computer Logic Circuits

*Instruction Matters: Purdue Academic Course Transformation. Introduction to Digital System Design. Module 4 Arithmetic and Computer Logic Circuits Purdue IM:PACT* Fall 2018 Edition *Instruction Matters: Purdue Academic Course Transformation Introduction to Digital System Design Module 4 Arithmetic and Computer Logic Circuits Glossary of Common Terms

More information

EE 109L Review. Name: Solutions

EE 109L Review. Name: Solutions EE 9L Review Name: Solutions Closed Book / Score:. Short Answer (6 pts.) a. Storing temporary values in (memory / registers) is preferred due to the (increased / decreased) access time. b. True / False:

More information

Systems Programming. Lecture 2 Review of Computer Architecture I

Systems Programming.   Lecture 2 Review of Computer Architecture I Systems Programming www.atomicrhubarb.com/systems Lecture 2 Review of Computer Architecture I In The Book Patt & Patel Chapter 1,2,3 (review) Outline Binary Bit Numbering Logical operations 2's complement

More information

Introduction to Verilog/System Verilog

Introduction to Verilog/System Verilog NTUEE DCLAB Feb. 27, 2018 Introduction to Verilog/System Verilog Presenter: Yao-Pin Wang 王耀斌 Advisor: Prof. Chia-Hsiang Yang 楊家驤 Dept. of Electrical Engineering, NTU National Taiwan University What is

More information

Arithmetic Circuits. Nurul Hazlina Adder 2. Multiplier 3. Arithmetic Logic Unit (ALU) 4. HDL for Arithmetic Circuit

Arithmetic Circuits. Nurul Hazlina Adder 2. Multiplier 3. Arithmetic Logic Unit (ALU) 4. HDL for Arithmetic Circuit Nurul Hazlina 1 1. Adder 2. Multiplier 3. Arithmetic Logic Unit (ALU) 4. HDL for Arithmetic Circuit Nurul Hazlina 2 Introduction 1. Digital circuits are frequently used for arithmetic operations 2. Fundamental

More information

BUILDING BLOCKS OF A BASIC MICROPROCESSOR. Part 1 PowerPoint Format of Lecture 3 of Book

BUILDING BLOCKS OF A BASIC MICROPROCESSOR. Part 1 PowerPoint Format of Lecture 3 of Book BUILDING BLOCKS OF A BASIC MICROPROCESSOR Part PowerPoint Format of Lecture 3 of Book Decoder Tri-state device Full adder, full subtractor Arithmetic Logic Unit (ALU) Memories Example showing how to write

More information

EXPERIMENT NUMBER 11 REGISTERED ALU DESIGN

EXPERIMENT NUMBER 11 REGISTERED ALU DESIGN 11-1 EXPERIMENT NUMBER 11 REGISTERED ALU DESIGN Purpose Extend the design of the basic four bit adder to include other arithmetic and logic functions. References Wakerly: Section 5.1 Materials Required

More information

Computer Aided Design Basic Syntax Gate Level Modeling Behavioral Modeling. Verilog

Computer Aided Design Basic Syntax Gate Level Modeling Behavioral Modeling. Verilog Verilog Radek Pelánek and Šimon Řeřucha Contents 1 Computer Aided Design 2 Basic Syntax 3 Gate Level Modeling 4 Behavioral Modeling Computer Aided Design Hardware Description Languages (HDL) Verilog C

More information

A Verilog Primer. An Overview of Verilog for Digital Design and Simulation

A Verilog Primer. An Overview of Verilog for Digital Design and Simulation A Verilog Primer An Overview of Verilog for Digital Design and Simulation John Wright Vighnesh Iyer Department of Electrical Engineering and Computer Sciences College of Engineering, University of California,

More information

Verilog Tutorial (Structure, Test)

Verilog Tutorial (Structure, Test) Digital Circuit Design and Language Verilog Tutorial (Structure, Test) Chang, Ik Joon Kyunghee University Hierarchical Design Top-down Design Methodology Bottom-up Design Methodology Module START Example)

More information

Two hours - online EXAM PAPER MUST NOT BE REMOVED FROM THE EXAM ROOM UNIVERSITY OF MANCHESTER SCHOOL OF COMPUTER SCIENCE

Two hours - online EXAM PAPER MUST NOT BE REMOVED FROM THE EXAM ROOM UNIVERSITY OF MANCHESTER SCHOOL OF COMPUTER SCIENCE COMP 12111 Two hours - online This paper version is made available as a backup In this event, only MCQ answers written in the boxes on the exam paper will be marked. EXAM PAPER MUST NOT BE REMOVED FROM

More information

Combinational Circuit Design

Combinational Circuit Design Modeling Combinational Circuits with Verilog Prof. Chien-Nan Liu TEL: 3-42275 ext:34534 Email: jimmy@ee.ncu.edu.tw 3- Combinational Circuit Design Outputs are functions of inputs inputs Combinational Circuit

More information

ENEE245 Digital Circuits and Systems Lab Manual

ENEE245 Digital Circuits and Systems Lab Manual ENEE245 Digital Circuits and Systems Lab Manual Department of Engineering, Physical & Computer Sciences Montgomery College Version 1.1 Copyright Prof. Lan Xiang (Do not distribute without permission) 1

More information

yamin/

yamin/ http://cis.k.hosei.ac.jp/ yamin/ Verilog HDL p.1/76 HDL Verilog HDL IEEE Standard 1364-1995 (Verilog-1995) IEEE Standard 1364-2001 (Verilog-2001) VHDL VHSIC HDL IEEE Standard 1076-1987 AHDL Altera HDL

More information

ENEE245 Digital Circuits and Systems Lab Manual

ENEE245 Digital Circuits and Systems Lab Manual ENEE245 Digital Circuits and Systems Lab Manual Department of Engineering, Physical & Computer Sciences Montgomery College Modified Fall 2017 Copyright Prof. Lan Xiang (Do not distribute without permission)

More information

In this lecture, we will go beyond the basic Verilog syntax and examine how flipflops and other clocked circuits are specified.

In this lecture, we will go beyond the basic Verilog syntax and examine how flipflops and other clocked circuits are specified. 1 In this lecture, we will go beyond the basic Verilog syntax and examine how flipflops and other clocked circuits are specified. I will also introduce the idea of a testbench as part of a design specification.

More information

Register Transfer Level in Verilog: Part I

Register Transfer Level in Verilog: Part I Source: M. Morris Mano and Michael D. Ciletti, Digital Design, 4rd Edition, 2007, Prentice Hall. Register Transfer Level in Verilog: Part I Lan-Da Van ( 范倫達 ), Ph. D. Department of Computer Science National

More information

Digital Fundamentals. Lab 6 2 s Complement / Digital Calculator

Digital Fundamentals. Lab 6 2 s Complement / Digital Calculator Richland College Engineering Technology Rev. 0. Donham Rev. 1 (7/2003) J. Horne Rev. 2 (1/2008) J. radbury Digital Fundamentals CETT 1425 Lab 6 2 s Complement / Digital Calculator Name: Date: Objectives:

More information

Contents. Chapter 9 Datapaths Page 1 of 28

Contents. Chapter 9 Datapaths Page 1 of 28 Chapter 9 Datapaths Page of 2 Contents Contents... 9 Datapaths... 2 9. General Datapath... 3 9.2 Using a General Datapath... 5 9.3 Timing Issues... 7 9.4 A More Complex General Datapath... 9 9.5 VHDL for

More information

Digital Design Using Digilent FPGA Boards -- Verilog / Active-HDL Edition

Digital Design Using Digilent FPGA Boards -- Verilog / Active-HDL Edition Digital Design Using Digilent FPGA Boards -- Verilog / Active-HDL Edition Table of Contents 1. Introduction to Digital Logic 1 1.1 Background 1 1.2 Digital Logic 5 1.3 Verilog 8 2. Basic Logic Gates 9

More information

Contents. Appendix D Verilog Summary Page 1 of 16

Contents. Appendix D Verilog Summary Page 1 of 16 Appix D Verilog Summary Page 1 of 16 Contents Appix D Verilog Summary... 2 D.1 Basic Language Elements... 2 D.1.1 Keywords... 2 D.1.2 Comments... 2 D.1.3 Identifiers... 2 D.1.4 Numbers and Strings... 3

More information

Register Transfer Level

Register Transfer Level Register Transfer Level Something between the logic level and the architecture level A convenient way to describe synchronous sequential systems State diagrams for pros Hierarchy of Designs The design

More information

EECS150 - Digital Design Lecture 4 - Verilog Introduction. Outline

EECS150 - Digital Design Lecture 4 - Verilog Introduction. Outline EECS150 - Digital Design Lecture 4 - Verilog Introduction Feb 3, 2009 John Wawrzynek Spring 2009 EECS150 - Lec05-Verilog Page 1 Outline Background and History of Hardware Description Brief Introduction

More information

Introduction To Verilog Design. Chun-Hung Chou

Introduction To Verilog Design. Chun-Hung Chou Introduction To Verilog Design Chun-Hung Chou 1 Outline Typical Design Flow Design Method Lexical Convention Data Type Data Assignment Event Control Conditional Description Register Description Synthesizable

More information

Chapter 4. Combinational Logic

Chapter 4. Combinational Logic Chapter 4. Combinational Logic Tong In Oh 1 4.1 Introduction Combinational logic: Logic gates Output determined from only the present combination of inputs Specified by a set of Boolean functions Sequential

More information

Chapter 9: Sequential Logic Modules

Chapter 9: Sequential Logic Modules Chapter 9: Sequential Logic Modules Prof. Soo-Ik Chae Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 9-1 Objectives After completing this chapter, you will be able

More information

R10. II B. Tech I Semester, Supplementary Examinations, May

R10. II B. Tech I Semester, Supplementary Examinations, May SET - 1 1. a) Convert the following decimal numbers into an equivalent binary numbers. i) 53.625 ii) 4097.188 iii) 167 iv) 0.4475 b) Add the following numbers using 2 s complement method. i) -48 and +31

More information

Why Should I Learn This Language? VLSI HDL. Verilog-2

Why Should I Learn This Language? VLSI HDL. Verilog-2 Verilog Why Should I Learn This Language? VLSI HDL Verilog-2 Different Levels of Abstraction Algorithmic the function of the system RTL the data flow the control signals the storage element and clock Gate

More information

Topics. Midterm Finish Chapter 7

Topics. Midterm Finish Chapter 7 Lecture 9 Topics Midterm Finish Chapter 7 ROM (review) Memory device in which permanent binary information is stored. Example: 32 x 8 ROM Five input lines (2 5 = 32) 32 outputs, each representing a memory

More information

This Lecture. Some components (useful for the homework) Verilog HDL (will continue next lecture)

This Lecture. Some components (useful for the homework) Verilog HDL (will continue next lecture) Last Lecture The basic component of a digital circuit is the MOS transistor Transistor have instrinsic resistance and capacitance, so voltage values in the circuit take some time to change ( delay ) There

More information

CSE140L: Components and Design Techniques for Digital Systems Lab

CSE140L: Components and Design Techniques for Digital Systems Lab CSE140L: Components and Design Techniques for Digital Systems Lab Tajana Simunic Rosing Source: Vahid, Katz, Culler 1 Announcements & Outline Lab 4 due; demo signup times listed on the cse140l site Check

More information

HDL for Combinational Circuits. ENEL211 Digital Technology

HDL for Combinational Circuits. ENEL211 Digital Technology HDL for Combinational Circuits ENEL211 Digital Technology Lecture Outline Vectors Modular design Tri-state gates Dataflow modelling Behavioural Modelling Vectors Often we want multi-bit quantities in digital

More information

Verilog Coding Guideline

Verilog Coding Guideline Verilog Coding Guideline Digital Circuit Lab TA: Po-Chen Wu Outline Introduction to Verilog HDL Verilog Syntax Combinational and Sequential Logics Module Hierarchy Write Your Design Finite State Machine

More information

CHAPTER 4: Register Transfer Language and Microoperations

CHAPTER 4: Register Transfer Language and Microoperations CS 224: Computer Organization S.KHABET CHAPTER 4: Register Transfer Language and Microoperations Outline Register Transfer Language Register Transfer Bus and Memory Transfers Arithmetic Microoperations

More information

Synthesis of Language Constructs. 5/10/04 & 5/13/04 Hardware Description Languages and Synthesis

Synthesis of Language Constructs. 5/10/04 & 5/13/04 Hardware Description Languages and Synthesis Synthesis of Language Constructs 1 Nets Nets declared to be input or output ports are retained Internal nets may be eliminated due to logic optimization User may force a net to exist trireg, tri0, tri1

More information

Digital Integrated Circuits

Digital Integrated Circuits Digital Integrated Circuits Lecture 4 Jaeyong Chung System-on-Chips (SoC) Laboratory Incheon National University BCD TO EXCESS-3 CODE CONVERTER 0100 0101 +0011 +0011 0111 1000 LSB received first Chung

More information

DIGITAL SYSTEM DESIGN

DIGITAL SYSTEM DESIGN DIGITAL SYSTEM DESIGN Prepared By: Engr. Yousaf Hameed Lab Engineer BASIC ELECTRICAL & DIGITAL SYSTEMS LAB DEPARTMENT OF ELECTRICAL ENGINEERING Digital System Design 1 Name: Registration No: Roll No: Semester:

More information

Verilog HDL. Gate-Level Modeling

Verilog HDL. Gate-Level Modeling Verilog HDL Verilog is a concurrent programming language unlike C, which is sequential in nature. block - executes once at time 0. If there is more then one block, each execute concurrently always block

More information

B.Tech II Year I Semester (R13) Regular Examinations December 2014 DIGITAL LOGIC DESIGN

B.Tech II Year I Semester (R13) Regular Examinations December 2014 DIGITAL LOGIC DESIGN B.Tech II Year I Semester () Regular Examinations December 2014 (Common to IT and CSE) (a) If 1010 2 + 10 2 = X 10, then X is ----- Write the first 9 decimal digits in base 3. (c) What is meant by don

More information

Chapter 9: Sequential Logic Modules

Chapter 9: Sequential Logic Modules Chapter 9: Sequential Logic Modules Prof. Ming-Bo Lin Department of Electronic Engineering National Taiwan University of Science and Technology Digital System Designs and Practices Using Verilog HDL and

More information

ENGN1640: Design of Computing Systems Topic 02: Design/Lab Foundations

ENGN1640: Design of Computing Systems Topic 02: Design/Lab Foundations ENGN1640: Design of Computing Systems Topic 02: Design/Lab Foundations Professor Sherief Reda http://scale.engin.brown.edu School of Engineering Brown University Spring 2017 1 Topics 1. Programmable logic

More information

CSE140L: Components and Design

CSE140L: Components and Design CSE140L: Components and Design Techniques for Digital Systems Lab Tajana Simunic Rosing Source: Vahid, Katz, Culler 1 Grade distribution: 70% Labs 35% Lab 4 30% Lab 3 20% Lab 2 15% Lab 1 30% Final exam

More information

EE 109L Final Review

EE 109L Final Review EE 09L Final Review Name: Closed Book / Score:. Short Answer (6 pts.) a. Storing temporary values in (memory / registers) is preferred due to the (increased / decreased) access time. b. True / False: A

More information

EECS150 - Digital Design Lecture 5 - Verilog Logic Synthesis

EECS150 - Digital Design Lecture 5 - Verilog Logic Synthesis EECS150 - Digital Design Lecture 5 - Verilog Logic Synthesis Jan 31, 2012 John Wawrzynek Spring 2012 EECS150 - Lec05-verilog_synth Page 1 Outline Quick review of essentials of state elements Finite State

More information

Verilog introduction. Embedded and Ambient Systems Lab

Verilog introduction. Embedded and Ambient Systems Lab Verilog introduction Embedded and Ambient Systems Lab Purpose of HDL languages Modeling hardware behavior Large part of these languages can only be used for simulation, not for hardware generation (synthesis)

More information

AN INTRODUCTION TO VERILOG HDL

AN INTRODUCTION TO VERILOG HDL AN INTRODUCTION TO VERILOG HDL Departamento de Tecnología Electrónica Universidad de Sevilla Rev.7 (feb 2013) Index Introducction Part I: combinational circuits Part II: sequential circuits 2 Introducción

More information

For Example: P: LOAD 5 R0. The command given here is used to load a data 5 to the register R0.

For Example: P: LOAD 5 R0. The command given here is used to load a data 5 to the register R0. Register Transfer Language Computers are the electronic devices which have several sets of digital hardware which are inter connected to exchange data. Digital hardware comprises of VLSI Chips which are

More information

HANSABA COLLEGE OF ENGINEERING & TECHNOLOGY (098) SUBJECT: DIGITAL ELECTRONICS ( ) Assignment

HANSABA COLLEGE OF ENGINEERING & TECHNOLOGY (098) SUBJECT: DIGITAL ELECTRONICS ( ) Assignment Assignment 1. What is multiplexer? With logic circuit and function table explain the working of 4 to 1 line multiplexer. 2. Implement following Boolean function using 8: 1 multiplexer. F(A,B,C,D) = (2,3,5,7,8,9,12,13,14,15)

More information