Quick Introduction to SystemVerilog: Sequental Logic

Transcription

1 ! Quick Introduction to SystemVerilog: Sequental Logic Lecture L Advanced Digital Design ECE Department Many elements Don Thomas, 24, used with permission with credit to G. Larson

2 Today Quick synopsis of Finite State Machines (FSM) Moore, Mealy Design process SystemVerilog for a Flip flop SystemVerilog for a FSM Exercise: Design, implement and synthesize a FSM 2

3 Designing FSMs: Step State Transition Diagrams represent FSMs at a high level of abstraction. Each state is represented by a circle A/, C/ 2. Each state is labeled with a symbolic name. An output value is specified for each state Reset B/ 3. A directed edge from state Sx to Sy indicates a potential transition 5. Whenever reset is asserted, the FSM transitions to a special initial state Each transition is labeled with input values that, should they be present, would cause the state to change from Sx to Sy 4. One of the state transitions occurs for each clock event 8-24 L9 3

4 What does it mean? E.g. -bit input, -bit output, 3-state FSM - trace the execution for input sequence after Reset - What will the output be? The next state? Reset A/, B/ C/ clock event State A A B B B C Output Input X Reset 8-24 L9 4

5 State Transition Diagram Example Things to note - Output is a function of state not input out = (state == B)? : ; - Next state is a function of current state and input Reset if (state == B && input == ) then next state is B else next state is C A/, B/ C/ An FSM is a 5-tuple - A set of states here {A, B, C} - A set of allowable inputs ( alphabet ) here {, } - A set of allowable outputs ( alphabet ) {, } - A next state function here a combinational fn of (state, input) - An output function here a combinational fn of (state) 8-24 L9 5

6 Reset Putting it in context A/, C/ inputs Next State Generator (comb logic) Current State Register Output Generator (comb logic) outputs B/ clock Let CS be current state and NS be next state if (Reset) NS=A else if (CS==A) if (Input==) NS=A else NS=B else if (CS==B) if (Input==) NS=C else NS=B else if (CS==C) NS=A 2-bit state register for example means A means B means C don t care Hmm, can you imagine describing these as always_comb blocks? Let CS be current state out = (CS == B)? : ; 8-24 L9 6

7 Moore vs. Mealy Machines At the start of this lecture - We said a machine s output was a function of the state Actually Two different types of FSMs - Moore machines: output = a fn of only state (We just did this) - Mealy machines: output = a fn of the state and the inputs Mealy machines = Moore + wire the only difference inputs Next State Generator (comb logic) Current State Register Output Generator (comb logic) outputs clock 8-24 L9 7

8 Mealy State Diagram and Table The state transition arcs must show the inputs/outputs Output is now a function of both state & input - If you re in state A the output is if the input is, and if the input is - If you re in state B, the output is different from above Reset A / / /,/ / C input/output / B Present state Next State X = X = Output X = X = A B C A C A B B A 8-24 L9 8

9 Mealy Output Notation Mealy outputs are a function of state and inputs Reset A In Out X Placing a truth table in each state is a bit clumsy - Though less confusing for new students As the transitions already have input specifications, we reuse them to describe outputs B In X Out C In Out X BE CAREFUL: Mealy notation is confusing! You don t have to actually take the transition for the output to occur 8-24 L9 9

10 Example: Series Recognizer Let s do one example in both Moore and Mealy - Want a series recognizer FSM that outputs a every time it detects sequence in input stream INPUT OUTPUT Moore State Transition Diagram Mealy State Transition Diagram R s? / s / s / R / s? / / s / 8-24 L9

11 Example: The Timing Is Different! INPUT OUTPUT INPUT OUTPUT Moore State Transition Diagram Mealy State Transition Diagram R s? / s / s / R / s? / / s / 8-24 L9

12 Example: Essential differences Moore - Need a state for reset that is also the last wasn t - Need a state for the last input was - Need a state for I just saw a after a I recognized a pattern Mealy - Need a state for reset which is also the last wasn t - Need a state for the last input was - Transitions get labeled with correct outputs, not the states - Notice that the start state is target of 2 transitions with different output values this is how we save that extra state - Outputs appear at different times wrt Moore machines The example is small - But you see the Mealy approach is different, results in one less state 8-24 L9 2

13 To infer a flip-flop Flip-flops are edge-triggered need to with posedge or negedge side effect every variable on the left-hand side assigned with a <= will be an edge triggered flip-flop (or vector of flip-flops) Some combinational logic can be specified in certain places module Dff (output logic Q, input clk, d, resetn); clk, negedge resetn) if (~resetn) Q <= ; else Q <= d; endmodule What happens on the clock edge is inferred it s the last (default) action. The assignment is made to a logic (or bit ) variable, not a reg as in old Verilog. Synthesis infers an FF Q, d, clk, and resetn are not keywords <= needed for synthesis and simulation SVbook 3. 3

14 New SystemVerilog Constructs A new flavor of always statement - clk) ; - this statement models a flip-flop or register - this statement will synthesize to a flip-flop or register clk) means to wait for the specified change on the listed signal posedge -to- negedge -to- module DFF (input logic d, clk, output logic q); clk) q <= d; endmodule: DFF Current state (Now) Next State (after clk) Clk D Q Q + X X X X X X 8-24 L2 4

15 Big Idea: Concurrent assignment What about that <=??? - Called non-blocking assignment Sometimes called concurrent, buffered or delayed assignment Use it to assign to a state value, like a flip-flop or register output module DFF (input logic d, clk, output logic q); clk) q <= d; endmodule: DFF <= is not less than or equal!! Why a new assignment type? - This models how an edge triggered flip-flop works All clock-triggered state updates in the design happen instantaneously, at the same time, indivisibly, you can t tell one happened before any other If your design has K flip-flops, then all K assignments happen instantaneously in simulation After all, in the physical hardware, the same clock triggers all K flip-flops and they change concurrently (and instantaneously)! 8-24 L2 5

16 What about reset? Asynchronous reset - happens anytime rstn becomes Trace behavior - anytime reset changes to, set q to - while reset remains, if the clock edge occurs, q still remains - when reset changes to, q remains until the next clock event module DFF_rst (input logic d, clk, rstn output logic q); clk, negedge rstn) if (~rstn) q <= ; else q <= d; endmodule: DFF_rst If reset asserted This is a list of what the always_ff block is sensitive to This is how to describe a flip-flop. Just do it this way! Copy it!!

17 How reset works reset is generally asynchronous... module Dff (output logic Q, input logic clk, d, resetn); clk, negedge resetn) if (~resetn) Q <= ; else Q <= d; endmodule : Dff... but could be rising edge module Dff (output logic Q, input logic clk, d, reset); clk, posedge reset) if (reset) Q <= ; else Q <= d; endmodule : Dff 8-24 L2 7

18 Finite State Machines Defined formally by - Set of states, including reset - set of input combinations not necessarily all 2 n are possible due to don t-cares - set of output combinations not necessarily all 2 n are possible - next state (δ) and output (λ) combinational functions - clock event (or clock domain) - reset signal R / A B / Legend s s i/a,b inputs next state logic / / C D Q D Q output logic x/ outputs MOC: starting in the reset state, the clock event causes the system to change to another (or same) state as defined by the δ function 8-24 L2 8

19 FSM in SystemVerilog Next State Logic Output Logic X Q D D Q Q Z Clk Q Q Q' D D Clk Q Q Q clock reset_l Two always_comb blocks (or continuous assigns) - one for the combinational next state logic - one for the output logic We ll have another always_ff block for the D flipflops 8-24 L2 9

20 Explicit FSM Style module myfsm2 (input logic clk, rstn, x, output logic z); logic [:] ns, cs; clk, negedge rstn) if (~rstn) cs <= ; else cs <= ns; always_comb begin ns[] = cs[] & x cs[] & x; ns[] = cs[] & x ~cs[] & x; end assign z = cs[] & cs[]; endmodule: myfsm2 Called explicit FSM style because everything is explicitly defined: state register, output logic, next state logic, and state assignment Done here as 3 blocks - The sequential part: generates current state (cs) from the next state (ns) synchronously - The next state generator: combinational logic to create the next state inputs (D, D) from the current state and input (x) - The output generator: combinational logic to create the output (z) from the current state

21 Where does clock come from? module clock (output logic clk); initial begin clk = ; forever # clk = ~clk; end endmodule: clock clk time = clk has value one time = clk = zero time = 2 clk = one In HW, the clock is driven from outside of the design A clock module - Used in simulation - Initialization to one (or zero) It will have this value when simulation starts (not x!) - Execution forever loop just keeps executing the statement # says to wait time units Every units clk gets ~clk Someplace else in the design must have a $finish!! 8-24 L2 2

22 enum enumerate for state encoding enum enumerate statement, similar to what is found in programming languages Below, 2-bit logic variables state and nextstate are defined A set of symbols are defined: ZERO, ONE, TWO, and THREE The bit patterns that represent these symbols are defined shown below These are strongly typed Can leave out type and size (integers with values starting at assumed) enum can also be typedef ed keyword labels and values enum logic [:] {ZERO = 2'd, ONE = 2'd, TWO = 2'd2, THREE = 2'd3} state, nextstate; type and size SVbook 3.4. declared variables 22

23 Style Points What are the logic components? module explicitfsm (output logic a, b, input ck, r_l, i); enum logic [:] {A=2'b, B=2'b, C=2'b} state, nextstate; One way to do state assignment Why set a to and later back to? but don t do that with b? Why ~r_l instead of switching the sense of the if-else? always_comb begin a = 'b; b = nextstate == A; if ((state == C) && i) a = 'b; end always_comb case (state) A: nextstate = (i)? B : A; B: nextstate = C; C: nextstate = (~i): A : C; default: nextstate = A; endcase ck, negedge r_l) if (~r_l) state <= A; else state <= nextstate; endmodule: explicitfsm Why have a default? 23

24 Other organizations module explicitfsm (output logic a, b, input ck, r_l, i); enum logic [:] {A=2'b, B=2'b, C=2'b} state, nextstate; always_comb begin a = 'b; b = nextstate == A; if ((state == C) && i) a = 'b; end always_comb case (state) A: nextstate = (i)? B : A; B: nextstate = C; C: nextstate = (~i): A : C; default: nextstate = A; endcase ck, negedge r_l) if (~r_l) state <= A; else state <= nextstate; endmodule: explicitfsm module explicitfsm (output logic a, b, input ck, r_l, i); enum logic [:] {A=2'b, B=2'b, C=2'b} state, nextstate; always_comb begin a = 'b; b = nextstate == A; if ((state == C) && i) a = 'b; end ck, negedge r_l) if (~r_l) state <= A; else case (state) A: state <= (i)? B : A; B: state <= C; C: state <= (~i): A : C; default: state <= A; endcase endmodule: explicitfsm This combines state and nextstate together. OKAY?? hmm, needs to change too. Why? 24

25 Combining parts of an explicit fsm Potential problem combining the output logic with the state update OK with a Mealy machine? OK with a Moore machine? module explicitfsm (output logic a, b, input ck, r_l, i); enum logic [:] {A=2'b, B=2'b, C=2'b} state, nextstate; always_comb begin a = 'b; b = nextstate == A; if ((state == C) && i) a = 'b; end always_comb case (state) A: nextstate = (i)? B : A; B: nextstate = C; C: nextstate = (~i): A : C; default: nextstate = A; endcase ck, negedge r_l) if (~r_l) state <= A; else state <= nextstate; endmodule: explicitfsm 25

26 Models of Computation R / A B A B C F / Legend s s i/a,b / x/ C / inputs next state logic D Q output logic outputs D Q Combinational Logic Where we ve been What are the assumptions about how new values are generated in each of these? specifically combinational logic and STDs Can think of this as the beginnings of a behavioral hierarchy What s next up? 26