SPIN part 2. Verification with LTL. Jaime Ramos. Departamento de Matemática, Técnico, ULisboa

Size: px
Start display at page:

Download "SPIN part 2. Verification with LTL. Jaime Ramos. Departamento de Matemática, Técnico, ULisboa"

Transcription

1 SPIN part 2 Verification with LTL Jaime Ramos Departamento de Matemática, Técnico, ULisboa Borrowed from slides by David Henriques, Técnico, ULisboa

2 LTL model checking How Spin works Checks non-empty intersection requires very little space in best case Works directly with Promela no explicit conversion to TS Must provide Spin with negation of property you want to prove. jspin does this for you.

3 LTL syntax in Spin ϕ ::= p true false ϕ bin_op ϕ un_op ϕ where p is a proposition (must start with a lower case letter) and un_op ::= [] always (G) <> sometimes (F) X next (X)! not ( ) bin_op ::= U until (U) && and ( ) or ( ) -> implication ( ) <-> equivalence ( )

4 Verifying safety properties Consider the processes bool wantp = false, wantq = false; byte critical = 0; active proctype P() { do :: wantp = true;!wantq; critical++; critical--; wantp = false; od } active proctype Q() { do :: wantq = true;!wantp; critical++; critical--; wantq = false; od }

5 We want to verify that mutual exclusion is guaranteed, that is, we want to check G (critical <= 1) However, critical<=1 is not a proposition. We can avoid this by defining, at the beginning #define mutex (critial <=1) Now, we can write, in LTL, G (mutex) that translates to Promela [](mutex)

6 In jspin Write the LTL formula in the text field provided. Select Translate. Ensure that Safety is selected from the pulldown menu. Select Verify. In recent versions of Spin, we may write []({critical <= 1}) Note: if your are using the command line then you need to write the negation of the formula you want to proof in a file with the extension.ltl.

7 Verifying liveness properties bool wantp = false, wantq = false, csp = false, csq = false; active proctype P() { do :: wantp = true; do :: wantq -> wantp = false; wantp = true :: else -> break od; csp = true; /* critical section */ csp = false; wantp = false od } active proctype Q() { do :: wantq = true; do :: wantp -> wantq = false; wantq = true :: else -> break od; csq = true; /* critical section */ csq = false; wantq = false od }

8 We can check that mutual exclusion is still preserved: []!(csp && csq) But now, we also want to check liveness properties. For instance, we want to check if process P will eventually enter its critical section. This is expressed by the LTL formula Fcsp that translates to Promela <>(csp)

9 In jspin Write the LTL formula in the text field provided. Select Translate. Ensure that Acceptance is selected from the pulldown menu. Ensure that the box labeled Weak fairness is checked. Select Verify.

10 In this case, the liveness property does not hold. The error message pan:1: acceptance cycle (at depth 18) is issued. A counterexample must be a reachable state within a cycle, falsifying the desired property. (see trail file).

11 Peterson s algorithm bool wantp = false, wantq = false; byte last = 1; active proctype P() { do active proctype Q() { do :: wantp = true; last = 1; :: wantq = true; last = 2; try: (wantq == false) (last == 2); try: (wantp == false) (last == 1); cs: wantp = false cs: wantq = false od } od }

12 Let us consider now some properties: Safety [](!(pcs && qcs)) No starvation Alternation (for process P) []<>(pcs) && []<>(qcs) [](ptry->(!qcs U(qcs U (!qcs U pcs))))

13 Recall the first example. Try to show some liveness properties: Process P will eventually enter its critical section Both processes enter the critical section infinitely often...

14 Bridge crossing Four soldiers who are heavily injured,need to cross a bridge. The bridge has been damaged and can only carry two soldiers at a time. They have only 1 hour to cross the bridge. The soldiers only have a single torch. List of the crossing times (one-way!) for each of the soldiers: soldier S0 5 min soldier S2 15 min soldier S1 10 min soldier S3 20 min Is there a strategy which gets all four soldiers to the safe side within 60 minutes?

15 We are going to use two processes, unsafe and safe to model the unsafe side and the safe side. Soldiers are sent from one side to the other via channels.

16 active proctype unsafe(){ bit here[n]; soldier s1,s2; here[0]=1; here[1]=1; here[2]=1; here[3]=1; } do :: select_soldier(s1); select_soldier(s2); unsafe_to_safe! s1,s2; IF all_gone -> break FI; safe_to_unsafe? s1; here[s1]=1; stopwatch! s1 ; od

17 active proctype safe(){ bit here[n]; soldier s1,s2; } do :: unsafe_to_safe? s1,s2; here[s1]=1; here[s2]=1; stopwatch! max(s1,s2); IF all_here -> break FI; select_soldier(s1) ; safe_to_unsafe!s1 od

18 active proctype timer(){ end: do :: stopwatch? 0 ->atomic{time=time+5 ; STIME} :: stopwatch? 1 ->atomic{time=time+10 ; STIME} :: stopwatch? 2 ->atomic{time=time+15 ; STIME} :: stopwatch? 3 ->atomic{time=time+20 ; STIME} od }

19 Macros #define select_soldier(x) \ if \ :: here[0] -> x=0 \ :: here[1] -> x=1 \ :: here[2] -> x=2 \ :: here[3] -> x=3 \ fi; \ here[x] = 0 #define all_gone (!here[0] &&!here[1] &&!here[2] &&!here[3]) #define all_here (here[0] && here[1] && here[2] && here[3]) #define STIME printf("time:%d\n",time) #define IF if :: #define FI :: else fi #define max(x,y) ((x>y)->x : y)

20 How can we get Spin to search and display a solution for the problem? We would like Spin to generate a trace for us that illustrates a solution where the soldiers can get from the unsafe to the safe side in 60 minutes or less. Spin generates counter-example or property-violation traces. Therefore, we need to ask Spin to try to prove that a solution does not exist. If it finds a counterexample, it will illustrate a solution to the soldiers problem. We express the desired property using LTL The question is: what property do we need to write?

21 We want to see that, no matter what, it is possible to guarantee that the variable time will eventually have a value greater than 60. A counter-example to this will yield a solution to the problem. The property is expressed in LTL by the formula Ftime>60 which translates to Promela <>(outoftime) where #define outoftime time>60

22 In jspin Write the LTL formula in the text field provided <>(outoftime) Select Translate. Ensure that Acceptance is selected from the pulldown menu. Ensure that the box labeled Weak fairness is checked. Select Verify. What happens?

23 Let s try again: In the Options menu, select Verify and add the option -DNOREDUCE Select Verify, again. Afterward, in the command line, write spin -t -M soldiers.pml

24 Traffic controller We want to model a controller for a traffic light at a road intersection, with the following characteristics: the traffic flows either from North to South or from East to West; turning is not allowed; there are sensors in each direction to detected waiting vehicles.

25 We want to verify the following properties: Safety there are no collisions Progress each waiting car eventually gets to go Optimality light only turns green if there is traffic

26 We use three variables: bool traffic[2] there is traffic bool light[2] the light is on bool turn alternation between the two roads The sensors: active proctype sensor0() { do ::!traffic[0] -> traffic[0] = 1 :: else -> skip od } active proctype sensor1() { do ::!traffic[1] -> traffic[1] = 1 :: else -> skip od }

27 The controllers active proctype light0() active proctype light1() { { do do :: (turn == 0) -> :: (turn == 1) -> if if :: traffic[0] -> light[0] = 1; :: traffic[1] -> light[1] = 1; light[0] = 0; light[1] = 0; traffic[0] = 0 traffic[1] = 0 fi; fi; turn = 1 turn = 0 :: else -> skip :: else -> skip od od } }

28 The properties: Safety there are no collisions [](!(light[0] && light[1])) Progress each waiting car eventually gets to go []<>(!(traffic[0]) && []<>(!(traffic[1]) Optimality light only turns green if there is traffic []((!light[0] traffic[0]) && (!light[1] traffic[1]))

29 Timeouts proctype watchdog() { timeout -> printf("...\n") } Is enabled when the entire system is deadlocked and sends a message to a reset process.

Formal Specification and Verification

Formal Specification and Verification Formal Specification and Verification Model Checking with Temporal Logic Bernhard Beckert Based on a lecture by Wolfgang Ahrendt and Reiner Hähnle at Chalmers University, Göteborg Formal Specification

More information

Formal Methods for Software Development

Formal Methods for Software Development Formal Methods for Software Development Model Checking with Temporal Logic Wolfgang Ahrendt 21st September 2018 FMSD: Model Checking with Temporal Logic /GU 180921 1 / 37 Model Checking Check whether a

More information

Tool demonstration: Spin

Tool demonstration: Spin Tool demonstration: Spin 1 Spin Spin is a model checker which implements the LTL model-checking procedure described previously (and much more besides). Developed by Gerard Holzmann of Bell Labs Has won

More information

SWEN-220 Mathematical Models of Software. Process Synchronization Critical Section & Semaphores

SWEN-220 Mathematical Models of Software. Process Synchronization Critical Section & Semaphores SWEN-220 Mathematical Models of Software Process Synchronization Critical Section & Semaphores 1 Topics The critical section Synchronization using busy-wait Semaphores 2 The Critical Section Processes

More information

Distributed Systems Programming (F21DS1) SPIN: Formal Analysis I

Distributed Systems Programming (F21DS1) SPIN: Formal Analysis I Distributed Systems Programming (F21DS1) SPIN: Formal Analysis I Andrew Ireland Department of Computer Science School of Mathematical and Computer Sciences Heriot-Watt University Edinburgh Overview Introduce

More information

Computer Lab 1: Model Checking and Logic Synthesis using Spin (lab)

Computer Lab 1: Model Checking and Logic Synthesis using Spin (lab) Computer Lab 1: Model Checking and Logic Synthesis using Spin (lab) Richard M. Murray Nok Wongpiromsarn Ufuk Topcu Calornia Institute of Technology AFRL, 25 April 2012 Outline Spin model checker: modeling

More information

Distributed Systems Programming (F21DS1) SPIN: Formal Analysis II

Distributed Systems Programming (F21DS1) SPIN: Formal Analysis II Distributed Systems Programming (F21DS1) SPIN: Formal Analysis II Andrew Ireland Department of Computer Science School of Mathematical and Computer Sciences Heriot-Watt University Edinburgh Overview Introduce

More information

4/6/2011. Model Checking. Encoding test specifications. Model Checking. Encoding test specifications. Model Checking CS 4271

4/6/2011. Model Checking. Encoding test specifications. Model Checking. Encoding test specifications. Model Checking CS 4271 Mel Checking LTL Property System Mel Mel Checking CS 4271 Mel Checking OR Abhik Roychoudhury http://www.comp.nus.edu.sg/~abhik Yes No, with Counter-example trace 2 Recap: Mel Checking for mel-based testing

More information

Model-Checking Concurrent Systems. The Model Checker Spin. The Model Checker Spin. Wolfgang Schreiner

Model-Checking Concurrent Systems. The Model Checker Spin. The Model Checker Spin. Wolfgang Schreiner Model-Checking Concurrent Systems Wolfgang Schreiner Wolfgang.Schreiner@risc.jku.at Research Institute for Symbolic Computation (RISC) Johannes Kepler University, Linz, Austria http://www.risc.jku.at 1.

More information

Applications of Formal Verification

Applications of Formal Verification Applications of Formal Verification Model Checking: Introduction to PROMELA Bernhard Beckert Mattias Ulbrich SS 2017 KIT INSTITUT FÜR THEORETISCHE INFORMATIK KIT University of the State of Baden-Württemberg

More information

Software Engineering using Formal Methods

Software Engineering using Formal Methods Software Engineering using Formal Methods Introduction to Promela Wolfgang Ahrendt 03 September 2015 SEFM: Promela /GU 150903 1 / 36 Towards Model Checking System Model Promela Program byte n = 0; active

More information

Applications of Formal Verification

Applications of Formal Verification Applications of Formal Verification Model Checking: Introduction to PROMELA Prof. Dr. Bernhard Beckert Dr. Vladimir Klebanov SS 2010 KIT INSTITUT FÜR THEORETISCHE INFORMATIK KIT University of the State

More information

Model-Checking Concurrent Systems

Model-Checking Concurrent Systems Model-Checking Concurrent Systems Wolfgang Schreiner Wolfgang.Schreiner@risc.jku.at Research Institute for Symbolic Computation (RISC) Johannes Kepler University, Linz, Austria http://www.risc.jku.at Wolfgang

More information

Patrick Trentin Formal Methods Lab Class, March 03, 2017

Patrick Trentin  Formal Methods Lab Class, March 03, 2017 Spin: Introduction Patrick Trentin patrick.trentin@unitn.it http://disi.unitn.it/trentin Formal Methods Lab Class, March 03, 2017 These slides are derived from those by Stefano Tonetta, Alberto Griggio,

More information

Formal Specification and Verification

Formal Specification and Verification Formal Specification and Verification Introduction to Promela Bernhard Beckert Based on a lecture by Wolfgang Ahrendt and Reiner Hähnle at Chalmers University, Göteborg Formal Specification and Verification:

More information

Applications of Formal Verification

Applications of Formal Verification Applications of Formal Verification Model Checking: Introduction to PROMELA Prof. Dr. Bernhard Beckert Dr. Vladimir Klebanov SS 2012 KIT INSTITUT FÜR THEORETISCHE INFORMATIK KIT University of the State

More information

Software Engineering using Formal Methods

Software Engineering using Formal Methods Software Engineering using Formal Methods Introduction to Promela Wolfgang Ahrendt & Richard Bubel & Reiner Hähnle & Wojciech Mostowski 31 August 2011 SEFM: Promela /GU 110831 1 / 35 Towards Model Checking

More information

Automated Reasoning. Model Checking with SPIN (II)

Automated Reasoning. Model Checking with SPIN (II) Automated Reasoning Model Checking with SPIN (II) Alan Bundy page 1 Verifying Global Properties Assertions can be used to verify a property locally For example, place assert(memreturned) at the end of

More information

The Spin Model Checker : Part I/II

The Spin Model Checker : Part I/II The Spin Model Checker : Part I/II Moonzoo Kim CS Dept. KAIST Korea Advanced Institute of Science and Technology Motivation: Tragic Accidents Caused by SW Bugs 2 Cost of Software Errors June 2002 Software

More information

Computer Lab 1: Model Checking and Logic Synthesis using Spin (lab)

Computer Lab 1: Model Checking and Logic Synthesis using Spin (lab) Computer Lab 1: Model Checking and Logic Synthesis using Spin (lab) Richard M. Murray Nok Wongpiromsarn Ufuk Topcu California Institute of Technology EECI 19 Mar 2013 Outline Spin model checker: modeling

More information

Algorithmic Verification. Algorithmic Verification. Model checking. Algorithmic verification. The software crisis (and hardware as well)

Algorithmic Verification. Algorithmic Verification. Model checking. Algorithmic verification. The software crisis (and hardware as well) Algorithmic Verification The software crisis (and hardware as well) Algorithmic Verification Comp4151 Lecture 1-B Ansgar Fehnker Computer become more powerful (Moore s law) The quality of programs cannot

More information

Copyright 2008 CS655 System Modeling and Analysis. Korea Advanced Institute of Science and Technology

Copyright 2008 CS655 System Modeling and Analysis. Korea Advanced Institute of Science and Technology The Spin Model Checker : Part I Copyright 2008 CS655 System Korea Advanced Institute of Science and Technology System Spec. In Promela Req. Spec. In LTL Overview of the Spin Architecture Spin Model pan.c

More information

SPIN, PETERSON AND BAKERY LOCKS

SPIN, PETERSON AND BAKERY LOCKS Concurrent Programs reasoning about their execution proving correctness start by considering execution sequences CS4021/4521 2018 jones@scss.tcd.ie School of Computer Science and Statistics, Trinity College

More information

Model Checking with Automata An Overview

Model Checking with Automata An Overview Model Checking with Automata An Overview Vanessa D Carson Control and Dynamical Systems, Caltech Doyle Group Presentation, 05/02/2008 VC 1 Contents Motivation Overview Software Verification Techniques

More information

INF5140: Specification and Verification of Parallel Systems

INF5140: Specification and Verification of Parallel Systems INF5140: Specification and Verification of Parallel Systems Lecture 09 Defining Correctness Claims Gerar Schneider Department of Informatics University of Oslo INF5140, Spring 2007 Gerar Schneider (Ifi,

More information

Computer Aided Verification 2015 The SPIN model checker

Computer Aided Verification 2015 The SPIN model checker Computer Aided Verification 2015 The SPIN model checker Grigory Fedyukovich Universita della Svizzera Italiana March 11, 2015 Material borrowed from Roberto Bruttomesso Outline 1 Introduction 2 PROcess

More information

Patrick Trentin Formal Methods Lab Class, Feb 26, 2016

Patrick Trentin  Formal Methods Lab Class, Feb 26, 2016 Spin: Introduction Patrick Trentin patrick.trentin@unitn.it http://disi.unitn.it/~trentin Formal Methods Lab Class, Feb 26, 2016 These slides are derived from those by Stefano Tonetta, Alberto Griggio,

More information

Testing Concurrent Programs: Model Checking SPIN. Bengt Jonsson

Testing Concurrent Programs: Model Checking SPIN. Bengt Jonsson Testing Concurrent Programs: Model Checking SPIN Bengt Jonsson Model Checking Section Weeks 15 and 16. Goal: Understand and use the basics of Model checking, using state space exploration Modeling parallel

More information

Formal Verification: Practical Exercise Model Checking with NuSMV

Formal Verification: Practical Exercise Model Checking with NuSMV Formal Verification: Practical Exercise Model Checking with NuSMV Jacques Fleuriot Daniel Raggi Semester 2, 2017 This is the first non-assessed practical exercise for the Formal Verification course. You

More information

The SPIN Model Checker

The SPIN Model Checker The SPIN Model Checker Metodi di Verifica del Software Andrea Corradini GianLuigi Ferrari Lezione 3 2011 Slides per gentile concessione di Gerard J. Holzmann 2 the do-statement do :: guard 1 -> stmnt 1.1

More information

Multi-Threaded System int x, y, r; int *p, *q, *z; int **a; EEC 421/521: Software Engineering. Thread Interleaving SPIN. Model Checking using SPIN

Multi-Threaded System int x, y, r; int *p, *q, *z; int **a; EEC 421/521: Software Engineering. Thread Interleaving SPIN. Model Checking using SPIN EEC 421/521: Software Engineering Model Checking using SPIN 4/29/08 EEC 421/521: Software Engineering 1 Multi-Threaded System int x, y, r; int *p, *q, *z; int **a; thread_1(void) /* initialize p, q, and

More information

Proving Dekker with SPIN and PROMELA

Proving Dekker with SPIN and PROMELA 15-410...fairness disabled... Proving Dekker with SPIN and PROMELA Joshua Wise With help from Greg Hartman L36_SPIN 1 Synchronization Project 4 due Wednesday Everyone having fun? Kernel interviews If you

More information

Model Requirements and JAVA Programs MVP 2 1

Model Requirements and JAVA Programs MVP 2 1 Model Requirements and JAVA Programs MVP 2 1 Traditional Software The Waterfall Model Problem Area Development Analysis REVIEWS Design Implementation Costly wrt time and money. Errors are found too late

More information

SPIN: Part /614 Bug Catching: Automated Program Verification. Sagar Chaki November 12, Carnegie Mellon University

SPIN: Part /614 Bug Catching: Automated Program Verification. Sagar Chaki November 12, Carnegie Mellon University SPIN: Part 1 15-414/614 Bug Catching: Automated Program Verification Sagar Chaki November 12, 2012 What is This All About? Spin On-the-fly verifier developed at Bell-labs by Gerard Holzmann and others

More information

Network Protocol Design and Evaluation

Network Protocol Design and Evaluation Network Protocol Design and Evaluation 05 - Validation, Part III Stefan Rührup Summer 2009 Overview In the first parts of this chapter: Validation models in Promela Defining and checking correctness claims

More information

Design and Analysis of Distributed Interacting Systems

Design and Analysis of Distributed Interacting Systems Design and Analysis of Distributed Interacting Systems Lecture 5 Linear Temporal Logic (cont.) Prof. Dr. Joel Greenyer May 2, 2013 (Last Time:) LTL Semantics (Informally) LTL Formulae are interpreted on

More information

Formal Verification by Model Checking

Formal Verification by Model Checking Formal Verication by Model Checking Jonathan Aldrich Carnegie Mellon University Based on slides developed by Natasha Sharygina 17-654/17-754: Analysis of Software Artacts Spring 2006 1 CTL Model Checking

More information

MP 6 Modeling in Promela and SPIN

MP 6 Modeling in Promela and SPIN MP 6 Modeling in Promela and SPIN CS 477 Spring 2018 Revision 1.0 Assigned April 23, 2018 Due May 2, 2018, 9:00 PM Extension 48 hours (penalty 20% of total points possible) 1 Change Log 1.0 Initial Release.

More information

The SPIN Model Checker

The SPIN Model Checker The SPIN Model Checker Metodi di Verifica del Software Andrea Corradini Lezione 1 2013 Slides liberamente adattate da Logic Model Checking, per gentile concessione di Gerard J. Holzmann http://spinroot.com/spin/doc/course/

More information

SPIN. Carla Ferreira.

SPIN. Carla Ferreira. SPIN Carla Ferreira http://www.spinroot.com/spin/man/intro.html Introduction PROMELA (PROcess MEta LAnguage) is the input language of SPIN (Simple Promela Interpreter) Inspired by: C and CSP Describes

More information

Model checking Timber program. Paweł Pietrzak

Model checking Timber program. Paweł Pietrzak Model checking Timber program Paweł Pietrzak 1 Outline Background on model checking (spam?) The SPIN model checker An exercise in SPIN - model checking Timber Deriving finite models from Timber programs

More information

Distributed Systems Programming (F21DS1) SPIN: Simple Promela INterpreter

Distributed Systems Programming (F21DS1) SPIN: Simple Promela INterpreter Distributed Systems Programming (F21DS1) SPIN: Simple Promela INterpreter Andrew Ireland Department of Computer Science School of Mathematical and Computer Sciences Heriot-Watt University Edinburgh Overview

More information

INF672 Protocol Safety and Verification. Karthik Bhargavan Xavier Rival Thomas Clausen

INF672 Protocol Safety and Verification. Karthik Bhargavan Xavier Rival Thomas Clausen INF672 Protocol Safety and Verication Karthik Bhargavan Xavier Rival Thomas Clausen 1 Course Outline Lecture 1 [Today, Sep 15] Introduction, Motivating Examples Lectures 2-4 [Sep 22,29, Oct 6] Network

More information

Formal Methods for Software Development

Formal Methods for Software Development Formal Methods for Software Development Verification with Spin Wolfgang Ahrendt 07 September 2018 FMSD: Spin /GU 180907 1 / 34 Spin: Previous Lecture vs. This Lecture Previous lecture Spin appeared as

More information

Spin: Overview of PROMELA

Spin: Overview of PROMELA Spin: Overview of PROMELA Patrick Trentin patrick.trentin@unitn.it http://disi.unitn.it/trentin Formal Methods Lab Class, March 10, 2017 These slides are derived from those by Stefano Tonetta, Alberto

More information

Behavioural Equivalences and Abstraction Techniques. Natalia Sidorova

Behavioural Equivalences and Abstraction Techniques. Natalia Sidorova Behavioural Equivalences and Abstraction Techniques Natalia Sidorova Part 1: Behavioural Equivalences p. p. The elevator example once more How to compare this elevator model with some other? The cabin

More information

CS5232 Formal Specification and Design Techniques. Using PAT to verify the Needham-Schroeder Public Key Protocol

CS5232 Formal Specification and Design Techniques. Using PAT to verify the Needham-Schroeder Public Key Protocol CS5232 Formal Specification and Design Techniques Using PAT to verify the Needham-Schroeder Public Key Protocol Semester 2, AY 2008/2009 1/37 Table of Contents 1. Project Introduction 3 2. Building the

More information

Linear Temporal Logic. Model Checking and. Based on slides developed by Natasha Sharygina. Carnegie Mellon University.

Linear Temporal Logic. Model Checking and. Based on slides developed by Natasha Sharygina. Carnegie Mellon University. Model Checking and Linear Temporal Logic Jonathan Aldrich Carnegie Mellon University Based on slides developed by Natasha Sharygina 17-654: Analysis of Software Artifacts 1 Formal Verification by Model

More information

FORMAL METHODS IN NETWORKING COMPUTER SCIENCE 598D, SPRING 2010 PRINCETON UNIVERSITY LIGHTWEIGHT MODELING IN PROMELA/SPIN AND ALLOY

FORMAL METHODS IN NETWORKING COMPUTER SCIENCE 598D, SPRING 2010 PRINCETON UNIVERSITY LIGHTWEIGHT MODELING IN PROMELA/SPIN AND ALLOY FORMAL METHODS IN NETWORKING COMPUTER SCIENCE 598D, SPRING 2010 PRINCETON UNIVERSITY LIGHTWEIGHT MODELING IN PROMELA/SPIN AND ALLOY Pamela Zave AT&T Laboratories Research Florham Park, New Jersey, USA

More information

A Tutorial on Model Checker SPIN

A Tutorial on Model Checker SPIN A Tutorial on Model Checker SPIN Instructor: Hao Zheng Department of Computer Science and Engineering University of South Florida Tampa, FL 33620 Email: haozheng@usf.edu Phone: (813)974-4757 Fax: (813)974-5456

More information

SPIN: Introduction and Examples

SPIN: Introduction and Examples SPIN: Introduction and Examples Alessandra Giordani agiordani@disi.unitn.it http://disi.unitn.it/~agiordani Formal Methods Lab Class, September 28, 2014 *These slides are derived from those by Stefano

More information

Deadlock. Disclaimer: some slides are adopted from Dr. Kulkarni s and book authors slides with permission 1

Deadlock. Disclaimer: some slides are adopted from Dr. Kulkarni s and book authors slides with permission 1 Deadlock Disclaimer: some slides are adopted from Dr. Kulkarni s and book authors slides with permission 1 Recap: Synchronization Race condition A situation when two or more threads read and write shared

More information

MINIX 3 Process Analysis

MINIX 3 Process Analysis Xander Damen Albert Gerritsen Eelis van der Weegen 2010-01-18 Introduction Our project: process analysis of MINIX 3. Outline: 1 methodology 2 subsystem & tool selection 3 the MINIX 3 scheduler 4 the model

More information

System Correctness. EEC 421/521: Software Engineering. System Correctness. The Problem at Hand. A system is correct when it meets its requirements

System Correctness. EEC 421/521: Software Engineering. System Correctness. The Problem at Hand. A system is correct when it meets its requirements System Correctness EEC 421/521: Software Engineering A Whirlwind Intro to Software Model Checking A system is correct when it meets its requirements a design without requirements cannot be right or wrong,

More information

CS477 Formal Software Development Methods / 39

CS477 Formal Software Development Methods / 39 CS477 Formal Software Development Methods 2112 SC, UIUC egunter@illinois.edu http://courses.engr.illinois.edu/cs477 SPIN Beginners Tutorial April 11, 2018 Hello World /* A "Hello World" Promela model for

More information

Formal Methods in Software Engineering. Lecture 07

Formal Methods in Software Engineering. Lecture 07 Formal Methods in Software Engineering Lecture 07 What is Temporal Logic? Objective: We describe temporal aspects of formal methods to model and specify concurrent systems and verify their correctness

More information

Deadlock. Disclaimer: some slides are adopted from Dr. Kulkarni s and book authors slides with permission 1

Deadlock. Disclaimer: some slides are adopted from Dr. Kulkarni s and book authors slides with permission 1 Deadlock Disclaimer: some slides are adopted from Dr. Kulkarni s and book authors slides with permission 1 Recap: Synchronization Race condition A situation when two or more threads read and write shared

More information

LTL Reasoning: How It Works

LTL Reasoning: How It Works Distributed Systems rogramming F21DS1 LTL Reasoning: How It Works Andrew Ireland School of Mathematical and Computer Sciences Heriot-Watt University Edinburgh Distributed Systems rogramming F21DS1 2 Overview

More information

Deadlock. Disclaimer: some slides are adopted from Dr. Kulkarni s and book authors slides with permission 1

Deadlock. Disclaimer: some slides are adopted from Dr. Kulkarni s and book authors slides with permission 1 Deadlock Disclaimer: some slides are adopted from Dr. Kulkarni s and book authors slides with permission 1 Recap: Synchronization Race condition A situation when two or more threads read and write shared

More information

The Spin Model Checker : Part I. Moonzoo Kim KAIST

The Spin Model Checker : Part I. Moonzoo Kim KAIST The Spin Model Checker : Part I Moonzoo Kim KAIST Hierarchy of SW Coverage Criteria Complete Value Coverage CVC (SW) Model checking Complete Path Coverage CPC Concolic testing All-DU-Paths Coverage ADUP

More information

THE MODEL CHECKER SPIN

THE MODEL CHECKER SPIN THE MODEL CHECKER SPIN Shin Hong, KAIST 17 th April,2007 1/33 Contents Introduction PROMELA Linear Temporal Logic Automata-theoretic software verification Example : Simple Elevator 2 SPIN is a software

More information

Lecture 3 SPIN and Promela

Lecture 3 SPIN and Promela Lecture 3 SPIN and Promela 1 What is SPIN(Simple Promela INterpreter) A tool for analyzing mels of concurrent systems Mels described in Promela Language with concurrent processes Communication via shared

More information

Design of Internet Protocols:

Design of Internet Protocols: CSCI 234 Design of Internet Protocols: George Blankenship George Blankenship 1 Outline Verication and Validation History and motivation Spin Promela language Promela model George Blankenship 2 Verication

More information

Finite State Verification. CSCE Lecture 14-02/25/2016

Finite State Verification. CSCE Lecture 14-02/25/2016 Finite State Verification CSCE 747 - Lecture 14-02/25/2016 So, You Want to Perform Verification... You have a property that you want your program to obey. Great! Let s write some tests! Does testing guarantee

More information

CoSc 450: Programming Paradigms. The Critical Section Problem

CoSc 450: Programming Paradigms. The Critical Section Problem CoSc 450: Programming Paradigms 03 The Critical Section Problem Algorithm 3.1: Critical section problem global variables p q local variables local variables loop forever loop forever non-critical section

More information

The Design of a Distributed Model Checking Algorithm for Spin

The Design of a Distributed Model Checking Algorithm for Spin The Design of a Distributed Model Checking Algorithm for Spin Gerard J. Holzmann http://eis.jpl.nasa.gov/lars http://spinroot.com/gerard/ Presented at FMCAD 2006, San Jose, California November 14, 2006

More information

Using Spin to Help Teach Concurrent Programming

Using Spin to Help Teach Concurrent Programming Using Spin to Help Teach Concurrent Programming John Regehr May 1, 1998 1 Introduction and Motivation Writing correct concurrent programs is very difficult; race conditions, deadlocks, and livelocks can

More information

Introduction to Linear-Time Temporal Logic. CSE 814 Introduction to LTL

Introduction to Linear-Time Temporal Logic. CSE 814 Introduction to LTL Introduction to Linear-Time Temporal Logic CSE 814 Introduction to LTL 1 Outline Motivation for TL in general Types of properties to be expressed in TL Structures on which LTL formulas are evaluated Syntax

More information

Spin: Overview of PROMELA

Spin: Overview of PROMELA Spin: Overview of PROMELA Patrick Trentin patrick.trentin@unitn.it http://disi.unitn.it/~trentin Formal Methods Lab Class, Mar 04, 2016 These slides are derived from those by Stefano Tonetta, Alberto Griggio,

More information

TOWARDS AUTOMATED VERIFICATION OF WEB SERVICES

TOWARDS AUTOMATED VERIFICATION OF WEB SERVICES TOWARDS AUTOMATED VERIFICATION OF WEB SERVICES Cátia Vaz INESC-ID Lisboa, ISEL-IPL Rua Alves Redol 9, 1000-029 Lisboa cvaz@cc.isel.ipl.pt Carla Ferreira INESC-ID, IST-UTL Rua Alves Redol 9, 1000-029 Lisboa

More information

Finite State Verification. CSCE Lecture 21-03/28/2017

Finite State Verification. CSCE Lecture 21-03/28/2017 Finite State Verification CSCE 747 - Lecture 21-03/28/2017 So, You Want to Perform Verification... You have a property that you want your program to obey. Great! Let s write some tests! Does testing guarantee

More information

G52CON: Concepts of Concurrency

G52CON: Concepts of Concurrency G52CON: Concepts of Concurrency Lecture 11: Semaphores I" Brian Logan School of Computer Science bsl@cs.nott.ac.uk Outline of this lecture" problems with Peterson s algorithm semaphores implementing semaphores

More information

What is SPIN(Simple Promela Interpreter) Material About SPIN. Elements of Promela. Basic Variables and Types. Typical Structure of Promela Model

What is SPIN(Simple Promela Interpreter) Material About SPIN. Elements of Promela. Basic Variables and Types. Typical Structure of Promela Model What is SPIN(Simple Promela Interpreter) Lecture 3 SPIN and Promela A tool for analyzing mels of reactive systems Mels described in Promela Language with concurrent processes, Communication via channels,

More information

CS477 Formal Software Development Methods / 32

CS477 Formal Software Development Methods / 32 CS477 Formal Software Development Methods 2112 SC, UIUC egunter@illinois.edu http://courses.engr.illinois.edu/cs477 SPIN Beginners Tutorial April 13, 2018 Assertion Violation: mutextwrong1.pml bit flag;

More information

Formal modelling and verification in UPPAAL

Formal modelling and verification in UPPAAL Budapest University of Technology and Economics Department of Measurement and Information Systems Fault Tolerant Systems Research Group Critical Embedded Systems Formal modelling and verification in UPPAAL

More information

Distributed Systems Programming (F21DS1) Formal Verification

Distributed Systems Programming (F21DS1) Formal Verification Distributed Systems Programming (F21DS1) Formal Verification Andrew Ireland Department of Computer Science School of Mathematical and Computer Sciences Heriot-Watt University Edinburgh Overview Focus on

More information

Sliced Path Prefixes: An Effective Method to Enable Refinement Selection

Sliced Path Prefixes: An Effective Method to Enable Refinement Selection FORTE '15 Sliced Path Prefixes: An Effective Method to Enable Refinement Selection Dirk Beyer, Stefan Löwe, Philipp Wendler SoSy-Lab Software Systems We want Refinement Selection!!! Because straight-forward

More information

On Nested Depth First Search

On Nested Depth First Search DIMACS Series in Discrete Mathematics and Theoretical Computer Science Volume 32, 1997 On Nested Depth First Search Gerard J. Holzmann, Doron Peled, and Mihalis Yannakakis The SPIN. ABSTRACT. We show in

More information

Operating Systems 2010/2011

Operating Systems 2010/2011 Operating Systems 2010/2011 Blocking and locking (with figures from Bic & Shaw) Johan Lukkien 1 Blocking & locking Blocking: waiting for a certain condition to become true Starvation: unpredictable, even

More information

How to Verify a CSP Model? February 28, 2009

How to Verify a CSP Model? February 28, 2009 How to Verify a CSP Model? February 28, 2009 1 Previously Given a process, a Labeled Transition System can be built by repeatedly applying the operational semantics. Given, Alice Bob Fork1 Fork2 = Alice.get.fork

More information

Coordination 1. To do. Mutual exclusion Election algorithms Next time: Global state. q q q

Coordination 1. To do. Mutual exclusion Election algorithms Next time: Global state. q q q Coordination 1 To do q q q Mutual exclusion Election algorithms Next time: Global state Coordination and agreement in US Congress 1798-2015 Process coordination How can processes coordinate their action?

More information

Research Collection. Formal background and algorithms. Other Conference Item. ETH Library. Author(s): Biere, Armin. Publication Date: 2001

Research Collection. Formal background and algorithms. Other Conference Item. ETH Library. Author(s): Biere, Armin. Publication Date: 2001 Research Collection Other Conference Item Formal background and algorithms Author(s): Biere, Armin Publication Date: 2001 Permanent Link: https://doi.org/10.3929/ethz-a-004239730 Rights / License: In Copyright

More information

CSC2108: Automated Verification Assignment 1 - Solutions

CSC2108: Automated Verification Assignment 1 - Solutions 8 CSC218: Automated Verification Assignment 1 - Solutions 1. Solve the following problem: Use the definition of between states and CTL formulas to explain why means that is true infinitely often along

More information

The Deadlock Problem. A set of blocked processes each holding a resource and waiting to acquire a resource held by another process in the set.

The Deadlock Problem. A set of blocked processes each holding a resource and waiting to acquire a resource held by another process in the set. Deadlock The Deadlock Problem A set of blocked processes each holding a resource and waiting to acquire a resource held by another process in the set Example semaphores A and B, initialized to 1 P 0 P

More information

Software Model Checking. Xiangyu Zhang

Software Model Checking. Xiangyu Zhang Software Model Checking Xiangyu Zhang Symbolic Software Model Checking CS510 S o f t w a r e E n g i n e e r i n g Symbolic analysis explicitly explores individual paths, encodes and resolves path conditions

More information

Verifying Safety Property of Lustre Programs: Temporal Induction

Verifying Safety Property of Lustre Programs: Temporal Induction 22c181: Formal Methods in Software Engineering The University of Iowa Spring 2008 Verifying Safety Property of Lustre Programs: Temporal Induction Copyright 2008 Cesare Tinelli. These notes are copyrighted

More information

Propositional Calculus: Boolean Algebra and Simplification. CS 270: Mathematical Foundations of Computer Science Jeremy Johnson

Propositional Calculus: Boolean Algebra and Simplification. CS 270: Mathematical Foundations of Computer Science Jeremy Johnson Propositional Calculus: Boolean Algebra and Simplification CS 270: Mathematical Foundations of Computer Science Jeremy Johnson Propositional Calculus Topics Motivation: Simplifying Conditional Expressions

More information

Introduction to Model Checking

Introduction to Model Checking Introduction to Model Checking René Thiemann Institute of Computer Science University of Innsbruck WS 2007/2008 RT (ICS @ UIBK) week 4 1/23 Outline Promela - Syntax and Intuitive Meaning Promela - Formal

More information

Applicant. LLC Service. LAN Segment

Applicant. LLC Service. LAN Segment Verication of Group Address Registration Protocol using PROMELA and SPIN Tadashi Nakatani Fuchu Works, Toshiba Corporation, Japan February 16, 1997 Abstract This paper demonstrates robustness and eectiveness

More information

Concurrent & Distributed 7Systems Safety & Liveness. Uwe R. Zimmer - The Australian National University

Concurrent & Distributed 7Systems Safety & Liveness. Uwe R. Zimmer - The Australian National University Concurrent & Distributed 7Systems 2017 Safety & Liveness Uwe R. Zimmer - The Australian National University References for this chapter [ Ben2006 ] Ben-Ari, M Principles of Concurrent and Distributed Programming

More information

MODERN OPERATING SYSTEMS. Third Edition ANDREW S. TANENBAUM. Chapter 6 Deadlocks

MODERN OPERATING SYSTEMS. Third Edition ANDREW S. TANENBAUM. Chapter 6 Deadlocks MODERN OPERATING SYSTEMS Third Edition ANDREW S. TANENBAUM Chapter 6 Deadlocks Preemptable and Nonpreemptable Resources Sequence of events required to use a resource: 1. Request the resource. 2. Use the

More information

Network Protocol Design and Evaluation

Network Protocol Design and Evaluation Network Protocol Design and Evaluation 05 - Validation, Part I Stefan Rührup Summer 2009 Overview In the last lectures: Specification of protocols and data/message formats In this chapter: Building a validation

More information

What is SPIN(Simple Promela Interpreter) Elements of Promela. Material About SPIN. Basic Variables and Types. Typical Structure of Promela Model

What is SPIN(Simple Promela Interpreter) Elements of Promela. Material About SPIN. Basic Variables and Types. Typical Structure of Promela Model What is SPIN(Simple Promela Interpreter) Lecture XX SPIN and Promela A tool for analyzing mels of reactive systems Mels described in Promela Language with concurrent processes, Communication via channels,

More information

Formal Verification of Process Communications in Operational Flight Program for a Small-Scale Unmanned Helicopter

Formal Verification of Process Communications in Operational Flight Program for a Small-Scale Unmanned Helicopter Formal Verication of Process Communications in Operational Flight Program for a Small-Scale Unmanned Helicopter Dong-Ah Lee 1, Junbeom Yoo 2 and Doo-Hyun Kim 3 1, 2 School of Computer Science and Engineering

More information

Planning: Wrap up CSP Planning Logic: Intro

Planning: Wrap up CSP Planning Logic: Intro Planning: Wrap up CSP Planning Logic: Intro Alan Mackworth UBC CS 322 Planning 3 ebruary 25, 2013 Textbook 8.4, 5.1 GAC vs. AC GAC = Generalized Arc Consistency (for k-ary constraints) AC = Arc Consistency

More information

Safety and liveness for critical sections

Safety and liveness for critical sections Safety and liveness for critical sections! At most k threads are concurrently in the critical section A. Safety B. Liveness C. Both! A thread that wants to enter the critical section will eventually succeed

More information

COMP 3713 Operating Systems Slides Part 3. Jim Diamond CAR 409 Jodrey School of Computer Science Acadia University

COMP 3713 Operating Systems Slides Part 3. Jim Diamond CAR 409 Jodrey School of Computer Science Acadia University COMP 3713 Operating Systems Slides Part 3 Jim Diamond CAR 409 Jodrey School of Computer Science Acadia University Acknowledgements These slides borrow from those prepared for Operating System Concepts

More information

7.3.3 Same Inputs in Antecedent and Consequent

7.3.3 Same Inputs in Antecedent and Consequent Formal Verification Using Assertions 249 There are some special scenarios in which the user may want to intentionally toggle the reset signal during a session. This may be needed to check conditions such

More information

Lecture 10: Nested Depth First Search, Counter- Example Generation Revisited, Bit-State Hashing, On-The-Fly Model Checking

Lecture 10: Nested Depth First Search, Counter- Example Generation Revisited, Bit-State Hashing, On-The-Fly Model Checking CS 267: Automated Verification Lecture 10: Nested Depth First Search, Counter- Example Generation Revisited, Bit-State Hashing, On-The-Fly Model Checking Instructor: Tevfik Bultan Buchi Automata Language

More information

Operating Systems 2006/2007

Operating Systems 2006/2007 Operating Systems 2006/2007 Blocking and locking Johan Lukkien 1 Blocking & locking Blocking: waiting for a certain condition to become true Starvation: unpredictable, even infinite blocking times the

More information